e9705e40b7
feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing
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Complete cross-layer upgrade from 1024-pt/64-bin to 2048-pt/512-bin FFT:
FPGA RTL (14+ modules):
- radar_params.vh: FFT_SIZE=2048, RANGE_BINS=512, 9-bit range, 6-bit stream
- fft_engine.v: 2048-pt FFT with XPM BRAM
- chirp_memory_loader_param.v: 2 segments x 2048 (was 4 x 1024)
- matched_filter_multi_segment.v: BRAM inference for overlap_cache, explicit ov_waddr
- mti_canceller.v: BRAM inference for prev_i/q arrays (was fabric FFs)
- doppler_processor.v: 16384-deep memory, 14-bit addressing
- cfar_ca.v: 512 rows, indentation fix
- radar_receiver_final.v: rising-edge detector for frame_complete, 11-bit sample_addr
- range_bin_decimator.v: 512 output bins
- usb_data_interface_ft2232h.v: bulk per-frame with Manhattan magnitude
- radar_mode_controller.v: XOR edge detector for toggle signals
- rx_gain_control.v: updated for new bin count
Python GUI + Protocol (8 files):
- radar_protocol.py: 512-bin bulk frame parser, LSB-first bitmap
- GUI_V65_Tk.py, v7/*.py: updated for 512 bins, 6m range resolution
Golden data + tests:
- All .hex/.csv/.npy golden references regenerated for 2048/512
- fft_twiddle_2048.mem added
- Deleted stale seg2/seg3 chirp mem files
- 9 new bulk frame cross-layer tests, deleted 6 stale per-sample tests
- Deleted stale tb_cross_layer_ft2232h.v and dead contract_parser functions
- Updated validate_mem_files.py for 2048/2-segment config
MCU: RadarSettings.cpp max_distance/map_size 1536->3072
All 4 CI jobs pass: 285 tests, 0 failures, 0 skips
2026-04-16 17:27:55 +05:45
e8b495ce6f
feat: CI test suite phases A+B, WaveformConfig separation, dead golden code cleanup
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- Phase A: Remove self-blessing golden test from FPGA regression, wire
MF co-sim (4 scenarios) into run_regression.sh, add opcode count guards
to cross-layer tests (+3 tests)
- Phase B: Add radar_params.vh parser and architectural param consistency
tests (+7 tests), add banned stale-value pattern scanner (+1 test)
- Separate WaveformConfig.range_resolution_m (physical, bandwidth-dependent)
from bin_spacing_m (sample-rate dependent); rename all callers
- Remove 151 lines of dead golden generate/compare code from
tb_radar_receiver_final.v; testbench now runs structural + bounds only
- Untrack generated MF co-sim CSV files, gitignore tb/golden/ directory
CI: 256 tests total (168 python + 40 cross-layer + 27 FPGA + 21 MCU), all green
2026-04-15 15:44:04 +05:45
05d1f8c26b
chore: gitignore sim artifacts (doppler CSV/mem) and MCU test binaries
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- Untrack rx_final_doppler_out.csv and golden_doppler.mem (regenerated by tests)
- Add 6 missing MCU test binaries to tests/.gitignore
2026-04-15 15:44:04 +05:45
e78e36a635
Add UART diagnostic capture tool for board-day bring-up
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- Python/pyserial script captures STM32 USART3 DIAG output (115200 8N1)
- Auto-detects serial port on macOS (ST-Link VCP, FTDI, CH340, CP210x)
- Color-coded terminal output by subsystem and severity
- Simultaneous logging to timestamped file in logs/
- Filtering by subsystem tag (--filter LO,PA) or severity (--errors-only)
- Parses all DIAG macro formats: DIAG, DIAG_WARN, DIAG_ERR, DIAG_SECTION
- Capture stats summary on exit (line counts by subsystem, error/warning totals)
- logs/ added to .gitignore
2026-03-19 16:32:54 +02:00
bb7a7390c3
Clean gitignore after root artifact reorganization
2026-03-18 22:08:02 +02:00
b879aefe6d
Ignore local cleanup artifacts and generated report directories
2026-03-18 22:04:44 +02:00
fd6094ee9e
Fix P0/P1 RTL bugs found during pre-hardware audit
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P0-1: nco_400m_enhanced.v — DSP48E1 OPMODE corrected from PCIN to P
feedback (was routing stale cascade data into accumulator)
P0-2: radar_receiver_final.v — removed same-clock CDC that corrupted
ADC data path between ad9484_interface and DDC
P1-5: fir_lowpass.v — fixed zero replication count in coefficient
symmetric extension ({0{1'b0}} is empty, now uses explicit 0)
Also updates .gitignore to exclude debug/scratch artifacts.
All 30+ testbenches pass (unit, co-sim, integration).
2026-03-16 22:24:06 +02:00
f5a3394f23
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
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Implement the 3 modules identified as missing during repo audit:
- matched_filter_processing_chain: behavioral FFT-based pulse compression
- range_bin_decimator: 1024→64 bin decimation with 3 modes + start_bin
- radar_mode_controller: 4-mode beam/chirp controller
Wire radar_mode_controller into radar_receiver_final.v to drive the
previously-undriven use_long_chirp and mc_new_* signals.
Implement start_bin functionality in range_bin_decimator (was dead code
in the original interface contract — now skips N input bins before
decimation for region-of-interest selection).
Add comprehensive testbenches with Tier 1 confidence improvements:
- Golden reference co-simulation (Python FFT → hex → bin comparison)
- Saturation boundary tests (0x7FFF / 0x8000 extremes)
- Reset mid-operation recovery tests
- Valid-gap / stall handling tests
- Mode switching and counter persistence tests
- Accumulator overflow stress tests
Test counts: matched_filter 40/40, range_bin_decimator 55/55,
radar_mode_controller 73/73 — all passing with iverilog -g2001.
2026-03-15 13:37:10 +02:00
558f49cd4a
Add 8 Verilog testbenches with full coverage (144/144 pass)
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Testbenches for: edge_detector (17), nco_400m (20), cic_decimator (14),
fir_lowpass (13), freq_matched_filter (14), ddc_400m full-chain (7),
chirp_controller (39), chirp_contract regression (20).
Includes CSV output data for waveform verification.
Add .gitignore to exclude VCD/VVP build artifacts.
2026-03-15 06:14:11 +02:00
Jason