Jason
60 lines
1.4 KiB
Plaintext
60 lines
1.4 KiB
Plaintext
# Verilog simulation artifacts
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*.vvp
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*.vcd
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# Testbench CSV output (regenerated on each run)
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mf_chain_autocorr.csv
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rbd_mode00_ramp.csv
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rbd_mode01_peak.csv
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rbd_mode10_avg.csv
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rbd_mode10_ramp.csv
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rmc_autoscan.csv
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# Debug / scratch RTL (not part of the design)
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9_Firmware/9_2_FPGA/debug_*.v
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9_Firmware/9_2_FPGA/tb/tb_fft_debug*.v
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9_Firmware/9_2_FPGA/tb/tb_fft_mini*.v
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9_Firmware/9_2_FPGA/tb/tb_bram_debug.v
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# Stray CSV artifacts from unit testbenches
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9_Firmware/9_2_FPGA/cic_*.csv
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9_Firmware/9_2_FPGA/fir_*.csv
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9_Firmware/9_2_FPGA/nco_*.csv
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9_Firmware/9_2_FPGA/ddc_*.csv
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9_Firmware/9_2_FPGA/mf_pipeline_output.csv
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9_Firmware/9_2_FPGA/tb_usb_data_interface.csv
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# Co-sim intermediate CSVs (regenerated by scripts)
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9_Firmware/9_2_FPGA/tb/cosim/rtl_doppler_*.csv
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9_Firmware/9_2_FPGA/tb/cosim/compare_doppler_*.csv
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9_Firmware/9_2_FPGA/tb/cosim/rtl_multiseg_*.csv
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# macOS
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.DS_Store
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# Python
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__pycache__/
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*.pyc
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# Local organization/archival folders (not part of repo source)
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10_docs/
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# Local simulation workspaces and generated outputs
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5_Simulations/generated/
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5_Simulations/aeris10_antenna_sim.py
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5_Simulations/aeris10_radar_sim.py
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# Local FPGA report dumps and scratch constraints
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9_Firmware/9_2_FPGA/reports/
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9_Firmware/9_2_FPGA/synth_only.xdc
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# Local timing closure report snapshots
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build6_reports/
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build7_reports/
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build8_reports/
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build9_reports/
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build10_reports/
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build11_reports/
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build12_reports/
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build13_reports/
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