Fix P0/P1 RTL bugs found during pre-hardware audit

P0-1: nco_400m_enhanced.v — DSP48E1 OPMODE corrected from PCIN to P
      feedback (was routing stale cascade data into accumulator)
P0-2: radar_receiver_final.v — removed same-clock CDC that corrupted
      ADC data path between ad9484_interface and DDC
P1-5: fir_lowpass.v — fixed zero replication count in coefficient
      symmetric extension ({0{1'b0}} is empty, now uses explicit 0)

Also updates .gitignore to exclude debug/scratch artifacts.

All 30+ testbenches pass (unit, co-sim, integration).

.gitignore

@@ -10,6 +10,25 @@ rbd_mode10_avg.csv
 rbd_mode10_ramp.csv
 rmc_autoscan.csv
 
+# Debug / scratch RTL (not part of the design)
+9_Firmware/9_2_FPGA/debug_*.v
+9_Firmware/9_2_FPGA/tb/tb_fft_debug*.v
+9_Firmware/9_2_FPGA/tb/tb_fft_mini*.v
+9_Firmware/9_2_FPGA/tb/tb_bram_debug.v
+
+# Stray CSV artifacts from unit testbenches
+9_Firmware/9_2_FPGA/cic_*.csv
+9_Firmware/9_2_FPGA/fir_*.csv
+9_Firmware/9_2_FPGA/nco_*.csv
+9_Firmware/9_2_FPGA/ddc_*.csv
+9_Firmware/9_2_FPGA/mf_pipeline_output.csv
+9_Firmware/9_2_FPGA/tb_usb_data_interface.csv
+
+# Co-sim intermediate CSVs (regenerated by scripts)
+9_Firmware/9_2_FPGA/tb/cosim/rtl_doppler_*.csv
+9_Firmware/9_2_FPGA/tb/cosim/compare_doppler_*.csv
+9_Firmware/9_2_FPGA/tb/cosim/rtl_multiseg_*.csv
+
 # macOS
 .DS_Store