Add 8 Verilog testbenches with full coverage (144/144 pass)

Testbenches for: edge_detector (17), nco_400m (20), cic_decimator (14),
fir_lowpass (13), freq_matched_filter (14), ddc_400m full-chain (7),
chirp_controller (39), chirp_contract regression (20).

Includes CSV output data for waveform verification.
Add .gitignore to exclude VCD/VVP build artifacts.

.gitignore

@@ -0,0 +1,10 @@
+# Verilog simulation artifacts
+*.vvp
+*.vcd
+
+# macOS
+.DS_Store
+
+# Python
+__pycache__/
+*.pyc