Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

Implement the 3 modules identified as missing during repo audit:
- matched_filter_processing_chain: behavioral FFT-based pulse compression
- range_bin_decimator: 1024→64 bin decimation with 3 modes + start_bin
- radar_mode_controller: 4-mode beam/chirp controller

Wire radar_mode_controller into radar_receiver_final.v to drive the
previously-undriven use_long_chirp and mc_new_* signals.

Implement start_bin functionality in range_bin_decimator (was dead code
in the original interface contract — now skips N input bins before
decimation for region-of-interest selection).

Add comprehensive testbenches with Tier 1 confidence improvements:
- Golden reference co-simulation (Python FFT → hex → bin comparison)
- Saturation boundary tests (0x7FFF / 0x8000 extremes)
- Reset mid-operation recovery tests
- Valid-gap / stall handling tests
- Mode switching and counter persistence tests
- Accumulator overflow stress tests

Test counts: matched_filter 40/40, range_bin_decimator 55/55,
radar_mode_controller 73/73 — all passing with iverilog -g2001.

.gitignore

@@ -2,6 +2,14 @@
 *.vvp
 *.vcd
 
+# Testbench CSV output (regenerated on each run)
+mf_chain_autocorr.csv
+rbd_mode00_ramp.csv
+rbd_mode01_peak.csv
+rbd_mode10_avg.csv
+rbd_mode10_ramp.csv
+rmc_autoscan.csv
+
 # macOS
 .DS_Store