Jason
fd6094ee9e
P0-1: nco_400m_enhanced.v — DSP48E1 OPMODE corrected from PCIN to P
feedback (was routing stale cascade data into accumulator)
P0-2: radar_receiver_final.v — removed same-clock CDC that corrupted
ADC data path between ad9484_interface and DDC
P1-5: fir_lowpass.v — fixed zero replication count in coefficient
symmetric extension ({0{1'b0}} is empty, now uses explicit 0)
Also updates .gitignore to exclude debug/scratch artifacts.
All 30+ testbenches pass (unit, co-sim, integration).
38 lines
906 B
Plaintext
38 lines
906 B
Plaintext
# Verilog simulation artifacts
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*.vvp
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*.vcd
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# Testbench CSV output (regenerated on each run)
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mf_chain_autocorr.csv
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rbd_mode00_ramp.csv
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rbd_mode01_peak.csv
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rbd_mode10_avg.csv
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rbd_mode10_ramp.csv
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rmc_autoscan.csv
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# Debug / scratch RTL (not part of the design)
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9_Firmware/9_2_FPGA/debug_*.v
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9_Firmware/9_2_FPGA/tb/tb_fft_debug*.v
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9_Firmware/9_2_FPGA/tb/tb_fft_mini*.v
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9_Firmware/9_2_FPGA/tb/tb_bram_debug.v
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# Stray CSV artifacts from unit testbenches
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9_Firmware/9_2_FPGA/cic_*.csv
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9_Firmware/9_2_FPGA/fir_*.csv
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9_Firmware/9_2_FPGA/nco_*.csv
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9_Firmware/9_2_FPGA/ddc_*.csv
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9_Firmware/9_2_FPGA/mf_pipeline_output.csv
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9_Firmware/9_2_FPGA/tb_usb_data_interface.csv
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# Co-sim intermediate CSVs (regenerated by scripts)
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9_Firmware/9_2_FPGA/tb/cosim/rtl_doppler_*.csv
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9_Firmware/9_2_FPGA/tb/cosim/compare_doppler_*.csv
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9_Firmware/9_2_FPGA/tb/cosim/rtl_multiseg_*.csv
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# macOS
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.DS_Store
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# Python
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__pycache__/
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*.pyc
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