# Verilog simulation artifacts
*.vvp
*.vcd

# Testbench CSV output (regenerated on each run)
mf_chain_autocorr.csv
rbd_mode00_ramp.csv
rbd_mode01_peak.csv
rbd_mode10_avg.csv
rbd_mode10_ramp.csv
rmc_autoscan.csv

# Debug / scratch RTL (not part of the design)
9_Firmware/9_2_FPGA/debug_*.v
9_Firmware/9_2_FPGA/tb/tb_fft_debug*.v
9_Firmware/9_2_FPGA/tb/tb_fft_mini*.v
9_Firmware/9_2_FPGA/tb/tb_bram_debug.v

# Stray CSV artifacts from unit testbenches
9_Firmware/9_2_FPGA/cic_*.csv
9_Firmware/9_2_FPGA/fir_*.csv
9_Firmware/9_2_FPGA/nco_*.csv
9_Firmware/9_2_FPGA/ddc_*.csv
9_Firmware/9_2_FPGA/mf_pipeline_output.csv
9_Firmware/9_2_FPGA/tb_usb_data_interface.csv

# Co-sim intermediate CSVs (regenerated by scripts)
9_Firmware/9_2_FPGA/tb/cosim/rtl_doppler_*.csv
9_Firmware/9_2_FPGA/tb/cosim/compare_doppler_*.csv
9_Firmware/9_2_FPGA/tb/cosim/rtl_multiseg_*.csv

# macOS
.DS_Store

# Python
__pycache__/
*.pyc