Jason e76925391c Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS) ...

RTL fix: matched_filter_multi_segment.v ST_WAIT_FFT now waits for
processing chain to complete ALL 1024 outputs and return to IDLE
before advancing to next segment. Previously, it transitioned on the
first fft_pc_valid edge, causing the chain to still be outputting
while multi-seg started collecting data for the next segment. This
broke the handshake and caused permanent deadlock after segment 0.

Also fixes forward reference of sample_addr_from_chain in
radar_receiver_final.v (declaration moved before first use).

New files:
- tb/tb_radar_receiver_final.v: P0 integration test for full RX
  pipeline (ADC->DDC->MF->range_bin_decimator->doppler), 10 checks
- tb/ad9484_interface_400m_stub.v: behavioral ADC stub for iverilog

All existing tests still pass: multi-seg 32/32, MF co-sim 3/3,
Doppler co-sim 14/14.

2026-03-16 18:51:08 +02:00

..

tb

Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS)

2026-03-16 18:51:08 +02:00

ad9484_interface_400m.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

cdc_modules.v

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

chirp_lut_init.v

Add files via upload

2026-03-09 00:17:39 +00:00

chirp_memory_loader_param.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

cic_decimator_4x_enhanced.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

cntrt.xdc

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

dac_interface_single.v

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2026-03-09 00:17:39 +00:00

ddc_400m.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

ddc_input_interface.v

Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale

2026-03-16 18:14:06 +02:00

doppler_processor.v

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

edge_detector.v

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2026-03-09 00:17:39 +00:00

fft_1024_forward.v

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2026-03-09 00:17:39 +00:00

fft_1024_inverse.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

fft_engine.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

fft_twiddle_32.mem

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

fft_twiddle_1024.mem

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

fir_lowpass.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

frequency_matched_filter.v

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2026-03-09 00:17:39 +00:00

latency_buffer_2159.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

level_shifter_interface.v

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2026-03-10 01:31:50 +00:00

long_chirp_seg0_i.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg0_q.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg1_i.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg1_q.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg2_i.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg2_q.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg3_i.mem

Add missing long_chirp_seg3 memory files for complete chirp waveform

2026-03-15 18:06:35 +02:00

long_chirp_seg3_q.mem

Add missing long_chirp_seg3 memory files for complete chirp waveform

2026-03-15 18:06:35 +02:00

lvds_to_cmos_400m.v

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2026-03-09 00:17:39 +00:00

matched_filter_multi_segment.v

Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS)

2026-03-16 18:51:08 +02:00

matched_filter_processing_chain.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

nco_400m_enhanced.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

plfm_chirp_controller.v

Fix 6 RTL bugs in FPGA signal processing chain

2026-03-15 06:14:04 +02:00

radar_mode_controller.v

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

radar_receiver_final.v

Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS)

2026-03-16 18:51:08 +02:00

radar_system_tb.v

Create radar_system_tb.v

2026-03-10 01:35:26 +00:00

radar_system_top.v

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

radar_transmitter.v

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2026-03-09 00:17:39 +00:00

range_bin_decimator.v

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

short_chirp_i.mem

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2026-03-09 00:17:39 +00:00

short_chirp_q.mem

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2026-03-09 00:17:39 +00:00

usb_data_interface.v

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

usb_packet_analyzer.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

xfft_32.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00