Jason
eefaf94e9e
Resolves all synthesis errors across attempts 3-11, achieving clean Vivado 2025.2 synthesis on XC7A100T (0 errors, 831 LUTs, 320 FFs, 2 DSPs). radar_receiver_final.v: - reg clk_400m -> wire; output reg -> output wire (x4) - Replace ad9484_lvds_to_cmos_400m with ad9484_interface_400m - Remove duplicate IBUFDS lvds_to_cmos_400m instantiation - Remove non-existent ref_i/ref_q port connections on matched filter - Connect adc_dco_bufg as 400MHz clock source ad9484_interface_400m.v: - Add adc_dco_bufg output port with BUFG instance - Route all internal logic through buffered DCO clock cic_decimator_4x_enhanced.v: - Move reset_monitors handling inside else branch (fixes Vivado ambiguous clock error in both integrator and comb always blocks) - Add separate comb_overflow_latched/comb_saturation_detected regs to eliminate multi-driven nets between integrator and comb blocks - Remove standalone always @(posedge reset_monitors) block - Add output_counter to async reset branch matched_filter_processing_chain.v: - Wrap behavioral FFT body (uses $cos/$sin/$rtoi) in ifdef SIMULATION - Add synthesis stub tying outputs to safe defaults chirp_memory_loader_param.v: - Replace hardcoded Windows paths with relative filenames for all 10 $readmem default parameters latency_buffer_2159.v: - Split single always block into separate BRAM write (synchronous only) and control logic (with async reset) blocks - Fixes Vivado Synth 8-3391: BRAM cannot infer with async reset xfft_32.v (NEW): - Synthesis stub for Xilinx 32-point FFT IP core - AXI-Stream interface with pass-through and 1-cycle latency - Placeholder until real xfft IP is generated
107 lines
3.0 KiB
Verilog
107 lines
3.0 KiB
Verilog
module ad9484_interface_400m (
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// ADC Physical Interface (LVDS)
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input wire [7:0] adc_d_p, // ADC Data P
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input wire [7:0] adc_d_n, // ADC Data N
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input wire adc_dco_p, // Data Clock Output P (400MHz)
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input wire adc_dco_n, // Data Clock Output N (400MHz)
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// System Interface
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input wire sys_clk, // 100MHz system clock (for control only)
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input wire reset_n,
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// Output at 400MHz domain
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output wire [7:0] adc_data_400m, // ADC data at 400MHz
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output wire adc_data_valid_400m, // Valid at 400MHz
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output wire adc_dco_bufg // Buffered 400MHz DCO clock for downstream use
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);
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// LVDS to single-ended conversion
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wire [7:0] adc_data;
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wire adc_dco;
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// IBUFDS for each data bit
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genvar i;
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generate
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for (i = 0; i < 8; i = i + 1) begin : data_buffers
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IBUFDS #(
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.DIFF_TERM("TRUE"),
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.IOSTANDARD("LVDS_25")
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) ibufds_data (
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.O(adc_data[i]),
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.I(adc_d_p[i]),
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.IB(adc_d_n[i])
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);
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end
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endgenerate
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// IBUFDS for DCO
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IBUFDS #(
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.DIFF_TERM("TRUE"),
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.IOSTANDARD("LVDS_25")
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) ibufds_dco (
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.O(adc_dco),
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.I(adc_dco_p),
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.IB(adc_dco_n)
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);
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// Global clock buffer for DCO — used as 400MHz clock throughout receiver
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wire adc_dco_buffered;
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BUFG bufg_dco (
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.I(adc_dco),
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.O(adc_dco_buffered)
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);
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assign adc_dco_bufg = adc_dco_buffered;
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// IDDR for capturing DDR data
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wire [7:0] adc_data_rise; // Data on rising edge
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wire [7:0] adc_data_fall; // Data on falling edge
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genvar j;
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generate
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for (j = 0; j < 8; j = j + 1) begin : iddr_gen
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IDDR #(
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.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
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.INIT_Q1(1'b0),
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.INIT_Q2(1'b0),
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.SRTYPE("SYNC")
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) iddr_inst (
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.Q1(adc_data_rise[j]), // Rising edge data
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.Q2(adc_data_fall[j]), // Falling edge data
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.C(adc_dco_buffered), // 400MHz DCO (buffered)
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.CE(1'b1),
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.D(adc_data[j]),
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.R(1'b0),
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.S(1'b0)
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);
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end
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endgenerate
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// Combine rising and falling edge data to get 400MSPS stream
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reg [7:0] adc_data_400m_reg;
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reg adc_data_valid_400m_reg;
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reg dco_phase;
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always @(posedge adc_dco_buffered or negedge reset_n) begin
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if (!reset_n) begin
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adc_data_400m_reg <= 8'b0;
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adc_data_valid_400m_reg <= 1'b0;
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dco_phase <= 1'b0;
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end else begin
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dco_phase <= ~dco_phase;
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if (dco_phase) begin
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// Output falling edge data (completes the 400MSPS stream)
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adc_data_400m_reg <= adc_data_fall;
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end else begin
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// Output rising edge data
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adc_data_400m_reg <= adc_data_rise;
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end
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adc_data_valid_400m_reg <= 1'b1; // Always valid when ADC is running
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end
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end
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assign adc_data_400m = adc_data_400m_reg;
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assign adc_data_valid_400m = adc_data_valid_400m_reg;
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endmodule |