NawfalMotii79
26 lines
678 B
Verilog
26 lines
678 B
Verilog
module dac_interface_enhanced (
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input wire clk_120m,
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input wire reset_n,
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input wire [7:0] chirp_data,
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input wire chirp_valid,
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output reg [7:0] dac_data,
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output wire dac_clk,
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output wire dac_sleep
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);
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// Register DAC data to meet timing
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always @(posedge clk_120m or negedge reset_n) begin
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if (!reset_n) begin
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dac_data <= 8'd128; // Center value
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end else if (chirp_valid) begin
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dac_data <= chirp_data;
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end else begin
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dac_data <= 8'd128; // Default to center when no chirp
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end
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end
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// DAC clock is same as input clock (120MHz)
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assign dac_clk = clk_120m;
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assign dac_sleep = 1'b0;
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endmodule |