Files

T

Serhii 7eb81668e0 docs: fix FPGA part number, dead paths, and add CONTRIBUTING.md

- README: XC7A100T → XC7A50T to match the XDC correction note
  (constraints/xc7a50t_ftg256.xdc lines 9-11)
- README: replace dead /10_docs/ paths with tracked locations
- README: update contributing section to reference CONTRIBUTING.md
- Add minimal CONTRIBUTING.md with repo layout and PR checklist

Closes #37

2026-04-06 20:06:56 +03:00

1.4 KiB

Raw Blame History

Contributing to PLFM_RADAR (AERIS-10)

Thanks for your interest in the project! This guide covers the basics for getting a change reviewed and merged.

Getting started

Fork the repository and create a topic branch from develop.
Keep generated outputs (Vivado projects, bitstreams, build logs) out of version control — the .gitignore already covers most of these.

Repository layout

Path	Contents
`4_Schematics and Boards Layout/`	KiCad schematics, Gerbers, BOM/CPL
`9_Firmware/9_2_FPGA/`	Verilog RTL, constraints, testbenches, build scripts
`9_Firmware/9_2_FPGA/formal/`	SymbiYosys formal-verification wrappers
`9_Firmware/9_2_FPGA/scripts/`	Vivado TCL build & debug scripts
`9_Firmware/9_3_GUI/`	Python radar dashboard (Tkinter + matplotlib)
`docs/`	GitHub Pages documentation site

Before submitting a pull request

Python — verify syntax: python3 -m py_compile <file>
Verilog — if you have Vivado, run the relevant build*.tcl; if not, note which scripts your change affects
Whitespace — git diff --check should be clean
Keep PRs focused: one logical change per PR is easier to review

Areas where help is especially welcome

See the list in README.md.

Questions?

Open a GitHub issue — that way the discussion is visible to everyone.

1.4 KiB Raw Blame History