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2026-04-02 01:23:36 +01:00
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2026-04-02 01:14:06 +01:00
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2026-04-02 01:03:40 +01:00
cfbe6d2bd4
Fix image paths in README.md
2026-04-02 00:58:22 +01:00
e4fa118b50
Refactor index.html for improved layout and SEO
2026-04-02 00:57:10 +01:00
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2026-04-02 00:56:29 +01:00
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2026-04-02 00:40:14 +01:00
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2026-04-02 00:32:41 +01:00
a6205bd768
Add initial HTML structure for AERIS-10 project
2026-04-02 00:01:44 +01:00
bbd0556200
Delete index.html
2026-04-01 23:53:26 +01:00
86681127b0
Add index.html for AERIS-10 documentation
2026-04-01 22:38:42 +01:00
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2026-03-31 03:21:54 +01:00
484bf0907c
Delete 4_Schematics and Boards Layout/4_6_Schematics/PowerBoard/PowerBoard.brd
2026-03-31 03:21:09 +01:00
f5d89fd710
Fix badge syntax in README.md
2026-03-29 10:50:46 +01:00
a3d0d3fb0c
Fix image formatting in README.md
2026-03-29 08:47:06 +01:00
46c37e17d4
Merge pull request #33 from JJassonn69/fix/staggered-prf-dual16-doppler
2026-03-27 22:09:08 +01:00
a577b7628b
Fix staggered-PRF Doppler processing with dual 16-point FFTs
2026-03-27 23:05:28 +02:00
2a89713c21
Add sponsors section to README
2026-03-27 03:40:34 +01:00
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2026-03-27 03:36:05 +01:00
02eb0b99cf
Delete 14_RADAR_Old_version directory
2026-03-22 01:32:49 +00:00
93c75d19df
Merge pull request #30 from JJassonn69/main
2026-03-21 20:02:05 +00:00
5499827ab7
add TE0713+UMFT601X-B FT601 integration dev bitstream (timing clean)
2026-03-21 20:43:52 +02:00
9dee28ab52
add TE0713 heartbeat bring-up artifact
2026-03-21 20:16:45 +02:00
f9ad30e737
GUI: add self-test UI, fix opcode mismatches (0x16->0x06, 0x04->0x05), update status parsing to 6-word/26-byte format
2026-03-20 20:54:42 +02:00
4985eccbae
Wire self-test results (0x31) to USB status readback path, add fpga_self_test to regression
2026-03-20 20:03:11 +02:00
eb907de3d1
Fix 5 GUI bugs: threaded connect, button toggle, live CFAR/MTI/DC replay, stable heatmap, physical axis labels
2026-03-20 19:36:21 +02:00
f8d80cc96e
Add radar dashboard GUI with replay mode for real ADI CN0566 data visualization, FPGA self-test module, and co-sim npy arrays
2026-03-20 19:02:06 +02:00
7a44f19432
Full-chain MTI+CFAR real-data co-simulation: bit-exact match across all 10247 checkpoints (decim->MTI->Doppler->DC notch->CFAR) using ADI CN0566 data
2026-03-20 17:16:12 +02:00
d5d28e9f1c
Build 25 engineering report: MTI canceller + DC notch timing PASS
2026-03-20 16:59:30 +02:00
ed629e7559
Integrate MTI canceller and DC notch filter for ground clutter removal
2026-03-20 16:39:17 +02:00
eb8e063f37
Change radar system image format to PNG
2026-03-20 05:49:13 +00:00
4801cb81d2
Replace radar system image with updated version
2026-03-20 05:48:20 +00:00
075ae1e77a
Add Build 24 15-point engineering report: timing, utilization, DSP/BRAM breakdown, power, DRC, methodology, congestion, routing, logic levels, build comparison, CFAR cost, verification summary
2026-03-20 05:47:20 +02:00
0b170f7c61
Added Full Diagram
2026-03-20 00:22:45 +00:00
d7fc8c6771
Complete Diagram
2026-03-20 00:17:42 +00:00
0745cc4f48
Pipeline CFAR noise computation: break critical path for timing closure
2026-03-20 05:24:08 +02:00
f71923b67d
Integrate CA-CFAR detector: replace fixed-threshold comparator with adaptive sliding-window CFAR engine (22/22 regression PASS)
2026-03-20 04:57:34 +02:00
e93bc33c6c
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
2026-03-20 04:38:35 +02:00
0b0643619c
Real-data co-simulation: range FFT, Doppler, full-chain all 2048/2048 exact match
2026-03-20 03:19:22 +02:00
b01c507de8
Added Full Diagram
2026-03-20 00:22:45 +00:00
19284ac277
Build 21 docs + TCL fix: WNS +0.156ns, 139 DSP, tag v0.1.4-build21
2026-03-20 02:21:33 +02:00
836bf8fb9f
Complete Diagram
2026-03-20 00:17:42 +00:00
2efab23cd9
Fix Vivado DRC: consolidate data_pending flags into single always block, fix MMCM LOCKED false_path
2026-03-20 01:56:20 +02:00
05efe692ad
Add Build 21 TCL script for FFT opts + E2E RTL fixes Vivado build
2026-03-20 01:48:51 +02:00
a31b4ec484
Update docs for FFT optimizations + E2E test + RTL fixes (19/19 FPGA regression)
2026-03-20 01:46:24 +02:00
0773001708
E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)
2026-03-20 01:45:00 +02:00
a3e1996833
FFT engine: merge SHIFT into WRITE (5→4 cycle butterfly, 20% throughput) + barrel-shift twiddle index
2026-03-20 00:20:59 +02:00
02b3b68e00
Update docs for Gap 2 GUI Settings completion (5 of 7 gaps closed)
2026-03-19 23:58:37 +02:00
7cdfa486e5
Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback (18/18 FPGA, 20/20 MCU)
2026-03-19 23:54:48 +02:00
d2f20f5c15
Update docs for Build 20 (v0.1.3-build20) stable release + Gaps 3-7 status
2026-03-19 23:22:38 +02:00
e5d1b3cfc3
Gap 4 USB Read Path: wire host-to-FPGA command path with toggle CDC, add read path tests
2026-03-19 23:16:26 +02:00
c6103b37de
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
f3bbf77ca1
Gap 3 Safety Architecture: IWDG watchdog, Emergency_Stop PA rail cutoff, temp max, periodic IDQ re-read, emergency state ordering + 5 tests (20/20 pass)
2026-03-19 21:58:39 +02:00
c87dce0d41
Fix chirp memory loader BRAM async reset (Gap 5, REQP-1839/1840)
2026-03-19 21:34:02 +02:00
94ffdb8f77
Add Phase 0 Vivado-style lint to regression runner, update golden data
2026-03-19 21:19:07 +02:00
e8b7cb7584
Fix matched filter synth errors: overlap_copy_count part-select width, add FSM default
2026-03-19 20:53:29 +02:00
3b7afba9d9
Add Build 18 production script with report_exceptions fix for Vivado 2025.2
2026-03-19 20:40:32 +02:00
ed6f79c6d3
FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache
2026-03-19 20:39:01 +02:00
4e3c20066b
Add Build 17 production build script with full 15-point analysis checklist
2026-03-19 17:07:02 +02:00
8ca6d992cb
Update ILA probe script references from Build 13 to Build 16
2026-03-19 17:01:12 +02:00
683e70e784
Update heartbeat dev target: LVCMOS33 for Bank 16 FT601 compat, add comments
2026-03-19 16:47:59 +02:00
e78e36a635
Add UART diagnostic capture tool for board-day bring-up
2026-03-19 16:32:54 +02:00
9b786eb33f
Add FMC-path FT601 XDC for TE0713+TE0701+UMFT601X-B pin mapping
2026-03-19 16:20:56 +02:00
f16d9524e5
Add board-day worksheet and cross-link bring-up docs
2026-03-19 15:25:23 +02:00
0009a74a49
Expand pre-hardware bring-up readiness docs
2026-03-19 14:57:56 +02:00
e62f3cd950
Port validated Build 16 XDC cleanup and sync docs
2026-03-19 14:34:26 +02:00
2763b4be91
Fix CFAR blocking assignment (= to <=) in clocked block, add Build 15 analysis report
2026-03-19 13:22:15 +02:00
3fa26c9e4c
Wire matched filter range profile to USB, replacing Doppler placeholder
2026-03-19 12:33:40 +02:00
f4ff2715ca
Fix matched filter golden test paths (40/40 pass, was 37/40)
2026-03-19 12:20:37 +02:00
463ebef554
CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner
2026-03-19 11:31:46 +02:00
c466021bb6
Fix bugs B12-B17 (PA cal loop, ADC buffer, DIAG_SECTION args, htim3 init, stale annotations) with regression tests
2026-03-19 11:04:53 +02:00
49c9aa28ad
Fix Bug #11 (platform SPI transmit-only), FPGA B2 (chirp BRAM migration), FPGA B3 (DSP48 pipelining)
2026-03-19 10:31:16 +02:00
3b32f67087
Fix SPI bugs #9 (NULL platform_ops) and #10 (missing CS toggle), widen chip_select to uint16_t
2026-03-19 10:00:05 +02:00
397969348e
Fix all 8 firmware bugs with regression tests
2026-03-19 09:42:59 +02:00
b93ee04592
Add .gitignore for test build artifacts, remove committed binaries and .o files
2026-03-19 09:28:48 +02:00
28a66889ad
Add MCU firmware test harness with 8 bug-confirming tests
2026-03-19 09:28:19 +02:00
fda8aab7a2
Add DIAG instrumentation to beamformer, PA, USB, and remaining main.cpp subsystems
2026-03-19 08:57:58 +02:00
bf912067cc
Add bring-up diagnostic instrumentation to clocking/LO subsystem and main init
2026-03-19 08:32:25 +02:00
576fe71150
add contact info
2026-03-19 02:41:57 +00:00
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2026-03-19 01:21:46 +00:00
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2026-03-19 01:15:52 +00:00
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2026-03-19 01:11:32 +00:00
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2026-03-19 01:09:00 +00:00
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2026-03-19 01:02:28 +00:00
1231c7cc94
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2026-03-19 00:47:41 +00:00
b8d912658b
Delete 2_Functional Diagram & Interconnection Matrices/Functional_Diagram.dwg
2026-03-18 23:31:18 +00:00
981bd271fa
Document repository file placement policy for generated artifacts
2026-03-18 22:08:57 +02:00
bb7a7390c3
Clean gitignore after root artifact reorganization
2026-03-18 22:08:02 +02:00
b879aefe6d
Ignore local cleanup artifacts and generated report directories
2026-03-18 22:04:44 +02:00
3755ee6302
Publish Simulation Report v2 aligned to current FPGA baseline
2026-03-18 21:51:08 +02:00
5710f7a83e
Annotate report currency status and flag legacy simulation PDF
2026-03-18 21:46:52 +02:00
cad804c347
Add release notes page keyed to major bring-up commits
2026-03-18 21:41:56 +02:00
94eed1e933
Expand GitHub Pages into full engineering documentation site
2026-03-18 21:40:44 +02:00
fcdd2708bb
Add GitHub Pages docs site for antenna and simulation reports
2026-03-18 21:34:26 +02:00
967ce179eb
Add TE0713/TE0701 alternate dev target for in-stock SoM path
2026-03-18 15:01:55 +02:00
25a739df07
Merge branch 'NawfalMotii79:main' into main
2026-03-18 13:25:26 +02:00
eafa6c7555
removed a short detected by @Mamenace
2026-03-18 02:36:02 +00:00
2453b16975
Add prepeg
2026-03-18 02:33:34 +00:00
NawfalMotii79
Jason