FlintyLemming/PLFM_RADAR
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  • 0ae7b40ff0 Add TE0712/TE0701 split target with dedicated top, XDC, and build flow Jason 2026-03-18 03:57:26 +02:00
  • 12e63b750c Fix ILA probe insertion script: deferred core creation, exact-path net resolution, Vivado 2025.2 MU_CNT minimum Jason 2026-03-18 02:26:09 +02:00
  • f6877aab64 Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts Jason 2026-03-18 01:28:42 +02:00
  • 254c0e6f03 Improve timing margins with targeted datapath register tuning Jason 2026-03-17 23:51:04 +02:00
  • 36ad15247c Split fft_engine FSM: async reset for control, sync reset for DSP/BRAM datapath (Build 11) Jason 2026-03-17 21:40:09 +02:00
  • d8a8532097 Convert CIC comb + FIR delay_line to sync reset for DSP48 absorption (Build 10) Jason 2026-03-17 20:56:42 +02:00
  • 47606a4459 Rewrite integration testbench with golden self-reference comparison + physics bounds checks Jason 2026-03-17 20:56:28 +02:00
  • 1558f17d05 Convert async→sync reset on DSP/BRAM datapath registers for timing closure Jason 2026-03-17 20:11:13 +02:00
  • fcf3999e39 Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions Jason 2026-03-17 19:38:09 +02:00
  • 6fc5a10785 Fix range_bin_decimator overflow guard priority bug: group completion now takes precedence over overflow guard in ST_PROCESS, ensuring all OUTPUT_BINS outputs are emitted when sufficient input samples exist. Split formal property 5 into 5a (upper bound) and 5b (exact count when start_bin=0), added Cover 4 for overflow guard path, reduced BMC depth to 50. Jason 2026-03-17 15:40:55 +02:00
  • 37c8925df0 Merge branch 'NawfalMotii79:main' into main Jason 2026-03-17 13:59:12 +02:00
  • 5fd632bc47 Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator Jason 2026-03-17 13:48:47 +02:00
  • fb59e98737 Add SymbiYosys formal verification for 6 modules, fix 2 doppler bugs Jason 2026-03-17 12:47:22 +02:00
  • 0b52f49135 Added all boards stack NawfalMotii79 2026-03-17 02:26:23 +00:00
  • a9c857c447 Remove 15 dead files, move radar_system_tb.v to tb/ directory Jason 2026-03-17 01:08:12 +02:00
  • 66d4faa9c4 Merge branch 'NawfalMotii79:main' into main Jason 2026-03-17 00:45:42 +02:00
  • 91b9286d1b Add files via upload NawfalMotii79 2026-03-16 22:31:18 +00:00
  • 85e59d6f46 Added missing classes and functions NawfalMotii79 2026-03-16 22:25:10 +00:00
  • 6d27ab7217 Fix NCO XSim test 12: widen zero-crossing range for DSP48E1 quantization Jason 2026-03-16 23:23:06 +02:00
  • ffe36b42dc Fix NCO XSim test 12: add pipeline warmup and sample skip for 1 MHz zero-crossing test Jason 2026-03-16 23:21:25 +02:00
  • 49eb6169b6 Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB Jason 2026-03-16 23:17:38 +02:00
  • af1af3bb91 Fix XDC for timing closure: add hold waivers, remove stale constraints Jason 2026-03-16 23:04:16 +02:00
  • b823d83feb Add new testbenches and fix USB clock forwarding test Jason 2026-03-16 22:24:34 +02:00
  • 1acedf494c Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I Jason 2026-03-16 22:24:22 +02:00
  • fd6094ee9e Fix P0/P1 RTL bugs found during pre-hardware audit Jason 2026-03-16 22:24:06 +02:00
  • f154edbd20 Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001 Jason 2026-03-16 19:53:40 +02:00
  • 17b70bdcff Fix overlap-save: fill full 1024-sample buffer per segment, zero-pad last partial segment Jason 2026-03-16 19:15:23 +02:00
  • 39f78d4349 Fix RTL Bug #3: S_IDLE->S_ACCUMULATE now writes first sample immediately Jason 2026-03-16 19:08:16 +02:00
  • 2db32af1d0 Add .mem file validator: verify FFT twiddle + chirp .mem files against radar parameters (55/56 PASS) Jason 2026-03-16 19:02:45 +02:00
  • e76925391c Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS) Jason 2026-03-16 18:51:08 +02:00
  • a5a5e96a57 Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale Jason 2026-03-16 18:14:06 +02:00
  • 17731dd482 Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites Jason 2026-03-16 18:09:26 +02:00
  • e506a80db5 Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0) Jason 2026-03-16 16:23:01 +02:00
  • baa24fd01e Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation Jason 2026-03-16 16:01:40 +02:00
  • 00fbab6c9d Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations) Jason 2026-03-16 15:02:35 +02:00
  • 692b6a3bfa Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference Jason 2026-03-16 10:25:07 +02:00
  • deb2e81ec4 Merge branch 'main' of https://github.com/JJassonn69/PLFM_RADAR Jason 2026-03-16 01:02:17 +02:00
  • c983a3c705 Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG Jason 2026-03-16 01:02:07 +02:00
  • 653098214c Merge branch 'NawfalMotii79:main' into main Jason 2026-03-16 00:51:55 +02:00
  • a9cd7bab2d Add files via upload NawfalMotii79 2026-03-15 22:25:02 +00:00
  • e0ff3b1bc5 Add files via upload NawfalMotii79 2026-03-15 22:03:54 +00:00
  • 70e8366dc4 Correct contributor name in license section NawfalMotii79 2026-03-15 21:46:03 +00:00
  • 415db19353 Update model name from AERIS-10X to AERIS-10E NawfalMotii79 2026-03-15 21:44:01 +00:00
  • 1e51b739a7 Add missing long_chirp_seg3 memory files for complete chirp waveform Jason 2026-03-15 18:06:35 +02:00
  • ffed7c1623 Fix CDC timing violations: add synchronizers for all inter-clock crossings Jason 2026-03-15 17:58:14 +02:00
  • eefaf94e9e Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis Jason 2026-03-15 17:37:59 +02:00
  • c871281f1e Fix synthesis blockers in 9 RTL files for Vivado compatibility Jason 2026-03-15 14:53:35 +02:00
  • f5a3394f23 Add 3 missing FPGA modules with enhanced testbenches (168/168 pass) Jason 2026-03-15 13:37:10 +02:00
  • 81435f9ff9 Merge branch 'main' of https://github.com/NawfalMotii79/PLFM_RADAR Jason 2026-03-15 06:22:27 +02:00
  • 558f49cd4a Add 8 Verilog testbenches with full coverage (144/144 pass) Jason 2026-03-15 06:14:11 +02:00
  • 76183e2e95 Fix 6 RTL bugs in FPGA signal processing chain Jason 2026-03-15 06:14:04 +02:00
  • 74d5a76abb Merge pull request #7 from walidb212/fix/gy85-i2c-status NawfalMotii79 2026-03-15 01:57:28 +00:00
  • eca26f413d Merge pull request #6 from walidb212/refactor/adar-sequencing-constants NawfalMotii79 2026-03-15 01:56:59 +00:00
  • e212c806d4 Merge pull request #5 from walidb212/fix/gps-transport-status NawfalMotii79 2026-03-15 01:56:16 +00:00
  • 63c0aedc3b Merge pull request #8 from walidb212/fix/gui-settings-validation NawfalMotii79 2026-03-15 00:52:05 +00:00
  • 246d088169 Update README with licensing details NawfalMotii79 2026-03-15 00:39:23 +00:00
  • eed253cab0 Add CERN Open Hardware Licence Version 2 - Permissive NawfalMotii79 2026-03-15 00:34:27 +00:00
  • a4b8a144ed fix(firmware): return gps transport status wb-eugenia 2026-03-13 19:41:45 +01:00
  • 9bb6080a73 fix(firmware): propagate gy85 i2c failures wb-eugenia 2026-03-13 19:38:42 +01:00
  • b1cb897275 refactor(firmware): name adar power sequencing constants wb-eugenia 2026-03-13 19:32:10 +01:00
  • 2d62d4320c fix(gui): validate radar settings before usb send wb-eugenia 2026-03-13 19:28:35 +01:00
  • 7510e31c20 Update image path for AERIS-10 Radar System NawfalMotii79 2026-03-11 02:04:42 +00:00
  • 19bcbba835 Add files via upload NawfalMotii79 2026-03-11 02:02:03 +00:00
  • 4781ab1001 Include radar system image in README NawfalMotii79 2026-03-11 02:01:34 +00:00
  • ea3319353b Add files via upload NawfalMotii79 2026-03-10 23:39:49 +00:00
  • 8896ed3814 Delete 1_Executive Summary directory NawfalMotii79 2026-03-10 23:39:12 +00:00
  • 7b6f93955f Create cntrt.xdc NawfalMotii79 2026-03-10 02:42:15 +00:00
  • a4a9c9ad00 Add files via upload NawfalMotii79 2026-03-10 02:17:36 +00:00
  • 35f1f2bc1d Add files via upload NawfalMotii79 2026-03-10 02:17:16 +00:00
  • 11089dfacd Update GUI_V6_Demo.py NawfalMotii79 2026-03-10 01:55:47 +00:00
  • 90bab6bd64 Create GUI_V6_Demo.py NawfalMotii79 2026-03-10 01:43:19 +00:00
  • a7e55c752f Create usb_packet_analyzer.v NawfalMotii79 2026-03-10 01:36:04 +00:00
  • 220f2e0d0b Create radar_system_tb.v NawfalMotii79 2026-03-10 01:35:26 +00:00
  • 45ad19184c Add files via upload NawfalMotii79 2026-03-10 01:31:50 +00:00
  • 0eb2d9726d Update GUI_versions.txt NawfalMotii79 2026-03-10 01:27:05 +00:00
  • 43ff85e331 Update and rename GUI_V6 to GUI_V6.py NawfalMotii79 2026-03-10 01:26:00 +00:00
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  • d6417fdca7 Add files via upload NawfalMotii79 2026-03-10 01:11:30 +00:00
  • 89f9daabd0 Delete 3_Power Management directory NawfalMotii79 2026-03-10 01:11:04 +00:00
  • b2997ba17a Add files via upload NawfalMotii79 2026-03-10 01:09:49 +00:00
  • 4cb53454ec Update README.md NawfalMotii79 2026-03-09 01:30:03 +00:00
  • caa35890cf Create README.md NawfalMotii79 2026-03-09 01:27:49 +00:00
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  • 30b77d5c6b Delete 7_Components Datasheets and Application notes NawfalMotii79 2026-03-09 00:32:53 +00:00
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