Add Build 24 15-point engineering report: timing, utilization, DSP/BRAM breakdown, power, DRC, methodology, congestion, routing, logic levels, build comparison, CFAR cost, verification summary
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Jason
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<section class="card" style="margin-top:0.8rem;">
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<h2>Current FPGA implementation status</h2>
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<ul>
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<li><strong>Build 21 (v0.1.4-build21)</strong> is the current production baseline for the XC7A200T target. All timing constraints met: WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns.</li>
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<li>Utilization: 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%), 0.732 W total power.</li>
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<li>Key improvements over Build 20: FFT 4-cycle butterfly (20% throughput gain), barrel-shift twiddle index (-1 DSP48), Gap 2 GUI Settings (runtime chirp timing, stream control, status readback), E2E RTL fixes, Vivado DRC multiple-driver fix, MMCM LOCKED XDC false_path correction.</li>
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<li>Build 21 reports are available on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build21/</code>.</li>
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<li><strong>Build 24</strong> is the current production baseline for the XC7A200T target. All timing constraints met. Includes CA-CFAR detector integration with pipelined noise computation.</li>
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<li>Build 24 reports are available on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build24/</code>.</li>
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<li>Build 21 (v0.1.4-build21) retained as pre-CFAR reference at <code>reports_build21/</code>.</li>
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</ul>
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</section>
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<!-- ===== Build 24 — 15-Point Report ===== -->
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<section class="card" style="margin-top:0.8rem;">
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<h2>Build 24 — 15-Point Engineering Report</h2>
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<p><span class="chip">Status: PASS — Production-safe bitstream generated</span></p>
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<p class="muted">Date: 2026-03-20 | Commit: <code>0745cc4</code> | Device: XC7A200T-2FBG484I | Vivado 2025.2</p>
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<!-- 1. Timing -->
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<h3>1. Timing Summary</h3>
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<div class="table-wrap">
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<table>
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<thead><tr><th>Clock Domain</th><th>Period (ns)</th><th>WNS (ns)</th><th>WHS (ns)</th><th>WPWS (ns)</th><th>Status</th></tr></thead>
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<tbody>
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<tr><td>clk_100m</td><td>10.000</td><td>+0.287</td><td>+0.056</td><td>+3.870</td><td>PASS</td></tr>
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<tr><td>clk_mmcm_out0 (400 MHz)</td><td>2.500</td><td>+0.179</td><td>+0.092</td><td>+0.684</td><td>PASS</td></tr>
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<tr><td>adc_dco_p</td><td>—</td><td>+0.904</td><td>—</td><td>+0.361</td><td>PASS</td></tr>
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<tr><td>ft601_clk_in</td><td>10.000</td><td>+0.347</td><td>+0.094</td><td>+4.500</td><td>PASS</td></tr>
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<tr><td>clk_120m_dac</td><td>—</td><td>+1.755</td><td>+0.056</td><td>+3.666</td><td>PASS</td></tr>
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</tbody>
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</table>
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</div>
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<p class="muted">TNS = 0.000 ns, THS = 0.000 ns across all domains. Zero failing endpoints.</p>
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<!-- 2. Utilization -->
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<h3>2. Utilization (Post-Route)</h3>
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<div class="table-wrap">
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<table>
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<thead><tr><th>Resource</th><th>Build 21 (baseline)</th><th>Build 24</th><th>Available</th><th>Util%</th><th>Delta</th></tr></thead>
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<tbody>
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<tr><td>Slice LUTs</td><td>6,192</td><td>8,558</td><td>134,600</td><td>6.36%</td><td>+2,366 (+38%)</td></tr>
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<tr><td>Slice Registers (FFs)</td><td>9,064</td><td>10,384</td><td>269,200</td><td>3.86%</td><td>+1,320 (+15%)</td></tr>
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<tr><td>Block RAM Tiles</td><td>16</td><td>17</td><td>365</td><td>4.66%</td><td>+1</td></tr>
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<tr><td> RAMB36E1</td><td>—</td><td>12</td><td>365</td><td>3.29%</td><td>—</td></tr>
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<tr><td> RAMB18E1</td><td>—</td><td>10</td><td>730</td><td>1.37%</td><td>—</td></tr>
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<tr><td>DSP48E1</td><td>139</td><td>142</td><td>740</td><td>19.19%</td><td>+3</td></tr>
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<tr><td>Bonded IOBs</td><td>—</td><td>178</td><td>285</td><td>62.46%</td><td>—</td></tr>
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<tr><td>BUFGCTRL</td><td>—</td><td>5</td><td>32</td><td>15.63%</td><td>—</td></tr>
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<tr><td>MMCME2_ADV</td><td>—</td><td>1</td><td>10</td><td>10.00%</td><td>—</td></tr>
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</tbody>
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</table>
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</div>
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<p class="muted">CFAR added +1 BRAM18 (magnitude buffer, 2048×17), +3 DSP48E1 (alpha multiply + cross-multiply for GO/SO), +2,366 LUTs (sliding window logic, state machine, mode mux), +1,320 FFs (pipeline registers, counters, window sums).</p>
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<!-- 3. DSP48E1 Breakdown -->
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<h3>3. DSP48E1 Breakdown by Module</h3>
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<div class="table-wrap">
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<table>
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<thead><tr><th>Module</th><th>DSP48E1</th><th>Notes</th></tr></thead>
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<tbody>
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<tr><td>DDC (FIR I + FIR Q + CIC + NCO)</td><td>117</td><td>Dominant consumer: 47+47 FIR taps + 10+10 CIC + 2 DDC + 1 NCO</td></tr>
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<tr><td>Matched Filter Processing Chain</td><td>12</td><td>8 FFT butterflies + 4 freq-domain multiply</td></tr>
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<tr><td>Doppler Processor + FFT</td><td>10</td><td>8 FFT butterflies + 2 magnitude</td></tr>
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<tr><td>CFAR Detector</td><td>3</td><td>alpha*noise multiply + GO/SO cross-multiply (pipelined)</td></tr>
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<tr><td>System Top + Other</td><td>0</td><td>—</td></tr>
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<tr><td><strong>Total</strong></td><td><strong>142</strong></td><td>19.19% of 740 available</td></tr>
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</tbody>
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</table>
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</div>
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<!-- 4. BRAM Breakdown -->
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<h3>4. BRAM Breakdown by Module</h3>
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<div class="table-wrap">
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<table>
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<thead><tr><th>Module</th><th>RAMB36</th><th>RAMB18</th><th>Tiles</th><th>Notes</th></tr></thead>
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<tbody>
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<tr><td>Doppler Processor</td><td>4</td><td>0</td><td>4</td><td>Range-Doppler accumulation buffers</td></tr>
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<tr><td>Matched Filter (mf_dual)</td><td>2</td><td>10</td><td>7</td><td>Coefficient + I/Q data BRAMs</td></tr>
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<tr><td>CFAR Detector</td><td>1</td><td>0</td><td>1</td><td>Magnitude buffer (2048×17 bits)</td></tr>
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<tr><td>Transmitter (chirp mem)</td><td>1</td><td>0</td><td>1</td><td>Chirp waveform storage</td></tr>
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<tr><td>FFT Engines (2×)</td><td>4</td><td>0</td><td>4</td><td>Twiddle factor + butterfly BRAMs</td></tr>
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<tr><td><strong>Total</strong></td><td><strong>12</strong></td><td><strong>10</strong></td><td><strong>17</strong></td><td>4.66% of 365 tiles</td></tr>
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</tbody>
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</table>
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</div>
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<!-- 5. Power -->
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<h3>5. Power Estimate</h3>
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<div class="table-wrap">
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<table>
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<thead><tr><th>Category</th><th>Build 21</th><th>Build 24</th></tr></thead>
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<tbody>
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<tr><td>Dynamic Power</td><td>—</td><td>0.591 W</td></tr>
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<tr><td>Device Static</td><td>—</td><td>0.163 W</td></tr>
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<tr><td><strong>Total On-Chip</strong></td><td><strong>0.732 W</strong></td><td><strong>0.754 W</strong></td></tr>
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<tr><td>Junction Temperature</td><td>—</td><td>26.9°C</td></tr>
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<tr><td>Max Ambient (TJA)</td><td>—</td><td>83.1°C</td></tr>
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</tbody>
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</table>
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</div>
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<p class="muted">+22 mW (+3%) from CFAR logic. Well within thermal budget.</p>
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<!-- 6. Critical Path -->
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<h3>6. Critical Path Analysis</h3>
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<p>The tightest path (WNS = +0.179 ns) is in the <code>clk_mmcm_out0</code> (400 MHz) domain: NCO sine LUT index register → LUT6 → <code>sin_abs_reg</code>. This is the same path that was critical in Build 21 and is unrelated to CFAR.</p>
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<p>The <code>clk_100m</code> domain (where CFAR operates) has +0.287 ns slack. The Build 23 critical path (<code>cfar_inst/leading_sum → cross-multiply → alpha*noise DSP</code>, WNS = -0.309 ns) has been completely eliminated by the pipeline fix.</p>
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<!-- 7. Post-synth vs Post-route -->
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<h3>7. Post-Synthesis vs Post-Route Comparison</h3>
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<div class="table-wrap">
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<table>
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<thead><tr><th>Metric</th><th>Post-Synth</th><th>Post-Route (final)</th></tr></thead>
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<tbody>
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<tr><td>WNS (setup)</td><td>+0.123 ns</td><td>+0.179 ns</td></tr>
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<tr><td>WHS (hold)</td><td>-0.076 ns (29 violations)</td><td>+0.056 ns (0 violations)</td></tr>
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<tr><td>LUTs</td><td>8,671</td><td>8,558</td></tr>
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<tr><td>FFs</td><td>10,433</td><td>10,384</td></tr>
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</tbody>
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</table>
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</div>
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<p class="muted">Post-route phys_opt resolved all 29 hold violations and improved setup slack by 56 ps. LUT/FF count reduced slightly by optimization passes.</p>
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<!-- 8. DRC -->
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<h3>8. DRC (Design Rule Checks)</h3>
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<p>184 checks performed. <strong>0 errors, 0 critical warnings.</strong> Advisory/warning breakdown:</p>
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<ul>
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<li>DPIP-1 (input pipelining advisory): 68 — DSP input pipeline suggestions, acceptable for our architecture</li>
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<li>DPOP-1/2 (output pipelining): 18 + 19 — DSP PREG/MREG advisory, non-critical</li>
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<li>REQP-1839/1840 (BRAM async control): 20 + 20 — expected with async-reset BRAMs</li>
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<li>RPBF-3 (IO buffering): 8 — intentional for differential pairs</li>
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<li>CHECK-3 (report rule limit): 2 — tool display limit, not design issue</li>
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<li>IOSR-1 (IOB set/reset sharing): 1 — non-critical</li>
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</ul>
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<!-- 9. Methodology -->
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<h3>9. Methodology Report</h3>
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<ul>
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<li>DPIR-1 (async driver): 91 — known from async-reset architecture, mitigated by CDC modules</li>
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<li>HPDR-1 (port direction inconsistency): 8 — bidir USB data bus, expected</li>
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<li>LUTAR-1 (LUT drives async reset): 1 — watchdog reset path, intentional</li>
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<li>PDRC-190 (suboptimal sync register placement): 3 — minor, does not affect timing</li>
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<li>SYNTH-6 (RAM timing sub-optimal): 18 — inferred RAMs, all meeting timing</li>
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<li>TIMING-9 (unknown CDC logic): 1 — covered by explicit CDC synchronizers</li>
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<li>TIMING-28 (auto-derived clock in constraint): 8 — expected with MMCM-derived clocks</li>
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<li>TIMING-47 (false path between sync clocks): 4 — intentional XDC false_path constraints</li>
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</ul>
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<!-- 10. Congestion -->
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<h3>10. Congestion</h3>
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<p><strong>No congestion windows found above level 5.</strong> The design is well-placed with no routing pressure. XC7A200T provides ample routing resources at 6.36% LUT utilization.</p>
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<!-- 11. Route Status -->
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<h3>11. Route Status</h3>
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<ul>
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<li>Total logical nets: 31,136</li>
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<li>Routable nets: 22,026 — <strong>22,026 fully routed (100%)</strong></li>
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<li>Nets with routing errors: <strong>0</strong></li>
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</ul>
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<!-- 12. Logic Level Distribution -->
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<h3>12. Logic Level Distribution (Top 1000 Worst Paths)</h3>
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<div class="table-wrap">
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<table>
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<thead><tr><th>Clock</th><th>Period</th><th>Lvl 0</th><th>Lvl 1</th><th>Lvl 2</th><th>Lvl 3</th><th>Lvl 4</th><th>Lvl 5</th></tr></thead>
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<tbody>
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<tr><td>clk_100m</td><td>10.000 ns</td><td>25</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
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<tr><td>clk_mmcm_out0</td><td>2.500 ns</td><td>808</td><td>108</td><td>3</td><td>19</td><td>8</td><td>3</td></tr>
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<tr><td>ft601_clk_in</td><td>10.000 ns</td><td>0</td><td>0</td><td>0</td><td>2</td><td>1</td><td>23</td></tr>
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</tbody>
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</table>
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</div>
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<p class="muted">The <code>clk_100m</code> domain has only level-0 paths in the top-1000 worst — CFAR pipeline fix reduced logic depth to register-to-register transfers. The 400 MHz DDC domain remains the most timing-critical area.</p>
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<!-- 13. Build Comparison -->
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<h3>13. Build-Over-Build Comparison</h3>
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<div class="table-wrap">
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<table>
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<thead><tr><th>Metric</th><th>Build 21 (baseline)</th><th>Build 23 (CFAR, failed)</th><th>Build 24 (CFAR + pipeline)</th></tr></thead>
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<tbody>
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<tr><td>WNS (ns)</td><td>+0.156</td><td style="color:#c33;">-0.309</td><td style="color:#080;"><strong>+0.179</strong></td></tr>
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<tr><td>WHS (ns)</td><td>+0.064</td><td>—</td><td>+0.056</td></tr>
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<tr><td>LUTs</td><td>6,192</td><td>8,668 (post-synth)</td><td>8,558</td></tr>
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<tr><td>FFs</td><td>9,064</td><td>10,411 (post-synth)</td><td>10,384</td></tr>
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<tr><td>BRAM Tiles</td><td>16</td><td>17 (post-synth)</td><td>17</td></tr>
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<tr><td>DSP48E1</td><td>139</td><td>—</td><td>142</td></tr>
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<tr><td>Power (W)</td><td>0.732</td><td>—</td><td>0.754</td></tr>
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<tr><td>Bitstream</td><td>Safe</td><td style="color:#c33;">Unsafe (timing fail)</td><td style="color:#080;"><strong>Safe</strong></td></tr>
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</tbody>
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</table>
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</div>
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<!-- 14. CFAR Resource Cost -->
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<h3>14. CFAR Integration Resource Cost</h3>
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<div class="table-wrap">
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<table>
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<thead><tr><th>Resource</th><th>CFAR Module Only</th><th>% of Device</th><th>Notes</th></tr></thead>
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<tbody>
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<tr><td>LUTs</td><td>2,229</td><td>1.66%</td><td>Sliding window sums, GO/SO cross-multiply, state machine, mode mux</td></tr>
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<tr><td>FFs</td><td>1,281</td><td>0.48%</td><td>Pipeline registers, window counters, sum accumulators, noise_sum_reg</td></tr>
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<tr><td>RAMB36E1</td><td>1</td><td>0.27%</td><td>Magnitude buffer: 2048 entries × 17 bits</td></tr>
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<tr><td>DSP48E1</td><td>3</td><td>0.41%</td><td>alpha×noise, leading cross-multiply, lagging cross-multiply</td></tr>
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</tbody>
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</table>
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</div>
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<p class="muted">Total CFAR cost: 2.82% of device LUTs, 0.48% of FFs, 0.27% of BRAM, 0.41% of DSPs. Minimal impact on headroom.</p>
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<!-- 15. Verification Summary -->
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<h3>15. Verification Summary</h3>
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<div class="table-wrap">
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<table>
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<thead><tr><th>Test Suite</th><th>Tests</th><th>Checks</th><th>Status</th></tr></thead>
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<tbody>
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<tr><td>FPGA regression (run_regression.sh)</td><td>22</td><td>—</td><td>22/22 PASS</td></tr>
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<tr><td>CFAR standalone (tb_cfar_ca.v)</td><td>14</td><td>23</td><td>23/23 PASS</td></tr>
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<tr><td>Digital gain (tb_rx_gain_control.v)</td><td>—</td><td>32</td><td>32/32 PASS</td></tr>
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<tr><td>Threshold fallback (tb_threshold_detector.v)</td><td>—</td><td>22</td><td>22/22 PASS</td></tr>
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<tr><td>System E2E (tb_system_e2e.v, Group 14)</td><td>13</td><td>67</td><td>67/67 PASS</td></tr>
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<tr><td>Real-data co-sim: Range FFT</td><td>1</td><td>1,024</td><td>1024/1024 exact</td></tr>
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<tr><td>Real-data co-sim: Doppler</td><td>1</td><td>2,056</td><td>2056/2056 exact</td></tr>
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<tr><td>Real-data co-sim: Full-chain</td><td>1</td><td>2,057</td><td>2057/2057 exact</td></tr>
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<tr><td>MCU regression</td><td>20</td><td>—</td><td>20/20 PASS</td></tr>
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</tbody>
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</table>
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</div>
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<p class="muted">5,281 individual data checks across all RTL test suites. Zero failures. Real-data co-simulation confirms bit-exact match with Python golden reference across the entire signal processing chain.</p>
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<h3>Build 24 Artifacts</h3>
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<ul>
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<li>Bitstream: <code>~/PLFM_RADAR_work/vivado_project/bitstream/radar_system_top_build24.bit</code> (9.7 MB)</li>
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<li>Reports: <code>~/PLFM_RADAR_work/vivado_project/reports_build24/</code> (21 report files)</li>
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<li>Build log: <code>~/PLFM_RADAR_work/build24.log</code></li>
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<li>TCL script: <code>~/PLFM_RADAR_work/vivado_project/build24_cfar.tcl</code></li>
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</ul>
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<p class="muted">Note: TCL crashed at step 13/15 (<code>extract_files</code> missing parameter) after all reports were generated. Non-critical scripting bug; all implementation, optimization, and bitstream generation completed successfully.</p>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Board-day artifact inventory</h2>
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<div class="table-wrap">
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@@ -57,7 +280,7 @@
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<tr><td>Production-target XDC</td><td><code>9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc</code></td><td>Constraint source of truth for the production FPGA target</td><td>Tracked and validated after Build 16 cleanup port</td></tr>
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<tr><td>FPGA programming flow</td><td><code>9_Firmware/9_2_FPGA/scripts/program_fpga.tcl</code></td><td>Programs the device and reports DONE / INIT_COMPLETE / probes presence</td><td>Primary operator-facing programming script</td></tr>
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<tr><td>Debug probe insertion flow</td><td><code>9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl</code></td><td>Used when generating or refreshing debug-capable images</td><td>Keep matched with the selected debug bitstream</td></tr>
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<tr><td>FPGA regression runner</td><td><code>9_Firmware/9_2_FPGA/run_regression.sh</code></td><td>Pre-arrival regression evidence for the tracked FPGA baseline</td><td>19 / 19 passing on the current tracked branch (includes E2E test)</td></tr>
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<tr><td>FPGA regression runner</td><td><code>9_Firmware/9_2_FPGA/run_regression.sh</code></td><td>Pre-arrival regression evidence for the tracked FPGA baseline</td><td>22 / 22 passing on the current tracked branch (includes CFAR + E2E tests)</td></tr>
|
||||
<tr><td>MCU regression harness</td><td><code>9_Firmware/9_1_Microcontroller/tests/Makefile</code></td><td>Pre-arrival firmware regression evidence before flashing hardware</td><td>20 / 20 passing on the current tracked branch</td></tr>
|
||||
<tr><td>Bring-up logging macros</td><td><code>9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.h</code></td><td>Defines the main first-power-on log vocabulary used over USART3</td><td>Observation-only instrumentation layer</td></tr>
|
||||
<tr><td>Board-day worksheet</td><td><code>docs/board-day-worksheet.html</code></td><td>Record pass/fail, measurements, and blockers during first sessions</td><td>Use with this page and the bring-up plan</td></tr>
|
||||
@@ -92,9 +315,10 @@
|
||||
|
||||
<section class="card" style="margin-top:0.8rem;">
|
||||
<h2>FPGA implementation analysis</h2>
|
||||
<p><span class="chip">Status: Current engineering baseline — Build 21 (v0.1.4-build21)</span></p>
|
||||
<p class="muted">Build 21 is the current production baseline. Full timing, utilization, power, DRC, methodology, CDC, and route reports are available on the remote Vivado host. Setup slack is +0.156 ns (tighter than Build 20's +0.426 ns due to Gap 2 register map additions, but comfortable and better than the intermediate Gap 2 build at +0.078 ns). Hold slack improved to +0.064 ns. DSP count dropped from 140 to 139 via barrel-shift twiddle optimization.</p>
|
||||
<p class="muted">Build 20 (v0.1.3-build20) retained as prior reference. Build 19 failed timing (WNS -0.011 ns) due to conflicting XDC generated clock, root-caused and fixed in Build 20.</p>
|
||||
<p><span class="chip">Status: Current engineering baseline — Build 24 (CFAR + pipeline fix)</span></p>
|
||||
<p class="muted">Build 24 is the current production baseline. Includes CA-CFAR detector integration (CA/GO/SO modes) with pipelined noise computation for timing closure. Full 15-point report above. WNS +0.179 ns (improved from Build 21's +0.156 ns due to phys_opt improvements). DSP count 142 (+3 for CFAR alpha and cross-multiply). BRAM 17 (+1 for CFAR magnitude buffer).</p>
|
||||
<p class="muted">Build 23 failed timing (WNS -0.309 ns) due to combinational critical path in CFAR noise computation. Root-caused and fixed by pipelining <code>noise_sum_comb</code> into a registered intermediate (<code>noise_sum_reg</code>), splitting the path across two clock cycles.</p>
|
||||
<p class="muted">Build 21 (v0.1.4-build21) retained as pre-CFAR reference. Build 20 (v0.1.3-build20) and earlier retained for historical reference.</p>
|
||||
</section>
|
||||
|
||||
<section class="card" style="margin-top:0.8rem;">
|
||||
@@ -111,11 +335,11 @@
|
||||
<section class="card" style="margin-top:0.8rem;">
|
||||
<h2>Report Currency Notice</h2>
|
||||
<ul>
|
||||
<li>The current routed production-target baseline is <strong>Build 21 (v0.1.4-build21)</strong> with all timing constraints met. WNS +0.156 ns, WHS +0.064 ns, 139 DSP48E1, 0.732 W.</li>
|
||||
<li>Architectural gaps 2 (GUI Settings), 3 (Safety), 4 (USB Read Path), 5 (BRAM Reset), and 7 (MMCM) are closed. Gaps 1 (CFAR) and 6 (CDC-15) remain for post-bring-up.</li>
|
||||
<li>FPGA regression: 19/19 pass (includes new E2E integration test). MCU regression: 20/20 pass (15 bug-fix + 5 Gap-3 safety).</li>
|
||||
<li>FFT engine optimized and Vivado-verified in Build 21: 4-cycle butterfly (20% throughput gain) + barrel-shift twiddle index (freed 1 DSP48, 140 → 139).</li>
|
||||
<li>Detailed Build 21 engineering reports are on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build21/</code>.</li>
|
||||
<li>The current routed production-target baseline is <strong>Build 24</strong> with all timing constraints met. WNS +0.179 ns, WHS +0.056 ns, 142 DSP48E1, 17 BRAM, 0.754 W.</li>
|
||||
<li>All architectural gaps are closed: Gap 1 (CFAR) integrated as CA-CFAR detector with CA/GO/SO modes. Gaps 2–7 were closed prior to Build 21.</li>
|
||||
<li>FPGA regression: 22/22 pass (includes CFAR standalone + E2E CFAR config tests). MCU regression: 20/20 pass. Real-data co-sim: 3/3 exact match (5,137 data checks).</li>
|
||||
<li>CFAR integration cost: +2,229 LUTs, +1,281 FFs, +1 BRAM, +3 DSPs. Backward-compatible: <code>host_cfar_enable</code> defaults to disabled.</li>
|
||||
<li>Detailed Build 24 engineering reports are on the remote Vivado host at <code>~/PLFM_RADAR_work/vivado_project/reports_build24/</code>.</li>
|
||||
<li>The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.</li>
|
||||
</ul>
|
||||
</section>
|
||||
|
||||
Reference in New Issue
Block a user