From 075ae1e77a302169b2ed62cbbd5b3fafa5db1046 Mon Sep 17 00:00:00 2001 From: Jason <83615043+JJassonn69@users.noreply.github.com> Date: Fri, 20 Mar 2026 05:47:20 +0200 Subject: [PATCH] Add Build 24 15-point engineering report: timing, utilization, DSP/BRAM breakdown, power, DRC, methodology, congestion, routing, logic levels, build comparison, CFAR cost, verification summary --- docs/reports.html | 250 +++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 237 insertions(+), 13 deletions(-) diff --git a/docs/reports.html b/docs/reports.html index 7390b33..9921268 100644 --- a/docs/reports.html +++ b/docs/reports.html @@ -34,13 +34,236 @@

Current FPGA implementation status

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Build 24 — 15-Point Engineering Report

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Status: PASS — Production-safe bitstream generated

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Date: 2026-03-20  |  Commit: 0745cc4  |  Device: XC7A200T-2FBG484I  |  Vivado 2025.2

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1. Timing Summary

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Clock DomainPeriod (ns)WNS (ns)WHS (ns)WPWS (ns)Status
clk_100m10.000+0.287+0.056+3.870PASS
clk_mmcm_out0 (400 MHz)2.500+0.179+0.092+0.684PASS
adc_dco_p—+0.904—+0.361PASS
ft601_clk_in10.000+0.347+0.094+4.500PASS
clk_120m_dac—+1.755+0.056+3.666PASS
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TNS = 0.000 ns, THS = 0.000 ns across all domains. Zero failing endpoints.

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2. Utilization (Post-Route)

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ResourceBuild 21 (baseline)Build 24AvailableUtil%Delta
Slice LUTs6,1928,558134,6006.36%+2,366 (+38%)
Slice Registers (FFs)9,06410,384269,2003.86%+1,320 (+15%)
Block RAM Tiles16173654.66%+1
  RAMB36E1—123653.29%—
  RAMB18E1—107301.37%—
DSP48E113914274019.19%+3
Bonded IOBs—17828562.46%—
BUFGCTRL—53215.63%—
MMCME2_ADV—11010.00%—
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CFAR added +1 BRAM18 (magnitude buffer, 2048×17), +3 DSP48E1 (alpha multiply + cross-multiply for GO/SO), +2,366 LUTs (sliding window logic, state machine, mode mux), +1,320 FFs (pipeline registers, counters, window sums).

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3. DSP48E1 Breakdown by Module

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ModuleDSP48E1Notes
DDC (FIR I + FIR Q + CIC + NCO)117Dominant consumer: 47+47 FIR taps + 10+10 CIC + 2 DDC + 1 NCO
Matched Filter Processing Chain128 FFT butterflies + 4 freq-domain multiply
Doppler Processor + FFT108 FFT butterflies + 2 magnitude
CFAR Detector3alpha*noise multiply + GO/SO cross-multiply (pipelined)
System Top + Other0—
Total14219.19% of 740 available
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4. BRAM Breakdown by Module

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ModuleRAMB36RAMB18TilesNotes
Doppler Processor404Range-Doppler accumulation buffers
Matched Filter (mf_dual)2107Coefficient + I/Q data BRAMs
CFAR Detector101Magnitude buffer (2048×17 bits)
Transmitter (chirp mem)101Chirp waveform storage
FFT Engines (2×)404Twiddle factor + butterfly BRAMs
Total1210174.66% of 365 tiles
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5. Power Estimate

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CategoryBuild 21Build 24
Dynamic Power—0.591 W
Device Static—0.163 W
Total On-Chip0.732 W0.754 W
Junction Temperature—26.9°C
Max Ambient (TJA)—83.1°C
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+22 mW (+3%) from CFAR logic. Well within thermal budget.

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6. Critical Path Analysis

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The tightest path (WNS = +0.179 ns) is in the clk_mmcm_out0 (400 MHz) domain: NCO sine LUT index register → LUT6 → sin_abs_reg. This is the same path that was critical in Build 21 and is unrelated to CFAR.

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The clk_100m domain (where CFAR operates) has +0.287 ns slack. The Build 23 critical path (cfar_inst/leading_sum → cross-multiply → alpha*noise DSP, WNS = -0.309 ns) has been completely eliminated by the pipeline fix.

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7. Post-Synthesis vs Post-Route Comparison

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MetricPost-SynthPost-Route (final)
WNS (setup)+0.123 ns+0.179 ns
WHS (hold)-0.076 ns (29 violations)+0.056 ns (0 violations)
LUTs8,6718,558
FFs10,43310,384
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Post-route phys_opt resolved all 29 hold violations and improved setup slack by 56 ps. LUT/FF count reduced slightly by optimization passes.

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8. DRC (Design Rule Checks)

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184 checks performed. 0 errors, 0 critical warnings. Advisory/warning breakdown:

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9. Methodology Report

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10. Congestion

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No congestion windows found above level 5. The design is well-placed with no routing pressure. XC7A200T provides ample routing resources at 6.36% LUT utilization.

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11. Route Status

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12. Logic Level Distribution (Top 1000 Worst Paths)

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ClockPeriodLvl 0Lvl 1Lvl 2Lvl 3Lvl 4Lvl 5
clk_100m10.000 ns2500000
clk_mmcm_out02.500 ns80810831983
ft601_clk_in10.000 ns0002123
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The clk_100m domain has only level-0 paths in the top-1000 worst — CFAR pipeline fix reduced logic depth to register-to-register transfers. The 400 MHz DDC domain remains the most timing-critical area.

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13. Build-Over-Build Comparison

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MetricBuild 21 (baseline)Build 23 (CFAR, failed)Build 24 (CFAR + pipeline)
WNS (ns)+0.156-0.309+0.179
WHS (ns)+0.064—+0.056
LUTs6,1928,668 (post-synth)8,558
FFs9,06410,411 (post-synth)10,384
BRAM Tiles1617 (post-synth)17
DSP48E1139—142
Power (W)0.732—0.754
BitstreamSafeUnsafe (timing fail)Safe
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14. CFAR Integration Resource Cost

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ResourceCFAR Module Only% of DeviceNotes
LUTs2,2291.66%Sliding window sums, GO/SO cross-multiply, state machine, mode mux
FFs1,2810.48%Pipeline registers, window counters, sum accumulators, noise_sum_reg
RAMB36E110.27%Magnitude buffer: 2048 entries × 17 bits
DSP48E130.41%alpha×noise, leading cross-multiply, lagging cross-multiply
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Total CFAR cost: 2.82% of device LUTs, 0.48% of FFs, 0.27% of BRAM, 0.41% of DSPs. Minimal impact on headroom.

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15. Verification Summary

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Test SuiteTestsChecksStatus
FPGA regression (run_regression.sh)22—22/22 PASS
CFAR standalone (tb_cfar_ca.v)142323/23 PASS
Digital gain (tb_rx_gain_control.v)—3232/32 PASS
Threshold fallback (tb_threshold_detector.v)—2222/22 PASS
System E2E (tb_system_e2e.v, Group 14)136767/67 PASS
Real-data co-sim: Range FFT11,0241024/1024 exact
Real-data co-sim: Doppler12,0562056/2056 exact
Real-data co-sim: Full-chain12,0572057/2057 exact
MCU regression20—20/20 PASS
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5,281 individual data checks across all RTL test suites. Zero failures. Real-data co-simulation confirms bit-exact match with Python golden reference across the entire signal processing chain.

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Build 24 Artifacts

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Note: TCL crashed at step 13/15 (extract_files missing parameter) after all reports were generated. Non-critical scripting bug; all implementation, optimization, and bitstream generation completed successfully.

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Board-day artifact inventory

@@ -57,7 +280,7 @@ Production-target XDC9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdcConstraint source of truth for the production FPGA targetTracked and validated after Build 16 cleanup port FPGA programming flow9_Firmware/9_2_FPGA/scripts/program_fpga.tclPrograms the device and reports DONE / INIT_COMPLETE / probes presencePrimary operator-facing programming script Debug probe insertion flow9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tclUsed when generating or refreshing debug-capable imagesKeep matched with the selected debug bitstream - FPGA regression runner9_Firmware/9_2_FPGA/run_regression.shPre-arrival regression evidence for the tracked FPGA baseline19 / 19 passing on the current tracked branch (includes E2E test) + FPGA regression runner9_Firmware/9_2_FPGA/run_regression.shPre-arrival regression evidence for the tracked FPGA baseline22 / 22 passing on the current tracked branch (includes CFAR + E2E tests) MCU regression harness9_Firmware/9_1_Microcontroller/tests/MakefilePre-arrival firmware regression evidence before flashing hardware20 / 20 passing on the current tracked branch Bring-up logging macros9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.hDefines the main first-power-on log vocabulary used over USART3Observation-only instrumentation layer Board-day worksheetdocs/board-day-worksheet.htmlRecord pass/fail, measurements, and blockers during first sessionsUse with this page and the bring-up plan @@ -92,9 +315,10 @@

FPGA implementation analysis

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Status: Current engineering baseline — Build 21 (v0.1.4-build21)

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Build 21 is the current production baseline. Full timing, utilization, power, DRC, methodology, CDC, and route reports are available on the remote Vivado host. Setup slack is +0.156 ns (tighter than Build 20's +0.426 ns due to Gap 2 register map additions, but comfortable and better than the intermediate Gap 2 build at +0.078 ns). Hold slack improved to +0.064 ns. DSP count dropped from 140 to 139 via barrel-shift twiddle optimization.

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Build 20 (v0.1.3-build20) retained as prior reference. Build 19 failed timing (WNS -0.011 ns) due to conflicting XDC generated clock, root-caused and fixed in Build 20.

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Status: Current engineering baseline — Build 24 (CFAR + pipeline fix)

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Build 24 is the current production baseline. Includes CA-CFAR detector integration (CA/GO/SO modes) with pipelined noise computation for timing closure. Full 15-point report above. WNS +0.179 ns (improved from Build 21's +0.156 ns due to phys_opt improvements). DSP count 142 (+3 for CFAR alpha and cross-multiply). BRAM 17 (+1 for CFAR magnitude buffer).

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Build 23 failed timing (WNS -0.309 ns) due to combinational critical path in CFAR noise computation. Root-caused and fixed by pipelining noise_sum_comb into a registered intermediate (noise_sum_reg), splitting the path across two clock cycles.

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Build 21 (v0.1.4-build21) retained as pre-CFAR reference. Build 20 (v0.1.3-build20) and earlier retained for historical reference.

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Report Currency Notice

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  • The current routed production-target baseline is Build 21 (v0.1.4-build21) with all timing constraints met. WNS +0.156 ns, WHS +0.064 ns, 139 DSP48E1, 0.732 W.
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  • Architectural gaps 2 (GUI Settings), 3 (Safety), 4 (USB Read Path), 5 (BRAM Reset), and 7 (MMCM) are closed. Gaps 1 (CFAR) and 6 (CDC-15) remain for post-bring-up.
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  • FPGA regression: 19/19 pass (includes new E2E integration test). MCU regression: 20/20 pass (15 bug-fix + 5 Gap-3 safety).
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  • FFT engine optimized and Vivado-verified in Build 21: 4-cycle butterfly (20% throughput gain) + barrel-shift twiddle index (freed 1 DSP48, 140 → 139).
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  • Detailed Build 21 engineering reports are on the remote Vivado host at ~/PLFM_RADAR_work/vivado_project/reports_build21/.
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  • The current routed production-target baseline is Build 24 with all timing constraints met. WNS +0.179 ns, WHS +0.056 ns, 142 DSP48E1, 17 BRAM, 0.754 W.
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  • All architectural gaps are closed: Gap 1 (CFAR) integrated as CA-CFAR detector with CA/GO/SO modes. Gaps 2–7 were closed prior to Build 21.
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  • FPGA regression: 22/22 pass (includes CFAR standalone + E2E CFAR config tests). MCU regression: 20/20 pass. Real-data co-sim: 3/3 exact match (5,137 data checks).
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  • CFAR integration cost: +2,229 LUTs, +1,281 FFs, +1 BRAM, +3 DSPs. Backward-compatible: host_cfar_enable defaults to disabled.
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  • Detailed Build 24 engineering reports are on the remote Vivado host at ~/PLFM_RADAR_work/vivado_project/reports_build24/.
  • The artifact inventory above is intended to stabilize day-0 execution even when detailed internal engineering reports stay outside the public docs site.