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merge into: FlintyLemming/PLFM_RADAR:fix/agc-gain-arithmetic-overflow
Branches Tags
FlintyLemming/PLFM_RADAR:main FlintyLemming/PLFM_RADAR:develop FlintyLemming/PLFM_RADAR:fix/mcu-fault-ack-emergency-clear FlintyLemming/PLFM_RADAR:fix/mcu-volatile-emergency-state-agc-holdoff FlintyLemming/PLFM_RADAR:fix/agc-gain-arithmetic-overflow FlintyLemming/PLFM_RADAR:fix/pre-bringup-audit-p0 FlintyLemming/PLFM_RADAR:fix/xdc-hardening-and-adc-pin-anchors FlintyLemming/PLFM_RADAR:fix/adar1000-channel-rotation FlintyLemming/PLFM_RADAR:fix/adar1000-vm-tables FlintyLemming/PLFM_RADAR:fix/invariant-p0-signal-processing FlintyLemming/PLFM_RADAR:fix/agc-cross-layer-enable FlintyLemming/PLFM_RADAR:feat/fft-2048-upgrade FlintyLemming/PLFM_RADAR:feat/ft2232h-default-ft601-option FlintyLemming/PLFM_RADAR:feat/um982-gps-driver FlintyLemming/PLFM_RADAR:revert-68-feature/add-um982-gps-driver FlintyLemming/PLFM_RADAR:feat/agc-fpga-gui FlintyLemming/PLFM_RADAR:fix/ruff-lint-full-repo
..
pull from: FlintyLemming/PLFM_RADAR:feat/agc-fpga-gui
Branches Tags
FlintyLemming/PLFM_RADAR:main FlintyLemming/PLFM_RADAR:develop FlintyLemming/PLFM_RADAR:fix/mcu-fault-ack-emergency-clear FlintyLemming/PLFM_RADAR:fix/mcu-volatile-emergency-state-agc-holdoff FlintyLemming/PLFM_RADAR:fix/agc-gain-arithmetic-overflow FlintyLemming/PLFM_RADAR:fix/pre-bringup-audit-p0 FlintyLemming/PLFM_RADAR:fix/xdc-hardening-and-adc-pin-anchors FlintyLemming/PLFM_RADAR:fix/adar1000-channel-rotation FlintyLemming/PLFM_RADAR:fix/adar1000-vm-tables FlintyLemming/PLFM_RADAR:fix/invariant-p0-signal-processing FlintyLemming/PLFM_RADAR:fix/agc-cross-layer-enable FlintyLemming/PLFM_RADAR:feat/fft-2048-upgrade FlintyLemming/PLFM_RADAR:feat/ft2232h-default-ft601-option FlintyLemming/PLFM_RADAR:feat/um982-gps-driver FlintyLemming/PLFM_RADAR:revert-68-feature/add-um982-gps-driver FlintyLemming/PLFM_RADAR:feat/agc-fpga-gui FlintyLemming/PLFM_RADAR:fix/ruff-lint-full-repo

4 Commits
fix/agc-gain-arithmetic-overflow .. feat/agc-fpga-gui

Author SHA1 Message Date
Jason 7cb7688814 chore: add .gitattributes to enforce LF line endings for new files 2026-04-15 13:03:54 +05:45
Jason 86b493a780 feat: CI test suite phases A+B, WaveformConfig separation, dead golden code cleanup 
- Phase A: Remove self-blessing golden test from FPGA regression, wire
  MF co-sim (4 scenarios) into run_regression.sh, add opcode count guards
  to cross-layer tests (+3 tests)
- Phase B: Add radar_params.vh parser and architectural param consistency
  tests (+7 tests), add banned stale-value pattern scanner (+1 test)
- Separate WaveformConfig.range_resolution_m (physical, bandwidth-dependent)
  from bin_spacing_m (sample-rate dependent); rename all callers
- Remove 151 lines of dead golden generate/compare code from
  tb_radar_receiver_final.v; testbench now runs structural + bounds only
- Untrack generated MF co-sim CSV files, gitignore tb/golden/ directory

CI: 256 tests total (168 python + 40 cross-layer + 27 FPGA + 21 MCU), all green
 2026-04-15 12:45:41 +05:45
Jason c023337949 chore: gitignore sim artifacts (doppler CSV/mem) and MCU test binaries 
- Untrack rx_final_doppler_out.csv and golden_doppler.mem (regenerated by tests)
- Add 6 missing MCU test binaries to tests/.gitignore
 2026-04-15 10:39:05 +05:45
Jason d259e5c106 fix: align all range/carrier/velocity values to PLFM hardware + FPGA bug fixes 
- Correct carrier from 10.525/10 GHz to 10.5 GHz (verified ADF4382 config)
- Correct range-per-bin from 4.8/5.6/781.25 m to 24.0 m (matched-filter)
- Correct velocity resolution from 1.484 to 2.67 m/s/bin (PRI-based)
- Correct processing rate from 4 MSPS to 100 MSPS (post-DDC)
- Correct max range from 307/5000/50000 m to 1536 m (64 bins x 24 m)
- Add WaveformConfig.pri_s field (167 us PRI for velocity calculation)
- Fix short chirp chirp_complete deadlock (Bug A)
- Remove dead short_chirp ports, rename long_chirp to ref_chirp (Bug B)
- Fix stale latency comment 2159 -> 3187 cycles (Bug C)
- Create radar_params.vh as single source of truth for FPGA parameters
- Lower RadarSettings.cpp map_size validation bound from 1000 to 100
- Add PLFM hardware constants to golden_reference.py
- Update all GUI versions, tests, and cross-layer contracts

All 244 tests passing (167 Python + 21 MCU + 29 cross-layer + 27 FPGA)
 2026-04-15 10:38:59 +05:45
89 changed files with 5595 additions and 23221 deletions
Expand all files Collapse all files
.gitattributes
+21
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@@ -0,0 +1,21 @@
# Enforce LF line endings for all text files going forward.
# Existing CRLF files are left as-is to avoid polluting git blame.
* text=auto eol=lf
# Binary files — ensure git doesn't mangle these
*.npy binary
*.h5 binary
*.hdf5 binary
*.png binary
*.jpg binary
*.pdf binary
*.zip binary
*.bin binary
*.mem binary
*.hex binary
*.vvp binary
*.s2p binary
*.s3p binary
*.step binary
*.FCStd binary
*.FCBak binary
.gitignore
+6
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@@ -32,6 +32,12 @@
9_Firmware/9_2_FPGA/tb/cosim/rtl_doppler_*.csv
9_Firmware/9_2_FPGA/tb/cosim/compare_doppler_*.csv
9_Firmware/9_2_FPGA/tb/cosim/rtl_multiseg_*.csv
9_Firmware/9_2_FPGA/tb/cosim/rx_final_doppler_out.csv
9_Firmware/9_2_FPGA/tb/cosim/rtl_mf_*.csv
9_Firmware/9_2_FPGA/tb/cosim/compare_mf_*.csv
# Golden reference outputs (regenerated by testbenches)
9_Firmware/9_2_FPGA/tb/golden/
# macOS
.DS_Store
1_Project_Description/Project_Description.docx
BIN
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4_Schematics and Boards Layout/4_6_Schematics/MainBoard/RADAR_Main_Board.brd
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8_Utils/AERIS-10_RADAR.png
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8_Utils/Python/LUT.py
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@@ -1,7 +1,10 @@
import numpy as np
# Define parameters
fs = 120e6 # Sampling frequency
# NOTE: This is a standalone LUT generation utility. The production chirp LUT
# is generated by 9_Firmware/9_2_FPGA/tb/cosim/gen_chirp_mem.py with
# CHIRP_BW=20e6 (target: 30e6 Phase 1) and DAC_CLK=120e6.
fs = 120e6 # Sampling frequency (DAC clock from AD9523 OUT10)
Ts = 1 / fs # Sampling time
Tb = 1e-6 # Burst time
Tau = 30e-6 # Pulse repetition time
9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_AGC.cpp
+1 -1
View File
@@ -18,7 +18,7 @@ ADAR1000_AGC::ADAR1000_AGC()
, min_gain(0)
, max_gain(127)
, holdoff_frames(4)
, enabled(false)
, enabled(true)
, holdoff_counter(0)
, last_saturated(false)
, saturation_event_count(0)
9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp
+12 -91
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@@ -20,71 +20,18 @@ static const struct {
{ADAR_4_CS_3V3_GPIO_Port, ADAR_4_CS_3V3_Pin} // ADAR1000 #4
};
// ADAR1000 Vector Modulator lookup tables (128-state phase grid, 2.8125 deg step).
//
// Source: Analog Devices ADAR1000 datasheet Rev. B, Tables 13-16, page 34
// (7_Components Datasheets and Application notes/ADAR1000.pdf)
// Cross-checked against the ADI Linux mainline driver (GPL-2.0, NOT vendored):
// https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/
// drivers/iio/beamformer/adar1000.c (adar1000_phase_values[])
// The 128 byte values themselves are factual data from the datasheet and are
// not subject to copyright; only the ADI driver code is GPL.
//
// Byte format (per datasheet):
// bit [7:6] reserved (0)
// bit [5] polarity: 1 = positive lobe (sign(I) or sign(Q) >= 0)
// 0 = negative lobe
// bits [4:0] 5-bit unsigned magnitude (0..31)
// At magnitude=0 the polarity bit is physically meaningless; the datasheet
// uses POL=1 (e.g. VM_Q at 0 deg = 0x20, VM_I at 90 deg = 0x21).
//
// Index mapping is uniform: VM_I[k] / VM_Q[k] correspond to phase angle
// k * 360/128 = k * 2.8125 degrees. Callers index as VM_*[phase % 128].
// Vector Modulator lookup tables
const uint8_t ADAR1000Manager::VM_I[128] = {
0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3E, 0x3E, 0x3D, // [ 0] 0.0000 deg
0x3D, 0x3C, 0x3C, 0x3B, 0x3A, 0x39, 0x38, 0x37, // [ 8] 22.5000 deg
0x36, 0x35, 0x34, 0x33, 0x32, 0x30, 0x2F, 0x2E, // [ 16] 45.0000 deg
0x2C, 0x2B, 0x2A, 0x28, 0x27, 0x25, 0x24, 0x22, // [ 24] 67.5000 deg
0x21, 0x01, 0x03, 0x04, 0x06, 0x07, 0x08, 0x0A, // [ 32] 90.0000 deg
0x0B, 0x0D, 0x0E, 0x0F, 0x11, 0x12, 0x13, 0x14, // [ 40] 112.5000 deg
0x16, 0x17, 0x18, 0x19, 0x19, 0x1A, 0x1B, 0x1C, // [ 48] 135.0000 deg
0x1C, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F, // [ 56] 157.5000 deg
0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1E, 0x1E, 0x1D, // [ 64] 180.0000 deg
0x1D, 0x1C, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, // [ 72] 202.5000 deg
0x16, 0x15, 0x14, 0x13, 0x12, 0x10, 0x0F, 0x0E, // [ 80] 225.0000 deg
0x0C, 0x0B, 0x0A, 0x08, 0x07, 0x05, 0x04, 0x02, // [ 88] 247.5000 deg
0x01, 0x21, 0x23, 0x24, 0x26, 0x27, 0x28, 0x2A, // [ 96] 270.0000 deg
0x2B, 0x2D, 0x2E, 0x2F, 0x31, 0x32, 0x33, 0x34, // [104] 292.5000 deg
0x36, 0x37, 0x38, 0x39, 0x39, 0x3A, 0x3B, 0x3C, // [112] 315.0000 deg
0x3C, 0x3D, 0x3E, 0x3E, 0x3E, 0x3F, 0x3F, 0x3F, // [120] 337.5000 deg
// ... (same as in your original file)
};
const uint8_t ADAR1000Manager::VM_Q[128] = {
0x20, 0x21, 0x23, 0x24, 0x26, 0x27, 0x28, 0x2A, // [ 0] 0.0000 deg
0x2B, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x33, 0x34, // [ 8] 22.5000 deg
0x35, 0x36, 0x37, 0x38, 0x38, 0x39, 0x3A, 0x3A, // [ 16] 45.0000 deg
0x3B, 0x3C, 0x3C, 0x3C, 0x3D, 0x3D, 0x3D, 0x3D, // [ 24] 67.5000 deg
0x3D, 0x3D, 0x3D, 0x3D, 0x3D, 0x3C, 0x3C, 0x3C, // [ 32] 90.0000 deg
0x3B, 0x3A, 0x3A, 0x39, 0x38, 0x38, 0x37, 0x36, // [ 40] 112.5000 deg
0x35, 0x34, 0x33, 0x31, 0x30, 0x2F, 0x2E, 0x2D, // [ 48] 135.0000 deg
0x2B, 0x2A, 0x28, 0x27, 0x26, 0x24, 0x23, 0x21, // [ 56] 157.5000 deg
0x20, 0x01, 0x03, 0x04, 0x06, 0x07, 0x08, 0x0A, // [ 64] 180.0000 deg
0x0B, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x13, 0x14, // [ 72] 202.5000 deg
0x15, 0x16, 0x17, 0x18, 0x18, 0x19, 0x1A, 0x1A, // [ 80] 225.0000 deg
0x1B, 0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1D, 0x1D, // [ 88] 247.5000 deg
0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1C, 0x1C, 0x1C, // [ 96] 270.0000 deg
0x1B, 0x1A, 0x1A, 0x19, 0x18, 0x18, 0x17, 0x16, // [104] 292.5000 deg
0x15, 0x14, 0x13, 0x11, 0x10, 0x0F, 0x0E, 0x0D, // [112] 315.0000 deg
0x0B, 0x0A, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, // [120] 337.5000 deg
// ... (same as in your original file)
};
// NOTE: a VM_GAIN[128] table previously existed here as a placeholder but was
// never populated and never read. The ADAR1000 vector modulator has no
// separate gain register: phase-state magnitude is encoded directly in
// bits [4:0] of the VM_I/VM_Q bytes above. Per-channel VGA gain is a
// distinct register (CHx_RX_GAIN at 0x10-0x13, CHx_TX_GAIN at 0x1C-0x1F)
// written with the user-supplied byte directly by adarSetRxVgaGain() /
// adarSetTxVgaGain(). Do not reintroduce a VM_GAIN[] array.
const uint8_t ADAR1000Manager::VM_GAIN[128] = {
// ... (same as in your original file)
};
ADAR1000Manager::ADAR1000Manager() {
for (int i = 0; i < 4; ++i) {
@@ -868,22 +815,11 @@ void ADAR1000Manager::adarSetRamBypass(uint8_t deviceIndex, uint8_t broadcast) {
}
void ADAR1000Manager::adarSetRxPhase(uint8_t deviceIndex, uint8_t channel, uint8_t phase, uint8_t broadcast) {
// channel is 1-based (CH1..CH4) per API contract documented in
// ADAR1000_AGC.cpp and matching ADI datasheet terminology.
// Reject out-of-range early so a stale 0-based caller does not
// silently wrap to ((0-1) & 0x03) == 3 and write to CH4.
// See issue #90.
if (channel < 1 || channel > 4) {
DIAG("BF", "adarSetRxPhase: channel %u out of range [1..4], ignored", channel);
return;
}
uint8_t i_val = VM_I[phase % 128];
uint8_t q_val = VM_Q[phase % 128];
// Subtract 1 to convert 1-based channel to 0-based register offset
// before masking. See issue #90.
uint32_t mem_addr_i = REG_CH1_RX_PHS_I + ((channel - 1) & 0x03) * 2;
uint32_t mem_addr_q = REG_CH1_RX_PHS_Q + ((channel - 1) & 0x03) * 2;
uint32_t mem_addr_i = REG_CH1_RX_PHS_I + (channel & 0x03) * 2;
uint32_t mem_addr_q = REG_CH1_RX_PHS_Q + (channel & 0x03) * 2;
adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
@@ -891,16 +827,11 @@ void ADAR1000Manager::adarSetRxPhase(uint8_t deviceIndex, uint8_t channel, uint8
}
void ADAR1000Manager::adarSetTxPhase(uint8_t deviceIndex, uint8_t channel, uint8_t phase, uint8_t broadcast) {
// channel is 1-based (CH1..CH4). See issue #90.
if (channel < 1 || channel > 4) {
DIAG("BF", "adarSetTxPhase: channel %u out of range [1..4], ignored", channel);
return;
}
uint8_t i_val = VM_I[phase % 128];
uint8_t q_val = VM_Q[phase % 128];
uint32_t mem_addr_i = REG_CH1_TX_PHS_I + ((channel - 1) & 0x03) * 2;
uint32_t mem_addr_q = REG_CH1_TX_PHS_Q + ((channel - 1) & 0x03) * 2;
uint32_t mem_addr_i = REG_CH1_TX_PHS_I + (channel & 0x03) * 2;
uint32_t mem_addr_q = REG_CH1_TX_PHS_Q + (channel & 0x03) * 2;
adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
@@ -908,23 +839,13 @@ void ADAR1000Manager::adarSetTxPhase(uint8_t deviceIndex, uint8_t channel, uint8
}
void ADAR1000Manager::adarSetRxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
// channel is 1-based (CH1..CH4). See issue #90.
if (channel < 1 || channel > 4) {
DIAG("BF", "adarSetRxVgaGain: channel %u out of range [1..4], ignored", channel);
return;
}
uint32_t mem_addr = REG_CH1_RX_GAIN + ((channel - 1) & 0x03);
uint32_t mem_addr = REG_CH1_RX_GAIN + (channel & 0x03);
adarWrite(deviceIndex, mem_addr, gain, broadcast);
adarWrite(deviceIndex, REG_LOAD_WORKING, 0x1, broadcast);
}
void ADAR1000Manager::adarSetTxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
// channel is 1-based (CH1..CH4). See issue #90.
if (channel < 1 || channel > 4) {
DIAG("BF", "adarSetTxVgaGain: channel %u out of range [1..4], ignored", channel);
return;
}
uint32_t mem_addr = REG_CH1_TX_GAIN + ((channel - 1) & 0x03);
uint32_t mem_addr = REG_CH1_TX_GAIN + (channel & 0x03);
adarWrite(deviceIndex, mem_addr, gain, broadcast);
adarWrite(deviceIndex, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
}
9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.h
+3 -5
View File
@@ -116,12 +116,10 @@ public:
bool beam_sweeping_active_ = false;
uint32_t last_beam_update_time_ = 0;
// Vector Modulator lookup tables (see ADAR1000_Manager.cpp for provenance).
// Indexed as VM_*[phase % 128] on a uniform 2.8125 deg grid.
// No VM_GAIN[] table exists: VM magnitude is bits [4:0] of the I/Q bytes
// themselves; per-channel VGA gain uses a separate register.
static const uint8_t VM_I[128];
// Lookup tables
static const uint8_t VM_I[128];
static const uint8_t VM_Q[128];
static const uint8_t VM_GAIN[128];
// Named defaults for the ADTR1107 and ADAR1000 power sequence.
static constexpr uint8_t kDefaultTxVgaGain = 0x7F;
9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/RadarSettings.cpp
+6 -6
View File
@@ -6,16 +6,16 @@ RadarSettings::RadarSettings() {
}
void RadarSettings::resetToDefaults() {
system_frequency = 10.0e9; // 10 GHz
chirp_duration_1 = 30.0e-6; // 30 �s
chirp_duration_2 = 0.5e-6; // 0.5 �s
system_frequency = 10.5e9; // 10.5 GHz (PLFM TX LO, ADF4382 config)
chirp_duration_1 = 30.0e-6; // 30 µs
chirp_duration_2 = 0.5e-6; // 0.5 µs
chirps_per_position = 32;
freq_min = 10.0e6; // 10 MHz
freq_max = 30.0e6; // 30 MHz
prf1 = 1000.0; // 1 kHz
prf2 = 2000.0; // 2 kHz
max_distance = 50000.0; // 50 km
map_size = 50000.0; // 50 km
max_distance = 1536.0; // 1536 m (64 bins × 24 m, 3 km mode)
map_size = 1536.0; // 1536 m
settings_valid = true;
}
@@ -88,7 +88,7 @@ bool RadarSettings::validateSettings() {
if (prf1 < 100 || prf1 > 10000) return false;
if (prf2 < 100 || prf2 > 10000) return false;
if (max_distance < 100 || max_distance > 100000) return false;
if (map_size < 1000 || map_size > 200000) return false;
if (map_size < 100 || map_size > 200000) return false;
return true;
}
9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/adar1000.c
+693
View File
@@ -0,0 +1,693 @@
/**
* MIT License
*
* Copyright (c) 2020 Jimmy Pentz
*
* Reach me at: github.com/jgpentz, jpentz1(at)gmail.com
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sells
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/* ADAR1000 4-Channel, X Band and Ku Band Beamformer */
// ----------------------------------------------------------------------------
// Includes
// ----------------------------------------------------------------------------
#include "main.h"
#include "stm32f7xx_hal.h"
#include "stm32f7xx_hal_spi.h"
#include "stm32f7xx_hal_gpio.h"
#include "adar1000.h"
// ----------------------------------------------------------------------------
// Preprocessor Definitions and Constants
// ----------------------------------------------------------------------------
// VM_GAIN is 15 dB of gain in 128 steps. ~0.12 dB per step.
// A 15 dB attenuator can be applied on top of these values.
const uint8_t VM_GAIN[128] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
};
// VM_I and VM_Q are the settings for the vector modulator. 128 steps in 360 degrees. ~2.813 degrees per step.
const uint8_t VM_I[128] = {
0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3E, 0x3E, 0x3D, 0x3D, 0x3C, 0x3C, 0x3B, 0x3A, 0x39, 0x38, 0x37,
0x36, 0x35, 0x34, 0x33, 0x32, 0x30, 0x2F, 0x2E, 0x2C, 0x2B, 0x2A, 0x28, 0x27, 0x25, 0x24, 0x22,
0x21, 0x01, 0x03, 0x04, 0x06, 0x07, 0x08, 0x0A, 0x0B, 0x0D, 0x0E, 0x0F, 0x11, 0x12, 0x13, 0x14,
0x16, 0x17, 0x18, 0x19, 0x19, 0x1A, 0x1B, 0x1C, 0x1C, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F,
0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1E, 0x1E, 0x1D, 0x1D, 0x1C, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17,
0x16, 0x15, 0x14, 0x13, 0x12, 0x10, 0x0F, 0x0E, 0x0C, 0x0B, 0x0A, 0x08, 0x07, 0x05, 0x04, 0x02,
0x01, 0x21, 0x23, 0x24, 0x26, 0x27, 0x28, 0x2A, 0x2B, 0x2D, 0x2E, 0x2F, 0x31, 0x32, 0x33, 0x34,
0x36, 0x37, 0x38, 0x39, 0x39, 0x3A, 0x3B, 0x3C, 0x3C, 0x3D, 0x3E, 0x3E, 0x3E, 0x3F, 0x3F, 0x3F,
};
const uint8_t VM_Q[128] = {
0x20, 0x21, 0x23, 0x24, 0x26, 0x27, 0x28, 0x2A, 0x2B, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x33, 0x34,
0x35, 0x36, 0x37, 0x38, 0x38, 0x39, 0x3A, 0x3A, 0x3B, 0x3C, 0x3C, 0x3C, 0x3D, 0x3D, 0x3D, 0x3D,
0x3D, 0x3D, 0x3D, 0x3D, 0x3D, 0x3C, 0x3C, 0x3C, 0x3B, 0x3A, 0x3A, 0x39, 0x38, 0x38, 0x37, 0x36,
0x35, 0x34, 0x33, 0x31, 0x30, 0x2F, 0x2E, 0x2D, 0x2B, 0x2A, 0x28, 0x27, 0x26, 0x24, 0x23, 0x21,
0x20, 0x01, 0x03, 0x04, 0x06, 0x07, 0x08, 0x0A, 0x0B, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x13, 0x14,
0x15, 0x16, 0x17, 0x18, 0x18, 0x19, 0x1A, 0x1A, 0x1B, 0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1D, 0x1D,
0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1C, 0x1C, 0x1C, 0x1B, 0x1A, 0x1A, 0x19, 0x18, 0x18, 0x17, 0x16,
0x15, 0x14, 0x13, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0B, 0x0A, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01,
};
// ----------------------------------------------------------------------------
// Function Definitions
// ----------------------------------------------------------------------------
/**
* @brief Initialize the ADC on the ADAR by setting the ADC with a 2 MHz clk,
* and then enable it.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @warning This is setup to only read temperature sensor data, not the power detectors.
*/
void Adar_AdcInit(const AdarDevice * p_adar, uint8_t broadcast)
{
uint8_t data;
data = ADAR1000_ADC_2MHZ_CLK | ADAR1000_ADC_EN;
Adar_Write(p_adar, REG_ADC_CONTROL, data, broadcast);
}
/**
* @brief Read a byte of data from the ADAR.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns a byte of data that has been converted from the temperature sensor.
*
* @warning This is setup to only read temperature sensor data, not the power detectors.
*/
uint8_t Adar_AdcRead(const AdarDevice * p_adar, uint8_t broadcast)
{
uint8_t data;
// Start the ADC conversion
Adar_Write(p_adar, REG_ADC_CONTROL, ADAR1000_ADC_ST_CONV, broadcast);
// This is blocking for now... wait until data is converted, then read it
while (!(Adar_Read(p_adar, REG_ADC_CONTROL) & 0x01))
{
}
data = Adar_Read(p_adar, REG_ADC_OUT);
return(data);
}
/**
* @brief Requests the device info from a specific ADAR and stores it in the
* provided AdarDeviceInfo struct.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param info[out] Struct that contains the device info fields.
*
* @return Returns ADAR_ERROR_NOERROR if information was successfully received and stored in the struct.
*/
uint8_t Adar_GetDeviceInfo(const AdarDevice * p_adar, AdarDeviceInfo * info)
{
*((uint8_t *)info) = Adar_Read(p_adar, 0x002);
info->chip_type = Adar_Read(p_adar, 0x003);
info->product_id = ((uint16_t)Adar_Read(p_adar, 0x004)) << 8;
info->product_id |= ((uint16_t)Adar_Read(p_adar, 0x005)) & 0x00ff;
info->scratchpad = Adar_Read(p_adar, 0x00A);
info->spi_rev = Adar_Read(p_adar, 0x00B);
info->vendor_id = ((uint16_t)Adar_Read(p_adar, 0x00C)) << 8;
info->vendor_id |= ((uint16_t)Adar_Read(p_adar, 0x00D)) & 0x00ff;
info->rev_id = Adar_Read(p_adar, 0x045);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Read the data that is stored in a single ADAR register.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param mem_addr Memory address of the register you wish to read from.
*
* @return Returns the byte of data that is stored in the desired register.
*
* @warning This function will clear ADDR_ASCN bits.
* @warning The ADAR does not allow for block reads.
*/
uint8_t Adar_Read(const AdarDevice * p_adar, uint32_t mem_addr)
{
uint8_t instruction[3];
// Set SDO active
Adar_Write(p_adar, REG_INTERFACE_CONFIG_A, INTERFACE_CONFIG_A_SDO_ACTIVE, 0);
instruction[0] = 0x80 | ((p_adar->dev_addr & 0x03) << 5);
instruction[0] |= ((0xff00 & mem_addr) >> 8);
instruction[1] = (0xff & mem_addr);
instruction[2] = 0x00;
p_adar->Transfer(instruction, p_adar->p_rx_buffer, ADAR1000_RD_SIZE);
// Set SDO Inactive
Adar_Write(p_adar, REG_INTERFACE_CONFIG_A, 0, 0);
return(p_adar->p_rx_buffer[2]);
}
/**
* @brief Block memory write to an ADAR device.
*
* @pre ADDR_ASCN bits in register zero must be set!
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param mem_addr Memory address of the register you wish to read from.
* @param p_data Pointer to block of data to transfer (must have two unused bytes preceding the data for instruction).
* @param size Size of data in bytes, including the two additional leading bytes.
*
* @warning First two bytes of data will be corrupted if you do not provide two unused leading bytes!
*/
void Adar_ReadBlock(const AdarDevice * p_adar, uint16_t mem_addr, uint8_t * p_data, uint32_t size)
{
// Set SDO active
Adar_Write(p_adar, REG_INTERFACE_CONFIG_A, INTERFACE_CONFIG_A_SDO_ACTIVE | INTERFACE_CONFIG_A_ADDR_ASCN, 0);
// Prepare command
p_data[0] = 0x80 | ((p_adar->dev_addr & 0x03) << 5);
p_data[0] |= ((mem_addr) >> 8) & 0x1F;
p_data[1] = (0xFF & mem_addr);
// Start the transfer
p_adar->Transfer(p_data, p_data, size);
Adar_Write(p_adar, REG_INTERFACE_CONFIG_A, 0, 0);
// Return nothing since we assume this is non-blocking and won't wait around
}
/**
* @brief Sets the Rx/Tx bias currents for the LNA, VM, and VGA to be in either
* low power setting or nominal setting.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param p_bias[in] An AdarBiasCurrents struct filled with bias settings
* as seen in the datasheet Table 6. SPI Settings for
* Different Power Modules
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns ADAR_ERR_NOERROR if the bias currents were set
*/
uint8_t Adar_SetBiasCurrents(const AdarDevice * p_adar, AdarBiasCurrents * p_bias, uint8_t broadcast)
{
uint8_t bias = 0;
// RX LNA/VGA/VM bias
bias = (p_bias->rx_lna & 0x0f);
Adar_Write(p_adar, REG_BIAS_CURRENT_RX_LNA, bias, broadcast); // RX LNA bias
bias = (p_bias->rx_vga & 0x07 << 3) | (p_bias->rx_vm & 0x07);
Adar_Write(p_adar, REG_BIAS_CURRENT_RX, bias, broadcast); // RX VM/VGA bias
// TX VGA/VM/DRV bias
bias = (p_bias->tx_vga & 0x07 << 3) | (p_bias->tx_vm & 0x07);
Adar_Write(p_adar, REG_BIAS_CURRENT_TX, bias, broadcast); // TX VM/VGA bias
bias = (p_bias->tx_drv & 0x07);
Adar_Write(p_adar, REG_BIAS_CURRENT_TX_DRV, bias, broadcast); // TX DRV bias
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Set the bias ON and bias OFF voltages for the four PA's and one LNA.
*
* @pre This will set all 5 bias ON values and all 5 bias OFF values at once.
* To enable these bias values, please see the data sheet and ensure that the BIAS_CTRL,
* LNA_BIAS_OUT_EN, TR_SOURCE, TX_EN, RX_EN, TR (input to chip), and PA_ON (input to chip)
* bits have all been properly set.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param bias_on_voltage Array that contains the bias ON voltages.
* @param bias_off_voltage Array that contains the bias OFF voltages.
*
* @return Returns ADAR_ERR_NOERROR if the bias currents were set
*/
uint8_t Adar_SetBiasVoltages(const AdarDevice * p_adar, uint8_t bias_on_voltage[5], uint8_t bias_off_voltage[5])
{
Adar_SetBit(p_adar, 0x30, 6, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x31, 2, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x38, 5, BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH1_BIAS_ON,bias_on_voltage[0], BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH2_BIAS_ON,bias_on_voltage[1], BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH3_BIAS_ON,bias_on_voltage[2], BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH4_BIAS_ON,bias_on_voltage[3], BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH1_BIAS_OFF,bias_off_voltage[0], BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH2_BIAS_OFF,bias_off_voltage[1], BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH3_BIAS_OFF,bias_off_voltage[2], BROADCAST_OFF);
Adar_Write(p_adar, REG_PA_CH4_BIAS_OFF,bias_off_voltage[3], BROADCAST_OFF);
Adar_SetBit(p_adar, 0x30, 4, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x30, 6, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x31, 2, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x38, 5, BROADCAST_OFF);
Adar_Write(p_adar, REG_LNA_BIAS_ON,bias_on_voltage[4], BROADCAST_OFF);
Adar_Write(p_adar, REG_LNA_BIAS_OFF,bias_off_voltage[4], BROADCAST_OFF);
Adar_ResetBit(p_adar, 0x30, 7, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x31, 2, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x31, 4, BROADCAST_OFF);
Adar_SetBit(p_adar, 0x31, 7, BROADCAST_OFF);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Setup the ADAR to use settings that are transferred over SPI.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns ADAR_ERR_NOERROR if the bias currents were set
*/
uint8_t Adar_SetRamBypass(const AdarDevice * p_adar, uint8_t broadcast)
{
uint8_t data;
data = (MEM_CTRL_BIAS_RAM_BYPASS | MEM_CTRL_BEAM_RAM_BYPASS);
Adar_Write(p_adar, REG_MEM_CTL, data, broadcast);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Set the VGA gain value of a Receive channel in dB.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param channel Channel in which to set the gain (1-4).
* @param vga_gain_db Gain to be applied to the channel, ranging from 0 - 30 dB.
* (Intended operation >16 dB).
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns ADAR_ERROR_NOERROR if the gain was successfully set.
* ADAR_ERROR_FAILED if an invalid channel was selected.
*
* @warning 0 dB or 15 dB step attenuator may also be turned on, which is why intended operation is >16 dB.
*/
uint8_t Adar_SetRxVgaGain(const AdarDevice * p_adar, uint8_t channel, uint8_t vga_gain_db, uint8_t broadcast)
{
uint8_t vga_gain_bits = (uint8_t)(255*vga_gain_db/16);
uint32_t mem_addr = 0;
if((channel == 0) || (channel > 4))
{
return(ADAR_ERROR_FAILED);
}
mem_addr = REG_CH1_RX_GAIN + (channel & 0x03);
// Set gain
Adar_Write(p_adar, mem_addr, vga_gain_bits, broadcast);
// Load the new setting
Adar_Write(p_adar, REG_LOAD_WORKING, 0x1, broadcast);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Set the phase of a given receive channel using the I/Q vector modulator.
*
* @pre According to the given @param phase, this sets the polarity (bit 5) and gain (bits 4-0)
* of the @param channel, and then loads them into the working register.
* A vector modulator I/Q look-up table has been provided at the beginning of this library.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param channel Channel in which to set the gain (1-4).
* @param phase Byte that is used to set the polarity (bit 5) and gain (bits 4-0).
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns ADAR_ERROR_NOERROR if the phase was successfully set.
* ADAR_ERROR_FAILED if an invalid channel was selected.
*
* @note To obtain your phase:
* phase = degrees * 128;
* phase /= 360;
*/
uint8_t Adar_SetRxPhase(const AdarDevice * p_adar, uint8_t channel, uint8_t phase, uint8_t broadcast)
{
uint8_t i_val = 0;
uint8_t q_val = 0;
uint32_t mem_addr_i, mem_addr_q;
if((channel == 0) || (channel > 4))
{
return(ADAR_ERROR_FAILED);
}
//phase = phase % 128;
i_val = VM_I[phase];
q_val = VM_Q[phase];
mem_addr_i = REG_CH1_RX_PHS_I + (channel & 0x03) * 2;
mem_addr_q = REG_CH1_RX_PHS_Q + (channel & 0x03) * 2;
Adar_Write(p_adar, mem_addr_i, i_val, broadcast);
Adar_Write(p_adar, mem_addr_q, q_val, broadcast);
Adar_Write(p_adar, REG_LOAD_WORKING, 0x1, broadcast);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Set the VGA gain value of a Tx channel in dB.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns ADAR_ERROR_NOERROR if the bias was successfully set.
* ADAR_ERROR_FAILED if an invalid channel was selected.
*
* @warning 0 dB or 15 dB step attenuator may also be turned on, which is why intended operation is >16 dB.
*/
uint8_t Adar_SetTxBias(const AdarDevice * p_adar, uint8_t broadcast)
{
uint8_t vga_bias_bits;
uint8_t drv_bias_bits;
uint32_t mem_vga_bias;
uint32_t mem_drv_bias;
mem_vga_bias = REG_BIAS_CURRENT_TX;
mem_drv_bias = REG_BIAS_CURRENT_TX_DRV;
// Set bias to nom
vga_bias_bits = 0x2D;
drv_bias_bits = 0x06;
// Set bias
Adar_Write(p_adar, mem_vga_bias, vga_bias_bits, broadcast);
// Set bias
Adar_Write(p_adar, mem_drv_bias, drv_bias_bits, broadcast);
// Load the new setting
Adar_Write(p_adar, REG_LOAD_WORKING, 0x2, broadcast);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Set the VGA gain value of a Tx channel.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param channel Tx channel in which to set the gain, ranging from 1 - 4.
* @param gain Gain to be applied to the channel, ranging from 0 - 127,
* plus the MSb 15dB attenuator (Intended operation >16 dB).
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns ADAR_ERROR_NOERROR if the gain was successfully set.
* ADAR_ERROR_FAILED if an invalid channel was selected.
*
* @warning 0 dB or 15 dB step attenuator may also be turned on, which is why intended operation is >16 dB.
*/
uint8_t Adar_SetTxVgaGain(const AdarDevice * p_adar, uint8_t channel, uint8_t gain, uint8_t broadcast)
{
uint32_t mem_addr;
if((channel == 0) || (channel > 4))
{
return(ADAR_ERROR_FAILED);
}
mem_addr = REG_CH1_TX_GAIN + (channel & 0x03);
// Set gain
Adar_Write(p_adar, mem_addr, gain, broadcast);
// Load the new setting
Adar_Write(p_adar, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Set the phase of a given transmit channel using the I/Q vector modulator.
*
* @pre According to the given @param phase, this sets the polarity (bit 5) and gain (bits 4-0)
* of the @param channel, and then loads them into the working register.
* A vector modulator I/Q look-up table has been provided at the beginning of this library.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param channel Channel in which to set the gain (1-4).
* @param phase Byte that is used to set the polarity (bit 5) and gain (bits 4-0).
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*
* @return Returns ADAR_ERROR_NOERROR if the phase was successfully set.
* ADAR_ERROR_FAILED if an invalid channel was selected.
*
* @note To obtain your phase:
* phase = degrees * 128;
* phase /= 360;
*/
uint8_t Adar_SetTxPhase(const AdarDevice * p_adar, uint8_t channel, uint8_t phase, uint8_t broadcast)
{
uint8_t i_val = 0;
uint8_t q_val = 0;
uint32_t mem_addr_i, mem_addr_q;
if((channel == 0) || (channel > 4))
{
return(ADAR_ERROR_FAILED);
}
//phase = phase % 128;
i_val = VM_I[phase];
q_val = VM_Q[phase];
mem_addr_i = REG_CH1_TX_PHS_I + (channel & 0x03) * 2;
mem_addr_q = REG_CH1_TX_PHS_Q + (channel & 0x03) * 2;
Adar_Write(p_adar, mem_addr_i, i_val, broadcast);
Adar_Write(p_adar, mem_addr_q, q_val, broadcast);
Adar_Write(p_adar, REG_LOAD_WORKING, 0x1, broadcast);
return(ADAR_ERROR_NOERROR);
}
/**
* @brief Reset the whole ADAR device.
*
* @param p_adar[in] ADAR pointer Which specifies the device and what function
* to use for SPI transfer.
*/
void Adar_SoftReset(const AdarDevice * p_adar)
{
uint8_t instruction[3];
instruction[0] = ((p_adar->dev_addr & 0x03) << 5);
instruction[1] = 0x00;
instruction[2] = 0x81;
p_adar->Transfer(instruction, NULL, sizeof(instruction));
}
/**
* @brief Reset ALL ADAR devices in the SPI chain.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
*/
void Adar_SoftResetAll(const AdarDevice * p_adar)
{
uint8_t instruction[3];
instruction[0] = 0x08;
instruction[1] = 0x00;
instruction[2] = 0x81;
p_adar->Transfer(instruction, NULL, sizeof(instruction));
}
/**
* @brief Write a byte of @param data to the register located at @param mem_addr.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param mem_addr Memory address of the register you wish to read from.
* @param data Byte of data to be stored in the register.
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
if this set to BROADCAST_ON.
*
* @warning If writing the same data to multiple registers, use ADAR_WriteBlock.
*/
void Adar_Write(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t data, uint8_t broadcast)
{
uint8_t instruction[3];
if (broadcast)
{
instruction[0] = 0x08;
}
else
{
instruction[0] = ((p_adar->dev_addr & 0x03) << 5);
}
instruction[0] |= (0x1F00 & mem_addr) >> 8;
instruction[1] = (0xFF & mem_addr);
instruction[2] = data;
p_adar->Transfer(instruction, NULL, sizeof(instruction));
}
/**
* @brief Block memory write to an ADAR device.
*
* @pre ADDR_ASCN BITS IN REGISTER ZERO MUST BE SET!
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param mem_addr Memory address of the register you wish to read from.
* @param p_data[in] Pointer to block of data to transfer (must have two unused bytes
preceding the data for instruction).
* @param size Size of data in bytes, including the two additional leading bytes.
*
* @warning First two bytes of data will be corrupted if you do not provide two unused leading bytes!
*/
void Adar_WriteBlock(const AdarDevice * p_adar, uint16_t mem_addr, uint8_t * p_data, uint32_t size)
{
// Prepare command
p_data[0] = ((p_adar->dev_addr & 0x03) << 5);
p_data[0] |= ((mem_addr) >> 8) & 0x1F;
p_data[1] = (0xFF & mem_addr);
// Start the transfer
p_adar->Transfer(p_data, NULL, size);
// Return nothing since we assume this is non-blocking and won't wait around
}
/**
* @brief Set contents of the INTERFACE_CONFIG_A register.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param flags #INTERFACE_CONFIG_A_SOFTRESET, #INTERFACE_CONFIG_A_LSB_FIRST,
* #INTERFACE_CONFIG_A_ADDR_ASCN, #INTERFACE_CONFIG_A_SDO_ACTIVE
* @param broadcast Send the message as a broadcast to all ADARs in the SPI chain
* if this set to BROADCAST_ON.
*/
void Adar_WriteConfigA(const AdarDevice * p_adar, uint8_t flags, uint8_t broadcast)
{
Adar_Write(p_adar, 0x00, flags, broadcast);
}
/**
* @brief Write a byte of @param data to the register located at @param mem_addr and
* then read from the device and verify that the register was correctly set.
*
* @param p_adar[in] Adar pointer Which specifies the device and what function
* to use for SPI transfer.
* @param mem_addr Memory address of the register you wish to read from.
* @param data Byte of data to be stored in the register.
*
* @return Returns the number of attempts that it took to successfully write to a register,
* starting from zero.
* @warning This function currently only supports writes to a single regiter in a single ADAR.
*/
uint8_t Adar_WriteVerify(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t data)
{
uint8_t rx_data;
for (uint8_t ii = 0; ii < 3; ii++)
{
Adar_Write(p_adar, mem_addr, data, 0);
// Can't read back from an ADAR with HW address 0
if (!((p_adar->dev_addr) % 4))
{
return(ADAR_ERROR_INVALIDADDR);
}
rx_data = Adar_Read(p_adar, mem_addr);
if (rx_data == data)
{
return(ii);
}
}
return(ADAR_ERROR_FAILED);
}
void Adar_SetBit(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t bit, uint8_t broadcast)
{
uint8_t temp = Adar_Read(p_adar, mem_addr);
uint8_t data = temp|(1<<bit);
Adar_Write(p_adar,mem_addr, data,broadcast);
}
void Adar_ResetBit(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t bit, uint8_t broadcast)
{
uint8_t temp = Adar_Read(p_adar, mem_addr);
uint8_t data = temp&~(1<<bit);
Adar_Write(p_adar,mem_addr, data,broadcast);
}
9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/adar1000.h
+294
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@@ -0,0 +1,294 @@
/**
* MIT License
*
* Copyright (c) 2020 Jimmy Pentz
*
* Reach me at: github.com/jgpentz, jpentz1( at )gmail.com
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sells
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/* ADAR1000 4-Channel, X Band and Ku Band Beamformer */
#ifndef LIB_ADAR1000_H_
#define LIB_ADAR1000_H_
#ifndef NULL
#define NULL (0)
#endif
// ----------------------------------------------------------------------------
// Includes
// ----------------------------------------------------------------------------
#include "main.h"
#include "stm32f7xx_hal.h"
#include "stm32f7xx_hal_spi.h"
#include "stm32f7xx_hal_gpio.h"
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#ifdef __cplusplus
extern "C" { // Prevent C++ name mangling
#endif
// ----------------------------------------------------------------------------
// Datatypes
// ----------------------------------------------------------------------------
extern SPI_HandleTypeDef hspi1;
extern const uint8_t VM_GAIN[128];
extern const uint8_t VM_I[128];
extern const uint8_t VM_Q[128];
/// A function pointer prototype for a SPI transfer, the 3 parameters would be
/// p_txData, p_rxData, and size (number of bytes to transfer), respectively.
typedef uint32_t (*Adar_SpiTransfer)( uint8_t *, uint8_t *, uint32_t);
typedef struct
{
uint8_t dev_addr; ///< 2-bit device hardware address, 0x00, 0x01, 0x10, 0x11
Adar_SpiTransfer Transfer; ///< Function pointer to the function used for SPI transfers
uint8_t * p_rx_buffer; ///< Data buffer to store received bytes into
}const AdarDevice;
/// Use this to store bias current values into, as seen in the datasheet
/// Table 6. SPI Settings for Different Power Modules
typedef struct
{
uint8_t rx_lna; ///< nominal: 8, low power: 5
uint8_t rx_vm; ///< nominal: 5, low power: 2
uint8_t rx_vga; ///< nominal: 10, low power: 3
uint8_t tx_vm; ///< nominal: 5, low power: 2
uint8_t tx_vga; ///< nominal: 5, low power: 5
uint8_t tx_drv; ///< nominal: 6, low power: 3
} AdarBiasCurrents;
/// Useful for queries regarding the device info
typedef struct
{
uint8_t norm_operating_mode : 2;
uint8_t cust_operating_mode : 2;
uint8_t dev_status : 4;
uint8_t chip_type;
uint16_t product_id;
uint8_t scratchpad;
uint8_t spi_rev;
uint16_t vendor_id;
uint8_t rev_id;
} AdarDeviceInfo;
/// Return types for functions in this library
typedef enum {
ADAR_ERROR_NOERROR = 0,
ADAR_ERROR_FAILED = 1,
ADAR_ERROR_INVALIDADDR = 2,
} AdarErrorCodes;
// ----------------------------------------------------------------------------
// Function Prototypes
// ----------------------------------------------------------------------------
void Adar_AdcInit(const AdarDevice * p_adar, uint8_t broadcast_bit);
uint8_t Adar_AdcRead(const AdarDevice * p_adar, uint8_t broadcast_bit);
uint8_t Adar_GetDeviceInfo(const AdarDevice * p_adar, AdarDeviceInfo * info);
uint8_t Adar_Read(const AdarDevice * p_adar, uint32_t mem_addr);
void Adar_ReadBlock(const AdarDevice * p_adar, uint16_t mem_addr, uint8_t * p_data, uint32_t size);
uint8_t Adar_SetBiasCurrents(const AdarDevice * p_adar, AdarBiasCurrents * p_bias, uint8_t broadcast_bit);
uint8_t Adar_SetBiasVoltages(const AdarDevice * p_adar, uint8_t bias_on_voltage[5], uint8_t bias_off_voltage[5]);
uint8_t Adar_SetRamBypass(const AdarDevice * p_adar, uint8_t broadcast_bit);
uint8_t Adar_SetRxVgaGain(const AdarDevice * p_adar, uint8_t channel, uint8_t vga_gain_db, uint8_t broadcast_bit);
uint8_t Adar_SetRxPhase(const AdarDevice * p_adar, uint8_t channel, uint8_t phase, uint8_t broadcast_bit);
uint8_t Adar_SetTxBias(const AdarDevice * p_adar, uint8_t broadcast_bit);
uint8_t Adar_SetTxVgaGain(const AdarDevice * p_adar, uint8_t channel, uint8_t vga_gain_db, uint8_t broadcast_bit);
uint8_t Adar_SetTxPhase(const AdarDevice * p_adar, uint8_t channel, uint8_t phase, uint8_t broadcast_bit);
void Adar_SoftReset(const AdarDevice * p_adar);
void Adar_SoftResetAll(const AdarDevice * p_adar);
void Adar_Write(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t data, uint8_t broadcast_bit);
void Adar_WriteBlock(const AdarDevice * p_adar, uint16_t mem_addr, uint8_t * p_data, uint32_t size);
void Adar_WriteConfigA(const AdarDevice * p_adar, uint8_t flags, uint8_t broadcast);
uint8_t Adar_WriteVerify(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t data);
void Adar_SetBit(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t bit, uint8_t broadcast);
void Adar_ResetBit(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t bit, uint8_t broadcast);
// ----------------------------------------------------------------------------
// Preprocessor Definitions and Constants
// ----------------------------------------------------------------------------
// Using BROADCAST_ON will send a command to all ADARs that share a bus
#define BROADCAST_OFF 0
#define BROADCAST_ON 1
// The minimum size of a read from the ADARs consists of 3 bytes
#define ADAR1000_RD_SIZE 3
// Address at which the TX RAM starts
#define ADAR_TX_RAM_START_ADDR 0x1800
// ADC Defines
#define ADAR1000_ADC_2MHZ_CLK 0x00
#define ADAR1000_ADC_EN 0x60
#define ADAR1000_ADC_ST_CONV 0x70
/* REGISTER DEFINITIONS */
#define REG_INTERFACE_CONFIG_A 0x000
#define REG_INTERFACE_CONFIG_B 0x001
#define REG_DEV_CONFIG 0x002
#define REG_SCRATCHPAD 0x00A
#define REG_TRANSFER 0x00F
#define REG_CH1_RX_GAIN 0x010
#define REG_CH2_RX_GAIN 0x011
#define REG_CH3_RX_GAIN 0x012
#define REG_CH4_RX_GAIN 0x013
#define REG_CH1_RX_PHS_I 0x014
#define REG_CH1_RX_PHS_Q 0x015
#define REG_CH2_RX_PHS_I 0x016
#define REG_CH2_RX_PHS_Q 0x017
#define REG_CH3_RX_PHS_I 0x018
#define REG_CH3_RX_PHS_Q 0x019
#define REG_CH4_RX_PHS_I 0x01A
#define REG_CH4_RX_PHS_Q 0x01B
#define REG_CH1_TX_GAIN 0x01C
#define REG_CH2_TX_GAIN 0x01D
#define REG_CH3_TX_GAIN 0x01E
#define REG_CH4_TX_GAIN 0x01F
#define REG_CH1_TX_PHS_I 0x020
#define REG_CH1_TX_PHS_Q 0x021
#define REG_CH2_TX_PHS_I 0x022
#define REG_CH2_TX_PHS_Q 0x023
#define REG_CH3_TX_PHS_I 0x024
#define REG_CH3_TX_PHS_Q 0x025
#define REG_CH4_TX_PHS_I 0x026
#define REG_CH4_TX_PHS_Q 0x027
#define REG_LOAD_WORKING 0x028
#define REG_PA_CH1_BIAS_ON 0x029
#define REG_PA_CH2_BIAS_ON 0x02A
#define REG_PA_CH3_BIAS_ON 0x02B
#define REG_PA_CH4_BIAS_ON 0x02C
#define REG_LNA_BIAS_ON 0x02D
#define REG_RX_ENABLES 0x02E
#define REG_TX_ENABLES 0x02F
#define REG_MISC_ENABLES 0x030
#define REG_SW_CONTROL 0x031
#define REG_ADC_CONTROL 0x032
#define REG_ADC_CONTROL_TEMP_EN 0xf0
#define REG_ADC_OUT 0x033
#define REG_BIAS_CURRENT_RX_LNA 0x034
#define REG_BIAS_CURRENT_RX 0x035
#define REG_BIAS_CURRENT_TX 0x036
#define REG_BIAS_CURRENT_TX_DRV 0x037
#define REG_MEM_CTL 0x038
#define REG_RX_CHX_MEM 0x039
#define REG_TX_CHX_MEM 0x03A
#define REG_RX_CH1_MEM 0x03D
#define REG_RX_CH2_MEM 0x03E
#define REG_RX_CH3_MEM 0x03F
#define REG_RX_CH4_MEM 0x040
#define REG_TX_CH1_MEM 0x041
#define REG_TX_CH2_MEM 0x042
#define REG_TX_CH3_MEM 0x043
#define REG_TX_CH4_MEM 0x044
#define REG_PA_CH1_BIAS_OFF 0x046
#define REG_PA_CH2_BIAS_OFF 0x047
#define REG_PA_CH3_BIAS_OFF 0x048
#define REG_PA_CH4_BIAS_OFF 0x049
#define REG_LNA_BIAS_OFF 0x04A
#define REG_TX_BEAM_STEP_START 0x04D
#define REG_TX_BEAM_STEP_STOP 0x04E
#define REG_RX_BEAM_STEP_START 0x04F
#define REG_RX_BEAM_STEP_STOP 0x050
// REGISTER CONSTANTS
#define INTERFACE_CONFIG_A_SOFTRESET ((1 << 7) | (1 << 0))
#define INTERFACE_CONFIG_A_LSB_FIRST ((1 << 6) | (1 << 1))
#define INTERFACE_CONFIG_A_ADDR_ASCN ((1 << 5) | (1 << 2))
#define INTERFACE_CONFIG_A_SDO_ACTIVE ((1 << 4) | (1 << 3))
#define LD_WRK_REGS_LDRX_OVERRIDE (1 << 0)
#define LD_WRK_REGS_LDTX_OVERRIDE (1 << 1)
#define RX_ENABLES_TX_VGA_EN (1 << 0)
#define RX_ENABLES_TX_VM_EN (1 << 1)
#define RX_ENABLES_TX_DRV_EN (1 << 2)
#define RX_ENABLES_CH3_TX_EN (1 << 3)
#define RX_ENABLES_CH2_TX_EN (1 << 4)
#define RX_ENABLES_CH1_TX_EN (1 << 5)
#define RX_ENABLES_CH0_TX_EN (1 << 6)
#define TX_ENABLES_TX_VGA_EN (1 << 0)
#define TX_ENABLES_TX_VM_EN (1 << 1)
#define TX_ENABLES_TX_DRV_EN (1 << 2)
#define TX_ENABLES_CH3_TX_EN (1 << 3)
#define TX_ENABLES_CH2_TX_EN (1 << 4)
#define TX_ENABLES_CH1_TX_EN (1 << 5)
#define TX_ENABLES_CH0_TX_EN (1 << 6)
#define MISC_ENABLES_CH4_DET_EN (1 << 0)
#define MISC_ENABLES_CH3_DET_EN (1 << 1)
#define MISC_ENABLES_CH2_DET_EN (1 << 2)
#define MISC_ENABLES_CH1_DET_EN (1 << 3)
#define MISC_ENABLES_LNA_BIAS_OUT_EN (1 << 4)
#define MISC_ENABLES_BIAS_EN (1 << 5)
#define MISC_ENABLES_BIAS_CTRL (1 << 6)
#define MISC_ENABLES_SW_DRV_TR_MODE_SEL (1 << 7)
#define SW_CTRL_POL (1 << 0)
#define SW_CTRL_TR_SPI (1 << 1)
#define SW_CTRL_TR_SOURCE (1 << 2)
#define SW_CTRL_SW_DRV_EN_POL (1 << 3)
#define SW_CTRL_SW_DRV_EN_TR (1 << 4)
#define SW_CTRL_RX_EN (1 << 5)
#define SW_CTRL_TX_EN (1 << 6)
#define SW_CTRL_SW_DRV_TR_STATE (1 << 7)
#define MEM_CTRL_RX_CHX_RAM_BYPASS (1 << 0)
#define MEM_CTRL_TX_CHX_RAM_BYPASS (1 << 1)
#define MEM_CTRL_RX_BEAM_STEP_EN (1 << 2)
#define MEM_CTRL_TX_BEAM_STEP_EN (1 << 3)
#define MEM_CTRL_BIAS_RAM_BYPASS (1 << 5)
#define MEM_CTRL_BEAM_RAM_BYPASS (1 << 6)
#define MEM_CTRL_SCAN_MODE_EN (1 << 7)
#ifdef __cplusplus
} // End extern "C"
#endif
#endif /* LIB_ADAR1000_H_ */
9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.h
+1 -1
View File
@@ -112,7 +112,7 @@ extern "C" {
* "BF" -- ADAR1000 beamformer
* "PA" -- Power amplifier bias/monitoring
* "FPGA" -- FPGA communication and handshake
* "USB" -- USB data path (FT2232H production / FT601 premium)
* "USB" -- FT601 USB data path
* "PWR" -- Power sequencing and rail monitoring
* "IMU" -- IMU/GPS/barometer sensors
* "MOT" -- Stepper motor/scan mechanics
9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/main.cpp
+106 -173
View File
@@ -21,6 +21,7 @@
#include "usb_device.h"
#include "USBHandler.h"
#include "usbd_cdc_if.h"
#include "adar1000.h"
#include "ADAR1000_Manager.h"
#include "ADAR1000_AGC.h"
extern "C" {
@@ -45,9 +46,7 @@ extern "C" {
#include <vector>
#include "stm32_spi.h"
#include "stm32_delay.h"
extern "C" {
#include "um982_gps.h"
}
#include "TinyGPSPlus.h"
extern "C" {
#include "GY_85_HAL.h"
}
@@ -122,8 +121,8 @@ UART_HandleTypeDef huart5;
UART_HandleTypeDef huart3;
/* USER CODE BEGIN PV */
// UM982 dual-antenna GPS receiver
UM982_GPS_t um982;
// The TinyGPSPlus object
TinyGPSPlus gps;
// Global data structures
GPS_Data_t current_gps_data = {0};
@@ -174,7 +173,7 @@ float RADAR_Altitude;
double RADAR_Longitude = 0;
double RADAR_Latitude = 0;
extern uint8_t GUI_start_flag_received; // [STM32-006] Legacy, unused -- kept for linker compat
extern uint8_t GUI_start_flag_received;
//RADAR
@@ -621,8 +620,7 @@ typedef enum {
ERROR_POWER_SUPPLY,
ERROR_TEMPERATURE_HIGH,
ERROR_MEMORY_ALLOC,
ERROR_WATCHDOG_TIMEOUT,
ERROR_COUNT // must be last — used for bounds checking error_strings[]
ERROR_WATCHDOG_TIMEOUT
} SystemError_t;
static SystemError_t last_error = ERROR_NONE;
@@ -633,41 +631,20 @@ static bool system_emergency_state = false;
SystemError_t checkSystemHealth(void) {
SystemError_t current_error = ERROR_NONE;
// 0. Watchdog: detect main-loop stall (checkSystemHealth not called for >60 s).
// Timestamp is captured at function ENTRY and updated unconditionally, so
// any early return from a sub-check below cannot leave a stale value that
// would later trip a spurious ERROR_WATCHDOG_TIMEOUT. A dedicated cold-start
// branch ensures the first call after boot never trips (last_health_check==0
// would otherwise make `HAL_GetTick() - 0 > 60000` true forever after the
// 60-s mark of the init sequence).
static uint32_t last_health_check = 0;
uint32_t now_tick = HAL_GetTick();
if (last_health_check == 0) {
last_health_check = now_tick; // cold start: seed only
} else {
uint32_t elapsed = now_tick - last_health_check;
last_health_check = now_tick; // update BEFORE any early return
if (elapsed > 60000) {
current_error = ERROR_WATCHDOG_TIMEOUT;
DIAG_ERR("SYS", "Health check: Watchdog timeout (>60s since last check)");
return current_error;
}
}
// 1. Check AD9523 Clock Generator
static uint32_t last_clock_check = 0;
if (HAL_GetTick() - last_clock_check > 5000) {
GPIO_PinState s0 = HAL_GPIO_ReadPin(AD9523_STATUS0_GPIO_Port, AD9523_STATUS0_Pin);
GPIO_PinState s1 = HAL_GPIO_ReadPin(AD9523_STATUS1_GPIO_Port, AD9523_STATUS1_Pin);
DIAG_GPIO("CLK", "AD9523 STATUS0", s0);
DIAG_GPIO("CLK", "AD9523 STATUS1", s1);
if (s0 == GPIO_PIN_RESET || s1 == GPIO_PIN_RESET) {
current_error = ERROR_AD9523_CLOCK;
DIAG_ERR("CLK", "AD9523 clock health check FAILED (STATUS0=%d STATUS1=%d)", s0, s1);
return current_error;
}
last_clock_check = HAL_GetTick();
}
if (HAL_GetTick() - last_clock_check > 5000) {
GPIO_PinState s0 = HAL_GPIO_ReadPin(AD9523_STATUS0_GPIO_Port, AD9523_STATUS0_Pin);
GPIO_PinState s1 = HAL_GPIO_ReadPin(AD9523_STATUS1_GPIO_Port, AD9523_STATUS1_Pin);
DIAG_GPIO("CLK", "AD9523 STATUS0", s0);
DIAG_GPIO("CLK", "AD9523 STATUS1", s1);
if (s0 == GPIO_PIN_RESET || s1 == GPIO_PIN_RESET) {
current_error = ERROR_AD9523_CLOCK;
DIAG_ERR("CLK", "AD9523 clock health check FAILED (STATUS0=%d STATUS1=%d)", s0, s1);
return current_error;
}
last_clock_check = HAL_GetTick();
}
// 2. Check ADF4382 Lock Status
bool tx_locked, rx_locked;
@@ -702,34 +679,37 @@ SystemError_t checkSystemHealth(void) {
// 4. Check IMU Communication
static uint32_t last_imu_check = 0;
if (HAL_GetTick() - last_imu_check > 10000) {
if (!GY85_Update(&imu)) {
current_error = ERROR_IMU_COMM;
DIAG_ERR("IMU", "Health check: GY85_Update() FAILED");
return current_error;
}
last_imu_check = HAL_GetTick();
}
if (HAL_GetTick() - last_imu_check > 10000) {
if (!GY85_Update(&imu)) {
current_error = ERROR_IMU_COMM;
DIAG_ERR("IMU", "Health check: GY85_Update() FAILED");
return current_error;
}
last_imu_check = HAL_GetTick();
}
// 5. Check BMP180 Communication
static uint32_t last_bmp_check = 0;
if (HAL_GetTick() - last_bmp_check > 15000) {
double pressure = myBMP.getPressure();
if (pressure < 30000.0 || pressure > 110000.0 || isnan(pressure)) {
current_error = ERROR_BMP180_COMM;
DIAG_ERR("SYS", "Health check: BMP180 pressure out of range: %.0f", pressure);
return current_error;
}
last_bmp_check = HAL_GetTick();
}
if (HAL_GetTick() - last_bmp_check > 15000) {
double pressure = myBMP.getPressure();
if (pressure < 30000.0 || pressure > 110000.0 || isnan(pressure)) {
current_error = ERROR_BMP180_COMM;
DIAG_ERR("SYS", "Health check: BMP180 pressure out of range: %.0f", pressure);
return current_error;
}
last_bmp_check = HAL_GetTick();
}
// 6. Check GPS Communication (30s grace period from boot / last valid fix)
uint32_t gps_fix_age = um982_position_age(&um982);
if (gps_fix_age > 30000) {
current_error = ERROR_GPS_COMM;
DIAG_WARN("SYS", "Health check: GPS no fix for >30s (age=%lu ms)", (unsigned long)gps_fix_age);
return current_error;
}
// 6. Check GPS Communication
static uint32_t last_gps_fix = 0;
if (gps.location.isUpdated()) {
last_gps_fix = HAL_GetTick();
}
if (HAL_GetTick() - last_gps_fix > 30000) {
current_error = ERROR_GPS_COMM;
DIAG_WARN("SYS", "Health check: GPS no fix for >30s");
return current_error;
}
// 7. Check RF Power Amplifier Current
if (PowerAmplifier) {
@@ -754,7 +734,14 @@ SystemError_t checkSystemHealth(void) {
return current_error;
}
// 9. Watchdog check is performed at function entry (see step 0).
// 9. Simple watchdog check
static uint32_t last_health_check = 0;
if (HAL_GetTick() - last_health_check > 60000) {
current_error = ERROR_WATCHDOG_TIMEOUT;
DIAG_ERR("SYS", "Health check: Watchdog timeout (>60s since last check)");
return current_error;
}
last_health_check = HAL_GetTick();
if (current_error != ERROR_NONE) {
DIAG_ERR("SYS", "checkSystemHealth returning error code %d", current_error);
@@ -866,7 +853,7 @@ void handleSystemError(SystemError_t error) {
DIAG_ERR("SYS", "handleSystemError: error=%d error_count=%lu", error, error_count);
char error_msg[100];
static const char* const error_strings[] = {
const char* error_strings[] = {
"No error",
"AD9523 Clock failure",
"ADF4382 TX LO unlocked",
@@ -886,16 +873,9 @@ void handleSystemError(SystemError_t error) {
"Watchdog timeout"
};
static_assert(sizeof(error_strings) / sizeof(error_strings[0]) == ERROR_COUNT,
"error_strings[] and SystemError_t enum are out of sync");
const char* err_name = (error >= 0 && error < (int)(sizeof(error_strings) / sizeof(error_strings[0])))
? error_strings[error]
: "Unknown error";
snprintf(error_msg, sizeof(error_msg),
"ERROR #%d: %s (Count: %lu)\r\n",
error, err_name, error_count);
error, error_strings[error], error_count);
HAL_UART_Transmit(&huart3, (uint8_t*)error_msg, strlen(error_msg), 1000);
// Blink LED pattern based on error code
@@ -905,23 +885,9 @@ void handleSystemError(SystemError_t error) {
HAL_Delay(200);
}
// Critical errors trigger emergency shutdown.
//
// Safety-critical range: any fault that can damage the PAs or leave the
// system in an undefined state must cut the RF rails via Emergency_Stop().
// This covers:
// ERROR_RF_PA_OVERCURRENT .. ERROR_POWER_SUPPLY (9..13) -- PA/supply faults
// ERROR_TEMPERATURE_HIGH (14) -- >75 C on the PA thermal sensors;
// without cutting bias + 5V/5V5/RFPA rails
// the GaN QPA2962 stage can thermal-runaway.
// ERROR_WATCHDOG_TIMEOUT (16) -- health-check loop has stalled (>60 s);
// transmitter state is unknown, safest to
// latch Emergency_Stop rather than rely on
// IWDG reset (which re-energises the rails).
if ((error >= ERROR_RF_PA_OVERCURRENT && error <= ERROR_POWER_SUPPLY) ||
error == ERROR_TEMPERATURE_HIGH ||
error == ERROR_WATCHDOG_TIMEOUT) {
DIAG_ERR("SYS", "CRITICAL ERROR (code %d: %s) -- initiating Emergency_Stop()", error, err_name);
// Critical errors trigger emergency shutdown
if (error >= ERROR_RF_PA_OVERCURRENT && error <= ERROR_POWER_SUPPLY) {
DIAG_ERR("SYS", "CRITICAL ERROR (code %d: %s) -- initiating Emergency_Stop()", error, error_strings[error]);
snprintf(error_msg, sizeof(error_msg),
"CRITICAL ERROR! Initiating emergency shutdown.\r\n");
HAL_UART_Transmit(&huart3, (uint8_t*)error_msg, strlen(error_msg), 1000);
@@ -1054,7 +1020,20 @@ static inline void delay_ms(uint32_t ms) { HAL_Delay(ms); }
// smartDelay removed -- replaced by non-blocking um982_process() in main loop
// This custom version of delay() ensures that the gps object
// is being "fed".
static void smartDelay(unsigned long ms)
{
uint32_t start = HAL_GetTick();
uint8_t ch;
do {
// While there is new data available in UART (non-blocking)
if (HAL_UART_Receive(&huart5, &ch, 1, 0) == HAL_OK) {
gps.encode(ch); // Pass received byte to TinyGPS++ equivalent parser
}
} while (HAL_GetTick() - start < ms);
}
// Small helper to enable DWT cycle counter for microdelay
static void DWT_Init(void)
@@ -1198,14 +1177,7 @@ static int configure_ad9523(void)
// init ad9523 defaults (fills any missing pdata defaults)
DIAG("CLK", "Calling ad9523_init() -- fills pdata defaults");
{
int32_t init_ret = ad9523_init(&init_param);
DIAG("CLK", "ad9523_init() returned %ld", (long)init_ret);
if (init_ret != 0) {
DIAG_ERR("CLK", "ad9523_init() FAILED (ret=%ld)", (long)init_ret);
return -1;
}
}
ad9523_init(&init_param);
/* [Bug #2 FIXED] Removed first ad9523_setup() call that was here.
* It wrote to the chip while still in reset — writes were lost.
@@ -1594,12 +1566,6 @@ int main(void)
Yaw_Sensor = (180*atan2(magRawY,magRawX)/PI) - Mag_Declination;
if(Yaw_Sensor<0)Yaw_Sensor+=360;
// Override magnetometer heading with UM982 dual-antenna heading when available
if (um982_is_heading_valid(&um982)) {
Yaw_Sensor = um982_get_heading(&um982);
}
RxEst_0 = RxEst_1;
RyEst_0 = RyEst_1;
RzEst_0 = RzEst_1;
@@ -1775,38 +1741,14 @@ int main(void)
//////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////GPS/////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////
DIAG_SECTION("GPS INIT (UM982)");
DIAG("GPS", "Initializing UM982 on UART5 @ 115200 (baseline=50cm, tol=3cm)");
if (!um982_init(&um982, &huart5, 50.0f, 3.0f)) {
DIAG_WARN("GPS", "UM982 init: no VERSIONA response -- module may need more time");
// Not fatal: module may still start sending NMEA data after boot
} else {
DIAG("GPS", "UM982 init OK -- VERSIONA received");
for(int i=0; i<10;i++){
smartDelay(1000);
RADAR_Longitude = gps.location.lng();
RADAR_Latitude = gps.location.lat();
}
// Collect GPS data for a few seconds (non-blocking pump)
DIAG("GPS", "Pumping GPS for 5 seconds to acquire initial fix...");
{
uint32_t gps_start = HAL_GetTick();
while (HAL_GetTick() - gps_start < 5000) {
um982_process(&um982);
HAL_Delay(10);
}
}
RADAR_Longitude = um982_get_longitude(&um982);
RADAR_Latitude = um982_get_latitude(&um982);
DIAG("GPS", "Initial position: lat=%.6f lon=%.6f fix=%d sats=%d",
RADAR_Latitude, RADAR_Longitude,
um982_get_fix_quality(&um982), um982_get_num_sats(&um982));
// Re-apply heading after GPS init so the north-alignment stepper move uses
// UM982 dual-antenna heading when available.
if (um982_is_heading_valid(&um982)) {
Yaw_Sensor = um982_get_heading(&um982);
}
//move Stepper to position 1 = 0°
HAL_GPIO_WritePin(STEPPER_CW_P_GPIO_Port, STEPPER_CW_P_Pin, GPIO_PIN_RESET);//Set stepper motor spinning direction to CCW
//move Stepper to position 1 = 0°
HAL_GPIO_WritePin(STEPPER_CW_P_GPIO_Port, STEPPER_CW_P_Pin, GPIO_PIN_RESET);//Set stepper motor spinning direction to CCW
//Point Stepper to North
for(int i= 0;i<(int)(Yaw_Sensor*Stepper_steps/360);i++){
HAL_GPIO_WritePin(STEPPER_CLK_P_GPIO_Port, STEPPER_CLK_P_Pin, GPIO_PIN_SET);
@@ -1828,11 +1770,29 @@ int main(void)
HAL_UART_Transmit(&huart3, (uint8_t*)gps_send_error, sizeof(gps_send_error) - 1, 1000);
}
/* [STM32-006 FIXED] Removed blocking do-while loop that waited for
* usbHandler.isStartFlagReceived(). The production V7 PyQt GUI does not
* send the legacy 4-byte start flag [23,46,158,237], so this loop hung
* the MCU at boot indefinitely. The USB settings handshake (if ever
* re-enabled) should be handled non-blocking in the main loop. */
// Check if start flag was received and settings are ready
do{
if (usbHandler.isStartFlagReceived() &&
usbHandler.getState() == USBHandler::USBState::READY_FOR_DATA) {
const RadarSettings& settings = usbHandler.getSettings();
// Use the settings to configure your radar system
/*
settings.getSystemFrequency();
settings.getChirpDuration1();
settings.getChirpDuration2();
settings.getChirpsPerPosition();
settings.getFreqMin();
settings.getFreqMax();
settings.getPRF1();
settings.getPRF2();
settings.getMaxDistance();
*/
}
}while(!usbHandler.isStartFlagReceived());
/***************************************************************/
/************RF Power Amplifier Powering up sequence************/
@@ -2057,18 +2017,6 @@ int main(void)
}
DIAG("SYS", "Exited safe mode blink loop -- system_emergency_state cleared");
}
//////////////////////////////////////////////////////////////////////////////////////
////////////////////////// GPS: Non-blocking NMEA processing ////////////////////////
//////////////////////////////////////////////////////////////////////////////////////
um982_process(&um982);
// Update position globals continuously
if (um982_is_position_valid(&um982)) {
RADAR_Latitude = um982_get_latitude(&um982);
RADAR_Longitude = um982_get_longitude(&um982);
}
//////////////////////////////////////////////////////////////////////////////////////
////////////////////////// Monitor ADF4382A lock status periodically//////////////////
//////////////////////////////////////////////////////////////////////////////////////
@@ -2179,24 +2127,9 @@ int main(void)
runRadarPulseSequence();
/* [AGC] Outer-loop AGC: sync enable from FPGA via DIG_6 (PD14),
* then read saturation flag (DIG_5 / PD13) and adjust ADAR1000 VGA
* common gain once per radar frame (~258 ms).
* FPGA register host_agc_enable is the single source of truth —
* DIG_6 propagates it to MCU every frame.
* 2-frame confirmation debounce: only change outerAgc.enabled when
* two consecutive frames read the same DIG_6 value. Prevents a
* single-sample glitch from causing a spurious AGC state transition.
* Added latency: 1 extra frame (~258 ms), acceptable for control plane. */
{
bool dig6_now = (HAL_GPIO_ReadPin(FPGA_DIG6_GPIO_Port,
FPGA_DIG6_Pin) == GPIO_PIN_SET);
static bool dig6_prev = false; // matches boot default (AGC off)
if (dig6_now == dig6_prev) {
outerAgc.enabled = dig6_now;
}
dig6_prev = dig6_now;
}
/* [AGC] Outer-loop AGC: read FPGA saturation flag (DIG_5 / PD13),
* adjust ADAR1000 VGA common gain once per radar frame (~258 ms).
* Only run when AGC is enabled — otherwise leave VGA gains untouched. */
if (outerAgc.enabled) {
bool sat = HAL_GPIO_ReadPin(FPGA_DIG5_SAT_GPIO_Port,
FPGA_DIG5_SAT_Pin) == GPIO_PIN_SET;
@@ -2634,7 +2567,7 @@ static void MX_UART5_Init(void)
/* USER CODE END UART5_Init 1 */
huart5.Instance = UART5;
huart5.Init.BaudRate = 115200;
huart5.Init.BaudRate = 9600;
huart5.Init.WordLength = UART_WORDLENGTH_8B;
huart5.Init.StopBits = UART_STOPBITS_1;
huart5.Init.Parity = UART_PARITY_NONE;
9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/um982_gps.c
-586
View File
@@ -1,586 +0,0 @@
/*******************************************************************************
* um982_gps.c -- UM982 dual-antenna GNSS receiver driver implementation
*
* See um982_gps.h for API documentation.
* Command syntax per Unicore N4 Command Reference EN R1.14.
******************************************************************************/
#include "um982_gps.h"
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
/* ========================= Internal helpers ========================== */
/**
* Advance to the next comma-delimited field in an NMEA sentence.
* Returns pointer to the start of the next field (after the comma),
* or NULL if no more commas found before end-of-string or '*'.
*
* Handles empty fields (consecutive commas) correctly by returning
* a pointer to the character after the comma (which may be another comma).
*/
static const char *next_field(const char *p)
{
if (p == NULL) return NULL;
while (*p != '\0' && *p != ',' && *p != '*') {
p++;
}
if (*p == ',') return p + 1;
return NULL; /* End of sentence or checksum marker */
}
/**
* Get the length of the current field (up to next comma, '*', or '\0').
*/
static int field_len(const char *p)
{
int len = 0;
if (p == NULL) return 0;
while (p[len] != '\0' && p[len] != ',' && p[len] != '*') {
len++;
}
return len;
}
/**
* Check if a field is non-empty (has at least one character before delimiter).
*/
static bool field_valid(const char *p)
{
return p != NULL && field_len(p) > 0;
}
/**
* Parse a floating-point value from a field, returning 0.0 if empty.
*/
static double field_to_double(const char *p)
{
if (!field_valid(p)) return 0.0;
return strtod(p, NULL);
}
static float field_to_float(const char *p)
{
return (float)field_to_double(p);
}
static int field_to_int(const char *p)
{
if (!field_valid(p)) return 0;
return (int)strtol(p, NULL, 10);
}
/* ========================= Checksum ================================== */
bool um982_verify_checksum(const char *sentence)
{
if (sentence == NULL || sentence[0] != '$') return false;
const char *p = sentence + 1; /* Skip '$' */
uint8_t computed = 0;
while (*p != '\0' && *p != '*') {
computed ^= (uint8_t)*p;
p++;
}
if (*p != '*') return false; /* No checksum marker found */
p++; /* Skip '*' */
/* Parse 2-char hex checksum */
if (p[0] == '\0' || p[1] == '\0') return false;
char hex_str[3] = { p[0], p[1], '\0' };
unsigned long expected = strtoul(hex_str, NULL, 16);
return computed == (uint8_t)expected;
}
/* ========================= Coordinate parsing ======================== */
double um982_parse_coord(const char *field, char hemisphere)
{
if (field == NULL || field[0] == '\0') return NAN;
/* Find the decimal point to determine degree digit count.
* Latitude: ddmm.mmmm (dot at index 4, degrees = 2)
* Longitude: dddmm.mmmm (dot at index 5, degrees = 3)
* General: degree_digits = dot_position - 2
*/
const char *dot = strchr(field, '.');
if (dot == NULL) return NAN;
int dot_pos = (int)(dot - field);
int deg_digits = dot_pos - 2;
if (deg_digits < 1 || deg_digits > 3) return NAN;
/* Extract degree portion */
double degrees = 0.0;
for (int i = 0; i < deg_digits; i++) {
if (field[i] < '0' || field[i] > '9') return NAN;
degrees = degrees * 10.0 + (field[i] - '0');
}
/* Extract minutes portion (everything from deg_digits onward) */
double minutes = strtod(field + deg_digits, NULL);
if (minutes < 0.0 || minutes >= 60.0) return NAN;
double result = degrees + minutes / 60.0;
/* Apply hemisphere sign */
if (hemisphere == 'S' || hemisphere == 'W') {
result = -result;
}
return result;
}
/* ========================= Sentence parsers ========================== */
/**
* Identify the NMEA sentence type by skipping the 2-char talker ID
* and comparing the 3-letter formatter.
*
* "$GNGGA,..." -> talker="GN", formatter="GGA"
* "$GPTHS,..." -> talker="GP", formatter="THS"
*
* Returns pointer to the formatter (3 chars at sentence+3), or NULL
* if sentence is too short.
*/
static const char *get_formatter(const char *sentence)
{
/* sentence starts with '$', followed by 2-char talker + 3-char formatter */
if (sentence == NULL || strlen(sentence) < 6) return NULL;
return sentence + 3; /* Skip "$XX" -> points to formatter */
}
/**
* Parse GGA sentence — position and fix quality.
*
* Format: $--GGA,time,lat,N/S,lon,E/W,quality,numSat,hdop,alt,M,geoidSep,M,dgpsAge,refID*XX
* field: 1 2 3 4 5 6 7 8 9 10 11 12 13 14
*/
static void parse_gga(UM982_GPS_t *gps, const char *sentence)
{
/* Skip to first field (after "$XXGGA,") */
const char *f = strchr(sentence, ',');
if (f == NULL) return;
f++; /* f -> field 1 (time) */
/* Field 1: UTC time — skip for now */
const char *f2 = next_field(f); /* lat */
const char *f3 = next_field(f2); /* N/S */
const char *f4 = next_field(f3); /* lon */
const char *f5 = next_field(f4); /* E/W */
const char *f6 = next_field(f5); /* quality */
const char *f7 = next_field(f6); /* numSat */
const char *f8 = next_field(f7); /* hdop */
const char *f9 = next_field(f8); /* altitude */
const char *f10 = next_field(f9); /* M */
const char *f11 = next_field(f10); /* geoid sep */
uint32_t now = HAL_GetTick();
/* Parse fix quality first — if 0, position is meaningless */
gps->fix_quality = (uint8_t)field_to_int(f6);
/* Parse coordinates */
if (field_valid(f2) && field_valid(f3)) {
char hem = field_valid(f3) ? *f3 : 'N';
double lat = um982_parse_coord(f2, hem);
if (!isnan(lat)) gps->latitude = lat;
}
if (field_valid(f4) && field_valid(f5)) {
char hem = field_valid(f5) ? *f5 : 'E';
double lon = um982_parse_coord(f4, hem);
if (!isnan(lon)) gps->longitude = lon;
}
/* Number of satellites */
gps->num_satellites = (uint8_t)field_to_int(f7);
/* HDOP */
if (field_valid(f8)) {
gps->hdop = field_to_float(f8);
}
/* Altitude */
if (field_valid(f9)) {
gps->altitude = field_to_float(f9);
}
/* Geoid separation */
if (field_valid(f11)) {
gps->geoid_sep = field_to_float(f11);
}
gps->last_gga_tick = now;
if (gps->fix_quality != UM982_FIX_NONE) {
gps->last_fix_tick = now;
}
}
/**
* Parse RMC sentence — recommended minimum (position, speed, date).
*
* Format: $--RMC,time,status,lat,N/S,lon,E/W,speed,course,date,magVar,E/W,mode*XX
* field: 1 2 3 4 5 6 7 8 9 10 11 12
*/
static void parse_rmc(UM982_GPS_t *gps, const char *sentence)
{
const char *f = strchr(sentence, ',');
if (f == NULL) return;
f++; /* f -> field 1 (time) */
const char *f2 = next_field(f); /* status */
const char *f3 = next_field(f2); /* lat */
const char *f4 = next_field(f3); /* N/S */
const char *f5 = next_field(f4); /* lon */
const char *f6 = next_field(f5); /* E/W */
const char *f7 = next_field(f6); /* speed knots */
const char *f8 = next_field(f7); /* course true */
/* Status */
if (field_valid(f2)) {
gps->rmc_status = *f2;
}
/* Position (only if status = A for valid) */
if (field_valid(f2) && *f2 == 'A') {
if (field_valid(f3) && field_valid(f4)) {
double lat = um982_parse_coord(f3, *f4);
if (!isnan(lat)) gps->latitude = lat;
}
if (field_valid(f5) && field_valid(f6)) {
double lon = um982_parse_coord(f5, *f6);
if (!isnan(lon)) gps->longitude = lon;
}
}
/* Speed (knots) */
if (field_valid(f7)) {
gps->speed_knots = field_to_float(f7);
}
/* Course */
if (field_valid(f8)) {
gps->course_true = field_to_float(f8);
}
gps->last_rmc_tick = HAL_GetTick();
}
/**
* Parse THS sentence — true heading and status (UM982-specific).
*
* Format: $--THS,heading,mode*XX
* field: 1 2
*/
static void parse_ths(UM982_GPS_t *gps, const char *sentence)
{
const char *f = strchr(sentence, ',');
if (f == NULL) return;
f++; /* f -> field 1 (heading) */
const char *f2 = next_field(f); /* mode */
/* Heading */
if (field_valid(f)) {
gps->heading = field_to_float(f);
} else {
gps->heading = NAN;
}
/* Mode */
if (field_valid(f2)) {
gps->heading_mode = *f2;
} else {
gps->heading_mode = 'V'; /* Not valid if missing */
}
gps->last_ths_tick = HAL_GetTick();
}
/**
* Parse VTG sentence — course and speed over ground.
*
* Format: $--VTG,courseTrue,T,courseMag,M,speedKnots,N,speedKmh,K,mode*XX
* field: 1 2 3 4 5 6 7 8 9
*/
static void parse_vtg(UM982_GPS_t *gps, const char *sentence)
{
const char *f = strchr(sentence, ',');
if (f == NULL) return;
f++; /* f -> field 1 (course true) */
const char *f2 = next_field(f); /* T */
const char *f3 = next_field(f2); /* course mag */
const char *f4 = next_field(f3); /* M */
const char *f5 = next_field(f4); /* speed knots */
const char *f6 = next_field(f5); /* N */
const char *f7 = next_field(f6); /* speed km/h */
/* Course true */
if (field_valid(f)) {
gps->course_true = field_to_float(f);
}
/* Speed knots */
if (field_valid(f5)) {
gps->speed_knots = field_to_float(f5);
}
/* Speed km/h */
if (field_valid(f7)) {
gps->speed_kmh = field_to_float(f7);
}
gps->last_vtg_tick = HAL_GetTick();
}
/* ========================= Sentence dispatch ========================= */
void um982_parse_sentence(UM982_GPS_t *gps, const char *sentence)
{
if (sentence == NULL || sentence[0] != '$') return;
/* Verify checksum before parsing */
if (!um982_verify_checksum(sentence)) return;
/* Check for VERSIONA response (starts with '#', not '$') -- handled separately */
/* Actually VERSIONA starts with '#', so it won't enter here. We check in feed(). */
/* Identify sentence type */
const char *fmt = get_formatter(sentence);
if (fmt == NULL) return;
if (strncmp(fmt, "GGA", 3) == 0) {
gps->initialized = true;
parse_gga(gps, sentence);
} else if (strncmp(fmt, "RMC", 3) == 0) {
gps->initialized = true;
parse_rmc(gps, sentence);
} else if (strncmp(fmt, "THS", 3) == 0) {
gps->initialized = true;
parse_ths(gps, sentence);
} else if (strncmp(fmt, "VTG", 3) == 0) {
gps->initialized = true;
parse_vtg(gps, sentence);
}
/* Other sentences silently ignored */
}
/* ========================= Command interface ========================= */
bool um982_send_command(UM982_GPS_t *gps, const char *cmd)
{
if (gps == NULL || gps->huart == NULL || cmd == NULL) return false;
/* Build command with \r\n termination */
char buf[UM982_CMD_BUF_SIZE];
int len = snprintf(buf, sizeof(buf), "%s\r\n", cmd);
if (len <= 0 || (size_t)len >= sizeof(buf)) return false;
HAL_StatusTypeDef status = HAL_UART_Transmit(
gps->huart, (const uint8_t *)buf, (uint16_t)len, 100);
return status == HAL_OK;
}
/* ========================= Line assembly + feed ====================== */
/**
* Process a completed line from the line buffer.
*/
static void process_line(UM982_GPS_t *gps, const char *line)
{
if (line == NULL || line[0] == '\0') return;
/* NMEA sentence starts with '$' */
if (line[0] == '$') {
um982_parse_sentence(gps, line);
return;
}
/* Unicore proprietary response starts with '#' (e.g. #VERSIONA) */
if (line[0] == '#') {
if (strncmp(line + 1, "VERSIONA", 8) == 0) {
gps->version_received = true;
gps->initialized = true;
}
return;
}
}
void um982_feed(UM982_GPS_t *gps, const uint8_t *data, uint16_t len)
{
if (gps == NULL || data == NULL || len == 0) return;
for (uint16_t i = 0; i < len; i++) {
uint8_t ch = data[i];
/* End of line: process if we have content */
if (ch == '\n' || ch == '\r') {
if (gps->line_len > 0 && !gps->line_overflow) {
gps->line_buf[gps->line_len] = '\0';
process_line(gps, gps->line_buf);
}
gps->line_len = 0;
gps->line_overflow = false;
continue;
}
/* Accumulate into line buffer */
if (gps->line_len < UM982_LINE_BUF_SIZE - 1) {
gps->line_buf[gps->line_len++] = (char)ch;
} else {
gps->line_overflow = true;
}
}
}
/* ========================= UART process (production) ================= */
void um982_process(UM982_GPS_t *gps)
{
if (gps == NULL || gps->huart == NULL) return;
/* Read all available bytes from the UART one at a time.
* At 115200 baud (~11.5 KB/s) and a typical main-loop period of ~10 ms,
* we expect ~115 bytes per call — negligible overhead on a 168 MHz STM32.
*
* Note: batch reads (HAL_UART_Receive with Size > 1 and Timeout = 0) are
* NOT safe here because the HAL consumes bytes from the data register as
* it reads them. If fewer than Size bytes are available, the consumed
* bytes are lost (HAL_TIMEOUT is returned and the caller has no way to
* know how many bytes were actually placed into the buffer). */
uint8_t ch;
while (HAL_UART_Receive(gps->huart, &ch, 1, 0) == HAL_OK) {
um982_feed(gps, &ch, 1);
}
}
/* ========================= Validity checks =========================== */
bool um982_is_heading_valid(const UM982_GPS_t *gps)
{
if (gps == NULL) return false;
if (isnan(gps->heading)) return false;
/* Mode must be Autonomous or Differential */
if (gps->heading_mode != 'A' && gps->heading_mode != 'D') return false;
/* Check age */
uint32_t age = HAL_GetTick() - gps->last_ths_tick;
return age < UM982_HEADING_TIMEOUT_MS;
}
bool um982_is_position_valid(const UM982_GPS_t *gps)
{
if (gps == NULL) return false;
if (gps->fix_quality == UM982_FIX_NONE) return false;
/* Check age of the last valid fix */
uint32_t age = HAL_GetTick() - gps->last_fix_tick;
return age < UM982_POSITION_TIMEOUT_MS;
}
uint32_t um982_heading_age(const UM982_GPS_t *gps)
{
if (gps == NULL) return UINT32_MAX;
return HAL_GetTick() - gps->last_ths_tick;
}
uint32_t um982_position_age(const UM982_GPS_t *gps)
{
if (gps == NULL) return UINT32_MAX;
return HAL_GetTick() - gps->last_fix_tick;
}
/* ========================= Initialization ============================ */
bool um982_init(UM982_GPS_t *gps, UART_HandleTypeDef *huart,
float baseline_cm, float tolerance_cm)
{
if (gps == NULL || huart == NULL) return false;
/* Zero-init entire structure */
memset(gps, 0, sizeof(UM982_GPS_t));
gps->huart = huart;
gps->heading = NAN;
gps->heading_mode = 'V';
gps->rmc_status = 'V';
gps->speed_knots = 0.0f;
/* Seed fix timestamp so position_age() returns ~0 instead of uptime.
* Gives the module a full 30s grace window from init to acquire a fix
* before the health check fires ERROR_GPS_COMM. */
gps->last_fix_tick = HAL_GetTick();
gps->speed_kmh = 0.0f;
gps->course_true = 0.0f;
/* Step 1: Stop all current output to get a clean slate */
um982_send_command(gps, "UNLOG");
HAL_Delay(100);
/* Step 2: Configure heading mode
* Per N4 Reference 4.18: CONFIG HEADING FIXLENGTH (default mode)
* "The distance between ANT1 and ANT2 is fixed. They move synchronously." */
um982_send_command(gps, "CONFIG HEADING FIXLENGTH");
HAL_Delay(50);
/* Step 3: Set baseline length if specified
* Per N4 Reference: CONFIG HEADING LENGTH <cm> <tolerance_cm>
* "parameter1: Fixed baseline length (cm), valid range >= 0"
* "parameter2: Tolerable error margin (cm), valid range > 0" */
if (baseline_cm > 0.0f) {
char cmd[64];
if (tolerance_cm > 0.0f) {
snprintf(cmd, sizeof(cmd), "CONFIG HEADING LENGTH %.0f %.0f",
baseline_cm, tolerance_cm);
} else {
snprintf(cmd, sizeof(cmd), "CONFIG HEADING LENGTH %.0f",
baseline_cm);
}
um982_send_command(gps, cmd);
HAL_Delay(50);
}
/* Step 4: Enable NMEA output sentences on COM2.
* Per N4 Reference: "When requesting NMEA messages, users should add GP
* before each command name"
*
* We target COM2 because the ELT0213 board (GNSS.STORE) exposes COM2
* (RXD2/TXD2) on its 12-pin JST connector (pins 5 & 6). The STM32
* UART5 (PC12-TX, PD2-RX) connects to these pins via JP8.
* COM2 defaults to 115200 baud — matching our UART5 config. */
um982_send_command(gps, "GPGGA COM2 1"); /* GGA at 1 Hz */
HAL_Delay(50);
um982_send_command(gps, "GPRMC COM2 1"); /* RMC at 1 Hz */
HAL_Delay(50);
um982_send_command(gps, "GPTHS COM2 0.2"); /* THS at 5 Hz (heading primary) */
HAL_Delay(50);
/* Step 5: Skip SAVECONFIG -- NMEA config is re-sent every boot anyway.
* Saving to NVM on every power cycle would wear flash. If persistent
* config is needed, call um982_send_command(gps, "SAVECONFIG") once
* during commissioning. */
/* Step 6: Query version to verify communication */
gps->version_received = false;
um982_send_command(gps, "VERSIONA");
/* Wait for VERSIONA response (non-blocking poll) */
uint32_t start = HAL_GetTick();
while (!gps->version_received &&
(HAL_GetTick() - start) < UM982_INIT_TIMEOUT_MS) {
um982_process(gps);
HAL_Delay(10);
}
gps->initialized = gps->version_received;
return gps->initialized;
}
9_Firmware/9_1_Microcontroller/9_1_3_C_Cpp_Code/um982_gps.h
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@@ -1,213 +0,0 @@
/*******************************************************************************
* um982_gps.h -- UM982 dual-antenna GNSS receiver driver
*
* Parses NMEA sentences (GGA, RMC, THS, VTG) from the Unicore UM982 module
* and provides position, heading, and velocity data.
*
* Design principles:
* - Non-blocking: process() reads available UART bytes without waiting
* - Correct NMEA parsing: proper tokenizer handles empty fields
* - Longitude handles 3-digit degrees (dddmm.mmmm) via decimal-point detection
* - Checksum verified on every sentence
* - Command syntax verified against Unicore N4 Command Reference EN R1.14
*
* Hardware: UM982 on UART5 @ 115200 baud, dual-antenna heading mode
******************************************************************************/
#ifndef UM982_GPS_H
#define UM982_GPS_H
#include <stdint.h>
#include <stdbool.h>
#include <math.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Forward-declare the HAL UART handle type. The real definition comes from
* stm32f7xx_hal.h (production) or stm32_hal_mock.h (tests). */
#ifndef STM32_HAL_MOCK_H
#include "stm32f7xx_hal.h"
#else
/* Already included via mock -- nothing to do */
#endif
/* ========================= Constants ================================= */
#define UM982_RX_BUF_SIZE 512 /* Ring buffer for incoming UART bytes */
#define UM982_LINE_BUF_SIZE 96 /* Max NMEA sentence (82 chars + margin) */
#define UM982_CMD_BUF_SIZE 128 /* Outgoing command buffer */
#define UM982_INIT_TIMEOUT_MS 3000 /* Timeout waiting for VERSIONA response */
/* Fix quality values (from GGA field 6) */
#define UM982_FIX_NONE 0
#define UM982_FIX_GPS 1
#define UM982_FIX_DGPS 2
#define UM982_FIX_RTK_FIXED 4
#define UM982_FIX_RTK_FLOAT 5
/* Validity timeout defaults (ms) */
#define UM982_HEADING_TIMEOUT_MS 2000
#define UM982_POSITION_TIMEOUT_MS 5000
/* ========================= Data Types ================================ */
typedef struct {
/* Position */
double latitude; /* Decimal degrees, positive = North */
double longitude; /* Decimal degrees, positive = East */
float altitude; /* Meters above MSL */
float geoid_sep; /* Geoid separation (meters) */
/* Heading (from dual-antenna THS) */
float heading; /* True heading 0-360 degrees, NAN if invalid */
char heading_mode; /* A=autonomous, D=diff, E=est, M=manual, S=sim, V=invalid */
/* Velocity */
float speed_knots; /* Speed over ground (knots) */
float speed_kmh; /* Speed over ground (km/h) */
float course_true; /* Course over ground (degrees true) */
/* Quality */
uint8_t fix_quality; /* 0=none, 1=GPS, 2=DGPS, 4=RTK fixed, 5=RTK float */
uint8_t num_satellites; /* Satellites used in fix */
float hdop; /* Horizontal dilution of precision */
/* RMC status */
char rmc_status; /* A=valid, V=warning */
/* Timestamps (HAL_GetTick() at last update) */
uint32_t last_fix_tick; /* Last valid GGA fix (fix_quality > 0) */
uint32_t last_gga_tick;
uint32_t last_rmc_tick;
uint32_t last_ths_tick;
uint32_t last_vtg_tick;
/* Communication state */
bool initialized; /* VERSIONA or supported NMEA traffic seen */
bool version_received; /* VERSIONA response seen */
/* ---- Internal parser state (not for external use) ---- */
/* Ring buffer */
uint8_t rx_buf[UM982_RX_BUF_SIZE];
uint16_t rx_head; /* Write index */
uint16_t rx_tail; /* Read index */
/* Line assembler */
char line_buf[UM982_LINE_BUF_SIZE];
uint8_t line_len;
bool line_overflow; /* Current line exceeded buffer */
/* UART handle */
UART_HandleTypeDef *huart;
} UM982_GPS_t;
/* ========================= Public API ================================ */
/**
* Initialize the UM982_GPS_t structure and configure the module.
*
* Sends: UNLOG, CONFIG HEADING, optional CONFIG HEADING LENGTH,
* GPGGA, GPRMC, GPTHS
* Queries VERSIONA to verify communication.
*
* @param gps Pointer to UM982_GPS_t instance
* @param huart UART handle (e.g. &huart5)
* @param baseline_cm Distance between antennas in cm (0 = use module default)
* @param tolerance_cm Baseline tolerance in cm (0 = use module default)
* @return true if VERSIONA response received within timeout
*/
bool um982_init(UM982_GPS_t *gps, UART_HandleTypeDef *huart,
float baseline_cm, float tolerance_cm);
/**
* Process available UART data. Call from main loop — non-blocking.
*
* Reads all available bytes from UART, assembles lines, and dispatches
* complete NMEA sentences to the appropriate parser.
*
* @param gps Pointer to UM982_GPS_t instance
*/
void um982_process(UM982_GPS_t *gps);
/**
* Feed raw bytes directly into the parser (useful for testing).
* In production, um982_process() calls this internally after UART read.
*
* @param gps Pointer to UM982_GPS_t instance
* @param data Pointer to byte array
* @param len Number of bytes
*/
void um982_feed(UM982_GPS_t *gps, const uint8_t *data, uint16_t len);
/* ---- Getters ---- */
static inline float um982_get_heading(const UM982_GPS_t *gps) { return gps->heading; }
static inline double um982_get_latitude(const UM982_GPS_t *gps) { return gps->latitude; }
static inline double um982_get_longitude(const UM982_GPS_t *gps) { return gps->longitude; }
static inline float um982_get_altitude(const UM982_GPS_t *gps) { return gps->altitude; }
static inline uint8_t um982_get_fix_quality(const UM982_GPS_t *gps) { return gps->fix_quality; }
static inline uint8_t um982_get_num_sats(const UM982_GPS_t *gps) { return gps->num_satellites; }
static inline float um982_get_hdop(const UM982_GPS_t *gps) { return gps->hdop; }
static inline float um982_get_speed_knots(const UM982_GPS_t *gps) { return gps->speed_knots; }
static inline float um982_get_speed_kmh(const UM982_GPS_t *gps) { return gps->speed_kmh; }
static inline float um982_get_course(const UM982_GPS_t *gps) { return gps->course_true; }
/**
* Check if heading is valid (mode A or D, and within timeout).
*/
bool um982_is_heading_valid(const UM982_GPS_t *gps);
/**
* Check if position is valid (fix_quality > 0, and within timeout).
*/
bool um982_is_position_valid(const UM982_GPS_t *gps);
/**
* Get age of last heading update in milliseconds.
*/
uint32_t um982_heading_age(const UM982_GPS_t *gps);
/**
* Get age of the last valid position fix in milliseconds.
*/
uint32_t um982_position_age(const UM982_GPS_t *gps);
/* ========================= Internal (exposed for testing) ============ */
/**
* Verify NMEA checksum. Returns true if valid.
* Sentence must start with '$' and contain '*XX' before termination.
*/
bool um982_verify_checksum(const char *sentence);
/**
* Parse a complete NMEA line (with $ prefix and *XX checksum).
* Dispatches to GGA/RMC/THS/VTG parsers as appropriate.
*/
void um982_parse_sentence(UM982_GPS_t *gps, const char *sentence);
/**
* Parse NMEA coordinate string to decimal degrees.
* Works for both latitude (ddmm.mmmm) and longitude (dddmm.mmmm)
* by detecting the decimal point position.
*
* @param field NMEA coordinate field (e.g. "4404.14036" or "12118.85961")
* @param hemisphere 'N', 'S', 'E', or 'W'
* @return Decimal degrees (negative for S/W), or NAN on parse error
*/
double um982_parse_coord(const char *field, char hemisphere);
/**
* Send a command to the UM982. Appends \r\n automatically.
* @return true if UART transmit succeeded
*/
bool um982_send_command(UM982_GPS_t *gps, const char *cmd);
#ifdef __cplusplus
}
#endif
#endif /* UM982_GPS_H */
9_Firmware/9_1_Microcontroller/tests/.gitignore
+10 -24
View File
@@ -3,38 +3,24 @@
*.dSYM/
# Test binaries (built by Makefile)
# TESTS_WITH_REAL
test_bug1_timed_sync_init_ordering
test_bug2_ad9523_double_setup
test_bug3_timed_sync_noop
test_bug4_phase_shift_before_check
test_bug5_fine_phase_gpio_only
test_bug9_platform_ops_null
test_bug10_spi_cs_not_toggled
test_bug15_htim3_dangling_extern
# TESTS_MOCK_ONLY
test_bug2_ad9523_double_setup
test_bug6_timer_variable_collision
test_bug7_gpio_pin_conflict
test_bug8_uart_commented_out
test_bug14_diag_section_args
test_gap3_emergency_stop_rails
# TESTS_STANDALONE
test_bug9_platform_ops_null
test_bug10_spi_cs_not_toggled
test_bug11_platform_spi_transmit_only
test_bug12_pa_cal_loop_inverted
test_bug13_dac2_adc_buffer_mismatch
test_bug14_diag_section_args
test_bug15_htim3_dangling_extern
test_agc_outer_loop
test_gap3_emergency_state_ordering
test_gap3_emergency_stop_rails
test_gap3_idq_periodic_reread
test_gap3_iwdg_config
test_gap3_temperature_max
test_gap3_idq_periodic_reread
test_gap3_emergency_state_ordering
test_gap3_overtemp_emergency_stop
test_gap3_health_watchdog_cold_start
# TESTS_WITH_PLATFORM
test_bug11_platform_spi_transmit_only
# TESTS_WITH_CXX
test_agc_outer_loop
# Manual / one-off test builds
test_um982_gps
9_Firmware/9_1_Microcontroller/tests/Makefile
+3 -39
View File
@@ -27,10 +27,6 @@ CXX_LIB_DIR := ../9_1_1_C_Cpp_Libraries
CXX_SRCS := $(CXX_LIB_DIR)/ADAR1000_AGC.cpp $(CXX_LIB_DIR)/ADAR1000_Manager.cpp
CXX_OBJS := ADAR1000_AGC.o ADAR1000_Manager.o
# GPS driver source
GPS_SRC := ../9_1_3_C_Cpp_Code/um982_gps.c
GPS_OBJ := um982_gps.o
# Real source files compiled against mock headers
REAL_SRC := ../9_1_1_C_Cpp_Libraries/adf4382a_manager.c
@@ -68,9 +64,7 @@ TESTS_STANDALONE := test_bug12_pa_cal_loop_inverted \
test_gap3_iwdg_config \
test_gap3_temperature_max \
test_gap3_idq_periodic_reread \
test_gap3_emergency_state_ordering \
test_gap3_overtemp_emergency_stop \
test_gap3_health_watchdog_cold_start
test_gap3_emergency_state_ordering
# Tests that need platform_noos_stm32.o + mocks
TESTS_WITH_PLATFORM := test_bug11_platform_spi_transmit_only
@@ -78,15 +72,11 @@ TESTS_WITH_PLATFORM := test_bug11_platform_spi_transmit_only
# C++ tests (AGC outer loop)
TESTS_WITH_CXX := test_agc_outer_loop
# GPS driver tests (need mocks + GPS source + -lm)
TESTS_GPS := test_um982_gps
ALL_TESTS := $(TESTS_WITH_REAL) $(TESTS_MOCK_ONLY) $(TESTS_STANDALONE) $(TESTS_WITH_PLATFORM) $(TESTS_WITH_CXX) $(TESTS_GPS)
ALL_TESTS := $(TESTS_WITH_REAL) $(TESTS_MOCK_ONLY) $(TESTS_STANDALONE) $(TESTS_WITH_PLATFORM) $(TESTS_WITH_CXX)
.PHONY: all build test clean \
$(addprefix test_,bug1 bug2 bug3 bug4 bug5 bug6 bug7 bug8 bug9 bug10 bug11 bug12 bug13 bug14 bug15) \
test_gap3_estop test_gap3_iwdg test_gap3_temp test_gap3_idq test_gap3_order \
test_gap3_overtemp test_gap3_wdog
test_gap3_estop test_gap3_iwdg test_gap3_temp test_gap3_idq test_gap3_order
all: build test
@@ -172,12 +162,6 @@ test_gap3_idq_periodic_reread: test_gap3_idq_periodic_reread.c
test_gap3_emergency_state_ordering: test_gap3_emergency_state_ordering.c
$(CC) $(CFLAGS) $< -o $@
test_gap3_overtemp_emergency_stop: test_gap3_overtemp_emergency_stop.c
$(CC) $(CFLAGS) $< -o $@
test_gap3_health_watchdog_cold_start: test_gap3_health_watchdog_cold_start.c
$(CC) $(CFLAGS) $< -o $@
# Tests that need platform_noos_stm32.o + mocks
$(TESTS_WITH_PLATFORM): %: %.c $(MOCK_OBJS) $(PLATFORM_OBJ)
$(CC) $(CFLAGS) $(INCLUDES) $< $(MOCK_OBJS) $(PLATFORM_OBJ) -o $@
@@ -200,20 +184,6 @@ test_agc_outer_loop: test_agc_outer_loop.cpp $(CXX_OBJS) $(MOCK_OBJS)
test_agc: test_agc_outer_loop
./test_agc_outer_loop
# --- GPS driver rules ---
$(GPS_OBJ): $(GPS_SRC)
$(CC) $(CFLAGS) $(INCLUDES) -I../9_1_3_C_Cpp_Code -c $< -o $@
# Note: test includes um982_gps.c directly for white-box testing (static fn access)
test_um982_gps: test_um982_gps.c $(MOCK_OBJS)
$(CC) $(CFLAGS) $(INCLUDES) -I../9_1_3_C_Cpp_Code $< $(MOCK_OBJS) -lm -o $@
# Convenience target
.PHONY: test_gps
test_gps: test_um982_gps
./test_um982_gps
# --- Individual test targets ---
test_bug1: test_bug1_timed_sync_init_ordering
@@ -276,12 +246,6 @@ test_gap3_idq: test_gap3_idq_periodic_reread
test_gap3_order: test_gap3_emergency_state_ordering
./test_gap3_emergency_state_ordering
test_gap3_overtemp: test_gap3_overtemp_emergency_stop
./test_gap3_overtemp_emergency_stop
test_gap3_wdog: test_gap3_health_watchdog_cold_start
./test_gap3_health_watchdog_cold_start
# --- Clean ---
clean:
9_Firmware/9_1_Microcontroller/tests/stm32_hal_mock.c
-101
View File
@@ -21,7 +21,6 @@ SPI_HandleTypeDef hspi4 = { .id = 4 };
I2C_HandleTypeDef hi2c1 = { .id = 1 };
I2C_HandleTypeDef hi2c2 = { .id = 2 };
UART_HandleTypeDef huart3 = { .id = 3 };
UART_HandleTypeDef huart5 = { .id = 5 }; /* GPS UART */
ADC_HandleTypeDef hadc3 = { .id = 3 };
TIM_HandleTypeDef htim3 = { .id = 3 };
@@ -35,26 +34,6 @@ uint32_t mock_tick = 0;
/* ========================= Printf control ========================= */
int mock_printf_enabled = 0;
/* ========================= Mock UART TX capture =================== */
uint8_t mock_uart_tx_buf[MOCK_UART_TX_BUF_SIZE];
uint16_t mock_uart_tx_len = 0;
/* ========================= Mock UART RX buffer ==================== */
#define MOCK_UART_RX_SLOTS 8
static struct {
uint32_t uart_id;
uint8_t buf[MOCK_UART_RX_BUF_SIZE];
uint16_t head;
uint16_t tail;
} mock_uart_rx[MOCK_UART_RX_SLOTS];
void mock_uart_tx_clear(void)
{
mock_uart_tx_len = 0;
memset(mock_uart_tx_buf, 0, sizeof(mock_uart_tx_buf));
}
/* ========================= Mock GPIO read ========================= */
#define GPIO_READ_TABLE_SIZE 32
static struct {
@@ -70,9 +49,6 @@ void spy_reset(void)
mock_tick = 0;
mock_printf_enabled = 0;
memset(gpio_read_table, 0, sizeof(gpio_read_table));
memset(mock_uart_rx, 0, sizeof(mock_uart_rx));
mock_uart_tx_len = 0;
memset(mock_uart_tx_buf, 0, sizeof(mock_uart_tx_buf));
}
const SpyRecord *spy_get(int index)
@@ -209,83 +185,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD
.value = Timeout,
.extra = huart
});
/* Capture TX data for test inspection */
for (uint16_t i = 0; i < Size && mock_uart_tx_len < MOCK_UART_TX_BUF_SIZE; i++) {
mock_uart_tx_buf[mock_uart_tx_len++] = pData[i];
}
return HAL_OK;
}
/* ========================= Mock UART RX helpers ====================== */
/* find_rx_slot, mock_uart_rx_load, etc. use the mock_uart_rx declared above */
static int find_rx_slot(UART_HandleTypeDef *huart)
{
if (huart == NULL) return -1;
/* Find existing slot */
for (int i = 0; i < MOCK_UART_RX_SLOTS; i++) {
if (mock_uart_rx[i].uart_id == huart->id && mock_uart_rx[i].head != mock_uart_rx[i].tail) {
return i;
}
if (mock_uart_rx[i].uart_id == huart->id) {
return i;
}
}
/* Find empty slot */
for (int i = 0; i < MOCK_UART_RX_SLOTS; i++) {
if (mock_uart_rx[i].uart_id == 0) {
mock_uart_rx[i].uart_id = huart->id;
return i;
}
}
return -1;
}
void mock_uart_rx_load(UART_HandleTypeDef *huart, const uint8_t *data, uint16_t len)
{
int slot = find_rx_slot(huart);
if (slot < 0) return;
mock_uart_rx[slot].uart_id = huart->id;
for (uint16_t i = 0; i < len; i++) {
uint16_t next = (mock_uart_rx[slot].head + 1) % MOCK_UART_RX_BUF_SIZE;
if (next == mock_uart_rx[slot].tail) break; /* Buffer full */
mock_uart_rx[slot].buf[mock_uart_rx[slot].head] = data[i];
mock_uart_rx[slot].head = next;
}
}
void mock_uart_rx_clear(UART_HandleTypeDef *huart)
{
int slot = find_rx_slot(huart);
if (slot < 0) return;
mock_uart_rx[slot].head = 0;
mock_uart_rx[slot].tail = 0;
}
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData,
uint16_t Size, uint32_t Timeout)
{
(void)Timeout;
int slot = find_rx_slot(huart);
if (slot < 0) return HAL_TIMEOUT;
for (uint16_t i = 0; i < Size; i++) {
if (mock_uart_rx[slot].head == mock_uart_rx[slot].tail) {
return HAL_TIMEOUT; /* No more data */
}
pData[i] = mock_uart_rx[slot].buf[mock_uart_rx[slot].tail];
mock_uart_rx[slot].tail = (mock_uart_rx[slot].tail + 1) % MOCK_UART_RX_BUF_SIZE;
}
spy_push((SpyRecord){
.type = SPY_UART_RX,
.port = NULL,
.pin = Size,
.value = Timeout,
.extra = huart
});
return HAL_OK;
}
9_Firmware/9_1_Microcontroller/tests/stm32_hal_mock.h
-19
View File
@@ -105,7 +105,6 @@ typedef struct {
extern SPI_HandleTypeDef hspi1, hspi4;
extern I2C_HandleTypeDef hi2c1, hi2c2;
extern UART_HandleTypeDef huart3;
extern UART_HandleTypeDef huart5; /* GPS UART */
extern ADC_HandleTypeDef hadc3;
extern TIM_HandleTypeDef htim3; /* Timer for DELADJ PWM */
@@ -140,7 +139,6 @@ typedef enum {
SPY_TIM_SET_COMPARE,
SPY_SPI_TRANSMIT_RECEIVE,
SPY_SPI_TRANSMIT,
SPY_UART_RX,
} SpyCallType;
typedef struct {
@@ -189,23 +187,6 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
uint32_t HAL_GetTick(void);
void HAL_Delay(uint32_t Delay);
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
/* ========================= Mock UART RX buffer ======================= */
/* Inject bytes into the mock UART RX buffer for a specific UART handle.
* HAL_UART_Receive will return these bytes one at a time. */
#define MOCK_UART_RX_BUF_SIZE 2048
void mock_uart_rx_load(UART_HandleTypeDef *huart, const uint8_t *data, uint16_t len);
void mock_uart_rx_clear(UART_HandleTypeDef *huart);
/* Capture buffer for UART TX data (to verify commands sent to GPS module) */
#define MOCK_UART_TX_BUF_SIZE 2048
extern uint8_t mock_uart_tx_buf[MOCK_UART_TX_BUF_SIZE];
extern uint16_t mock_uart_tx_len;
void mock_uart_tx_clear(void);
/* ========================= SPI stubs ============================== */
9_Firmware/9_1_Microcontroller/tests/test_agc_outer_loop.cpp
+1 -9
View File
@@ -50,7 +50,7 @@ static void test_defaults()
assert(agc.min_gain == 0);
assert(agc.max_gain == 127);
assert(agc.holdoff_frames == 4);
assert(agc.enabled == false); // disabled by default — FPGA DIG_6 is source of truth
assert(agc.enabled == true);
assert(agc.holdoff_counter == 0);
assert(agc.last_saturated == false);
assert(agc.saturation_event_count == 0);
@@ -67,7 +67,6 @@ static void test_defaults()
static void test_saturation_reduces_gain()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
uint8_t initial = agc.agc_base_gain; // 30
agc.update(true); // saturation
@@ -83,7 +82,6 @@ static void test_saturation_reduces_gain()
static void test_holdoff_prevents_early_gain_up()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
agc.update(true); // saturate once -> gain = 26
uint8_t after_sat = agc.agc_base_gain;
@@ -103,7 +101,6 @@ static void test_holdoff_prevents_early_gain_up()
static void test_recovery_after_holdoff()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
agc.update(true); // saturate -> gain = 26
uint8_t after_sat = agc.agc_base_gain;
@@ -122,7 +119,6 @@ static void test_recovery_after_holdoff()
static void test_min_gain_clamp()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
agc.min_gain = 10;
agc.agc_base_gain = 12;
agc.gain_step_down = 4;
@@ -140,7 +136,6 @@ static void test_min_gain_clamp()
static void test_max_gain_clamp()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
agc.max_gain = 32;
agc.agc_base_gain = 31;
agc.gain_step_up = 2;
@@ -231,7 +226,6 @@ static void test_apply_gain_spi()
static void test_reset_preserves_config()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
agc.agc_base_gain = 42;
agc.gain_step_down = 8;
agc.cal_offset[3] = -5;
@@ -261,7 +255,6 @@ static void test_reset_preserves_config()
static void test_saturation_counter()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
for (int i = 0; i < 10; ++i) {
agc.update(true);
@@ -281,7 +274,6 @@ static void test_saturation_counter()
static void test_mixed_sequence()
{
ADAR1000_AGC agc;
agc.enabled = true; // default is OFF; enable for this test
agc.agc_base_gain = 30;
agc.gain_step_down = 4;
agc.gain_step_up = 1;
9_Firmware/9_1_Microcontroller/tests/test_gap3_emergency_state_ordering.c
+10 -35
View File
@@ -34,25 +34,22 @@ static void Mock_Emergency_Stop(void)
state_was_true_when_estop_called = system_emergency_state;
}
/* Error codes (subset matching main.cpp SystemError_t) */
/* Error codes (subset matching main.cpp) */
typedef enum {
ERROR_NONE = 0,
ERROR_RF_PA_OVERCURRENT = 9,
ERROR_RF_PA_BIAS = 10,
ERROR_STEPPER_MOTOR = 11,
ERROR_STEPPER_FAULT = 11,
ERROR_FPGA_COMM = 12,
ERROR_POWER_SUPPLY = 13,
ERROR_TEMPERATURE_HIGH = 14,
ERROR_MEMORY_ALLOC = 15,
ERROR_WATCHDOG_TIMEOUT = 16,
} SystemError_t;
/* Extracted critical-error handling logic (matches post-fix main.cpp predicate) */
/* Extracted critical-error handling logic (post-fix ordering) */
static void simulate_handleSystemError_critical(SystemError_t error)
{
if ((error >= ERROR_RF_PA_OVERCURRENT && error <= ERROR_POWER_SUPPLY) ||
error == ERROR_TEMPERATURE_HIGH ||
error == ERROR_WATCHDOG_TIMEOUT) {
/* Only critical errors (PA overcurrent through power supply) trigger e-stop */
if (error >= ERROR_RF_PA_OVERCURRENT && error <= ERROR_POWER_SUPPLY) {
/* FIX 5: set flag BEFORE calling Emergency_Stop */
system_emergency_state = true;
Mock_Emergency_Stop();
@@ -96,39 +93,17 @@ int main(void)
assert(state_was_true_when_estop_called == true);
printf("PASS\n");
/* Test 4: Overtemp → MUST trigger e-stop (was incorrectly non-critical before fix) */
printf(" Test 4: Overtemp triggers e-stop... ");
/* Test 4: Non-critical error → no e-stop, flag stays false */
printf(" Test 4: Non-critical error (no e-stop)... ");
system_emergency_state = false;
emergency_stop_called = false;
state_was_true_when_estop_called = false;
simulate_handleSystemError_critical(ERROR_TEMPERATURE_HIGH);
assert(emergency_stop_called == true);
assert(system_emergency_state == true);
assert(state_was_true_when_estop_called == true);
printf("PASS\n");
/* Test 5: Watchdog timeout → MUST trigger e-stop */
printf(" Test 5: Watchdog timeout triggers e-stop... ");
system_emergency_state = false;
emergency_stop_called = false;
state_was_true_when_estop_called = false;
simulate_handleSystemError_critical(ERROR_WATCHDOG_TIMEOUT);
assert(emergency_stop_called == true);
assert(system_emergency_state == true);
assert(state_was_true_when_estop_called == true);
printf("PASS\n");
/* Test 6: Non-critical error (memory alloc) → no e-stop */
printf(" Test 6: Non-critical error (no e-stop)... ");
system_emergency_state = false;
emergency_stop_called = false;
simulate_handleSystemError_critical(ERROR_MEMORY_ALLOC);
assert(emergency_stop_called == false);
assert(system_emergency_state == false);
printf("PASS\n");
/* Test 7: ERROR_NONE → no e-stop */
printf(" Test 7: ERROR_NONE (no action)... ");
/* Test 5: ERROR_NONE → no e-stop */
printf(" Test 5: ERROR_NONE (no action)... ");
system_emergency_state = false;
emergency_stop_called = false;
simulate_handleSystemError_critical(ERROR_NONE);
@@ -136,6 +111,6 @@ int main(void)
assert(system_emergency_state == false);
printf("PASS\n");
printf("\n=== Gap-3 Fix 5: ALL 7 TESTS PASSED ===\n\n");
printf("\n=== Gap-3 Fix 5: ALL TESTS PASSED ===\n\n");
return 0;
}
9_Firmware/9_1_Microcontroller/tests/test_gap3_health_watchdog_cold_start.c
-132
View File
@@ -1,132 +0,0 @@
/*******************************************************************************
* test_gap3_health_watchdog_cold_start.c
*
* Safety bug: checkSystemHealth()'s internal watchdog (step 9, pre-fix) had two
* linked defects that, once ERROR_WATCHDOG_TIMEOUT was escalated to
* Emergency_Stop() by the overtemp/watchdog PR, would false-latch the radar:
*
* (1) Cold-start false trip:
* static uint32_t last_health_check = 0;
* if (HAL_GetTick() - last_health_check > 60000) { ... }
* On the very first call, last_health_check == 0, so once the MCU has
* been up >60 s (which is typical after the ADAR1000 / AD9523 / ADF4382
* init sequence) the subtraction `now - 0` exceeds 60 000 ms and the
* watchdog trips spuriously.
*
* (2) Stale-timestamp after early returns:
* last_health_check = HAL_GetTick(); // at END of function
* Every earlier sub-check (IMU, BMP180, GPS, PA Idq, temperature) has an
* `if (fault) return current_error;` path that skips the update. After a
* cumulative 60 s of transient faults, the next clean call compares
* `now` against the long-stale `last_health_check` and trips.
*
* After fix: Watchdog logic moved to function ENTRY. A dedicated cold-start
* branch seeds the timestamp on the first call without checking.
* On every subsequent call, the elapsed delta is captured FIRST
* and last_health_check is updated BEFORE any sub-check runs, so
* early returns no longer leave a stale value.
*
* Test strategy:
* Extract the post-fix watchdog predicate into a standalone function that
* takes a simulated HAL_GetTick() value and returns whether the watchdog
* should trip. Walk through boot + fault sequences that would have tripped
* the pre-fix code and assert the post-fix code does NOT trip.
******************************************************************************/
#include <assert.h>
#include <stdint.h>
#include <stdio.h>
/* --- Post-fix watchdog state + predicate, extracted verbatim --- */
static uint32_t last_health_check = 0;
/* Returns 1 iff this call should raise ERROR_WATCHDOG_TIMEOUT.
Updates last_health_check BEFORE returning (matches post-fix behaviour). */
static int health_watchdog_step(uint32_t now_tick)
{
if (last_health_check == 0) {
last_health_check = now_tick; /* cold start: seed only, never trip */
return 0;
}
uint32_t elapsed = now_tick - last_health_check;
last_health_check = now_tick; /* update BEFORE any early return */
return (elapsed > 60000) ? 1 : 0;
}
/* Test helper: reset the static state between scenarios. */
static void reset_state(void) { last_health_check = 0; }
int main(void)
{
printf("=== Safety fix: checkSystemHealth() watchdog cold-start + stale-ts ===\n");
/* ---------- Scenario 1: cold-start after 60 s of init must NOT trip ---- */
printf(" Test 1: first call at t=75000 ms (post-init) does not trip... ");
reset_state();
assert(health_watchdog_step(75000) == 0);
printf("PASS\n");
/* ---------- Scenario 2: first call far beyond 60 s (PRE-FIX BUG) ------- */
printf(" Test 2: first call at t=600000 ms still does not trip... ");
reset_state();
assert(health_watchdog_step(600000) == 0);
printf("PASS\n");
/* ---------- Scenario 3: healthy main-loop pacing (10 ms period) -------- */
printf(" Test 3: 1000 calls at 10 ms intervals never trip... ");
reset_state();
(void)health_watchdog_step(1000); /* seed */
for (int i = 1; i <= 1000; i++) {
assert(health_watchdog_step(1000 + i * 10) == 0);
}
printf("PASS\n");
/* ---------- Scenario 4: stale-timestamp after a burst of early returns -
Pre-fix bug: many early returns skipped the timestamp update, so a
later clean call would compare `now` against a 60+ s old value. Post-fix,
every call (including ones that would have early-returned in the real
function) updates the timestamp at the top, so this scenario is modelled
by calling health_watchdog_step() on every iteration of the main loop. */
printf(" Test 4: 70 s of 100 ms-spaced calls after seed do not trip... ");
reset_state();
(void)health_watchdog_step(50000); /* seed mid-run */
for (int i = 1; i <= 700; i++) { /* 70 s @ 100 ms */
int tripped = health_watchdog_step(50000 + i * 100);
assert(tripped == 0);
}
printf("PASS\n");
/* ---------- Scenario 5: genuine stall MUST trip ------------------------ */
printf(" Test 5: real 60+ s gap between calls does trip... ");
reset_state();
(void)health_watchdog_step(10000); /* seed */
assert(health_watchdog_step(10000 + 60001) == 1);
printf("PASS\n");
/* ---------- Scenario 6: exactly 60 s gap is the boundary -- do NOT trip
Post-fix predicate uses strict >60000, matching the pre-fix comparator. */
printf(" Test 6: exactly 60000 ms gap does not trip (boundary)... ");
reset_state();
(void)health_watchdog_step(10000);
assert(health_watchdog_step(10000 + 60000) == 0);
printf("PASS\n");
/* ---------- Scenario 7: trip, then recover on next paced call ---------- */
printf(" Test 7: after a genuine stall+trip, next paced call does not re-trip... ");
reset_state();
(void)health_watchdog_step(5000); /* seed */
assert(health_watchdog_step(5000 + 70000) == 1); /* stall -> trip */
assert(health_watchdog_step(5000 + 70000 + 10) == 0); /* resume paced */
printf("PASS\n");
/* ---------- Scenario 8: HAL_GetTick() 32-bit wrap (~49.7 days) ---------
Because we subtract unsigned 32-bit values, wrap is handled correctly as
long as the true elapsed time is < 2^32 ms. */
printf(" Test 8: tick wrap from 0xFFFFFF00 -> 0x00000064 (200 ms span) does not trip... ");
reset_state();
(void)health_watchdog_step(0xFFFFFF00u);
assert(health_watchdog_step(0x00000064u) == 0); /* elapsed = 0x164 = 356 ms */
printf("PASS\n");
printf("\n=== Safety fix: ALL TESTS PASSED ===\n\n");
return 0;
}
9_Firmware/9_1_Microcontroller/tests/test_gap3_overtemp_emergency_stop.c
-119
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@@ -1,119 +0,0 @@
/*******************************************************************************
* test_gap3_overtemp_emergency_stop.c
*
* Safety bug: handleSystemError() did not escalate ERROR_TEMPERATURE_HIGH
* (or ERROR_WATCHDOG_TIMEOUT) to Emergency_Stop().
*
* Before fix: The critical-error gate was
* if (error >= ERROR_RF_PA_OVERCURRENT &&
* error <= ERROR_POWER_SUPPLY) { Emergency_Stop(); }
* So overtemp (code 14) and watchdog timeout (code 16) fell
* through to attemptErrorRecovery()'s default branch (log and
* continue), leaving the 10 W GaN PAs biased at >75 °C.
*
* After fix: The gate also matches ERROR_TEMPERATURE_HIGH and
* ERROR_WATCHDOG_TIMEOUT, so thermal and watchdog faults
* latch Emergency_Stop() exactly like PA overcurrent.
*
* Test strategy:
* Replicate the critical-error predicate and assert that every error
* enum value which threatens RF/power safety is accepted, and that the
* non-critical ones (comm, sensor, memory) are not.
******************************************************************************/
#include <assert.h>
#include <stdio.h>
/* Mirror of SystemError_t from main.cpp (keep in lockstep). */
typedef enum {
ERROR_NONE = 0,
ERROR_AD9523_CLOCK,
ERROR_ADF4382_TX_UNLOCK,
ERROR_ADF4382_RX_UNLOCK,
ERROR_ADAR1000_COMM,
ERROR_ADAR1000_TEMP,
ERROR_IMU_COMM,
ERROR_BMP180_COMM,
ERROR_GPS_COMM,
ERROR_RF_PA_OVERCURRENT,
ERROR_RF_PA_BIAS,
ERROR_STEPPER_MOTOR,
ERROR_FPGA_COMM,
ERROR_POWER_SUPPLY,
ERROR_TEMPERATURE_HIGH,
ERROR_MEMORY_ALLOC,
ERROR_WATCHDOG_TIMEOUT
} SystemError_t;
/* Extracted post-fix predicate: returns 1 when Emergency_Stop() must fire. */
static int triggers_emergency_stop(SystemError_t e)
{
return ((e >= ERROR_RF_PA_OVERCURRENT && e <= ERROR_POWER_SUPPLY) ||
e == ERROR_TEMPERATURE_HIGH ||
e == ERROR_WATCHDOG_TIMEOUT);
}
int main(void)
{
printf("=== Safety fix: overtemp / watchdog -> Emergency_Stop() ===\n");
/* --- Errors that MUST latch Emergency_Stop --- */
printf(" Test 1: ERROR_RF_PA_OVERCURRENT triggers... ");
assert(triggers_emergency_stop(ERROR_RF_PA_OVERCURRENT));
printf("PASS\n");
printf(" Test 2: ERROR_RF_PA_BIAS triggers... ");
assert(triggers_emergency_stop(ERROR_RF_PA_BIAS));
printf("PASS\n");
printf(" Test 3: ERROR_STEPPER_MOTOR triggers... ");
assert(triggers_emergency_stop(ERROR_STEPPER_MOTOR));
printf("PASS\n");
printf(" Test 4: ERROR_FPGA_COMM triggers... ");
assert(triggers_emergency_stop(ERROR_FPGA_COMM));
printf("PASS\n");
printf(" Test 5: ERROR_POWER_SUPPLY triggers... ");
assert(triggers_emergency_stop(ERROR_POWER_SUPPLY));
printf("PASS\n");
printf(" Test 6: ERROR_TEMPERATURE_HIGH triggers (regression)... ");
assert(triggers_emergency_stop(ERROR_TEMPERATURE_HIGH));
printf("PASS\n");
printf(" Test 7: ERROR_WATCHDOG_TIMEOUT triggers (regression)... ");
assert(triggers_emergency_stop(ERROR_WATCHDOG_TIMEOUT));
printf("PASS\n");
/* --- Errors that MUST NOT escalate (recoverable / informational) --- */
printf(" Test 8: ERROR_NONE does not trigger... ");
assert(!triggers_emergency_stop(ERROR_NONE));
printf("PASS\n");
printf(" Test 9: ERROR_AD9523_CLOCK does not trigger... ");
assert(!triggers_emergency_stop(ERROR_AD9523_CLOCK));
printf("PASS\n");
printf(" Test 10: ERROR_ADF4382_TX_UNLOCK does not trigger (recoverable)... ");
assert(!triggers_emergency_stop(ERROR_ADF4382_TX_UNLOCK));
printf("PASS\n");
printf(" Test 11: ERROR_ADAR1000_COMM does not trigger... ");
assert(!triggers_emergency_stop(ERROR_ADAR1000_COMM));
printf("PASS\n");
printf(" Test 12: ERROR_IMU_COMM does not trigger... ");
assert(!triggers_emergency_stop(ERROR_IMU_COMM));
printf("PASS\n");
printf(" Test 13: ERROR_GPS_COMM does not trigger... ");
assert(!triggers_emergency_stop(ERROR_GPS_COMM));
printf("PASS\n");
printf(" Test 14: ERROR_MEMORY_ALLOC does not trigger... ");
assert(!triggers_emergency_stop(ERROR_MEMORY_ALLOC));
printf("PASS\n");
printf("\n=== Safety fix: ALL TESTS PASSED ===\n\n");
return 0;
}
9_Firmware/9_1_Microcontroller/tests/test_um982_gps.c
-853
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@@ -1,853 +0,0 @@
/*******************************************************************************
* test_um982_gps.c -- Unit tests for UM982 GPS driver
*
* Tests NMEA parsing, checksum validation, coordinate parsing, init sequence,
* and validity tracking. Uses the mock HAL infrastructure for UART.
*
* Build: see Makefile target test_um982_gps
* Run: ./test_um982_gps
******************************************************************************/
#include "stm32_hal_mock.h"
#include "../9_1_3_C_Cpp_Code/um982_gps.h"
#include "../9_1_3_C_Cpp_Code/um982_gps.c" /* Include .c directly for white-box testing */
#include <stdio.h>
#include <string.h>
#include <assert.h>
#include <math.h>
/* ========================= Test helpers ============================== */
static int tests_passed = 0;
static int tests_failed = 0;
#define TEST(name) \
do { printf(" [TEST] %-55s ", name); } while(0)
#define PASS() \
do { printf("PASS\n"); tests_passed++; } while(0)
#define FAIL(msg) \
do { printf("FAIL: %s\n", msg); tests_failed++; } while(0)
#define ASSERT_TRUE(expr, msg) \
do { if (!(expr)) { FAIL(msg); return; } } while(0)
#define ASSERT_FALSE(expr, msg) \
do { if (expr) { FAIL(msg); return; } } while(0)
#define ASSERT_EQ_INT(a, b, msg) \
do { if ((a) != (b)) { \
char _buf[256]; \
snprintf(_buf, sizeof(_buf), "%s (got %d, expected %d)", msg, (int)(a), (int)(b)); \
FAIL(_buf); return; \
} } while(0)
#define ASSERT_NEAR(a, b, tol, msg) \
do { if (fabs((double)(a) - (double)(b)) > (tol)) { \
char _buf[256]; \
snprintf(_buf, sizeof(_buf), "%s (got %.8f, expected %.8f)", msg, (double)(a), (double)(b)); \
FAIL(_buf); return; \
} } while(0)
#define ASSERT_NAN(val, msg) \
do { if (!isnan(val)) { FAIL(msg); return; } } while(0)
static UM982_GPS_t gps;
static void reset_gps(void)
{
spy_reset();
memset(&gps, 0, sizeof(gps));
gps.huart = &huart5;
gps.heading = NAN;
gps.heading_mode = 'V';
gps.rmc_status = 'V';
}
/* ========================= Checksum tests ============================ */
static void test_checksum_valid(void)
{
TEST("checksum: valid GGA");
ASSERT_TRUE(um982_verify_checksum(
"$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47"),
"should be valid");
PASS();
}
static void test_checksum_valid_ths(void)
{
TEST("checksum: valid THS");
ASSERT_TRUE(um982_verify_checksum("$GNTHS,341.3344,A*1F"),
"should be valid");
PASS();
}
static void test_checksum_invalid(void)
{
TEST("checksum: invalid (wrong value)");
ASSERT_FALSE(um982_verify_checksum("$GNTHS,341.3344,A*FF"),
"should be invalid");
PASS();
}
static void test_checksum_missing_star(void)
{
TEST("checksum: missing * marker");
ASSERT_FALSE(um982_verify_checksum("$GNTHS,341.3344,A"),
"should be invalid");
PASS();
}
static void test_checksum_null(void)
{
TEST("checksum: NULL input");
ASSERT_FALSE(um982_verify_checksum(NULL), "should be false");
PASS();
}
static void test_checksum_no_dollar(void)
{
TEST("checksum: missing $ prefix");
ASSERT_FALSE(um982_verify_checksum("GNTHS,341.3344,A*1F"),
"should be invalid without $");
PASS();
}
/* ========================= Coordinate parsing tests ================== */
static void test_coord_latitude_north(void)
{
TEST("coord: latitude 4404.14036 N");
double lat = um982_parse_coord("4404.14036", 'N');
/* 44 + 04.14036/60 = 44.069006 */
ASSERT_NEAR(lat, 44.069006, 0.000001, "latitude");
PASS();
}
static void test_coord_latitude_south(void)
{
TEST("coord: latitude 3358.92500 S (negative)");
double lat = um982_parse_coord("3358.92500", 'S');
ASSERT_TRUE(lat < 0.0, "should be negative for S");
ASSERT_NEAR(lat, -(33.0 + 58.925/60.0), 0.000001, "latitude");
PASS();
}
static void test_coord_longitude_3digit(void)
{
TEST("coord: longitude 12118.85961 W (3-digit degrees)");
double lon = um982_parse_coord("12118.85961", 'W');
/* 121 + 18.85961/60 = 121.314327 */
ASSERT_TRUE(lon < 0.0, "should be negative for W");
ASSERT_NEAR(lon, -(121.0 + 18.85961/60.0), 0.000001, "longitude");
PASS();
}
static void test_coord_longitude_east(void)
{
TEST("coord: longitude 11614.19729 E");
double lon = um982_parse_coord("11614.19729", 'E');
ASSERT_TRUE(lon > 0.0, "should be positive for E");
ASSERT_NEAR(lon, 116.0 + 14.19729/60.0, 0.000001, "longitude");
PASS();
}
static void test_coord_empty(void)
{
TEST("coord: empty string returns NAN");
ASSERT_NAN(um982_parse_coord("", 'N'), "should be NAN");
PASS();
}
static void test_coord_null(void)
{
TEST("coord: NULL returns NAN");
ASSERT_NAN(um982_parse_coord(NULL, 'N'), "should be NAN");
PASS();
}
static void test_coord_no_dot(void)
{
TEST("coord: no decimal point returns NAN");
ASSERT_NAN(um982_parse_coord("440414036", 'N'), "should be NAN");
PASS();
}
/* ========================= GGA parsing tests ========================= */
static void test_parse_gga_full(void)
{
TEST("GGA: full sentence with all fields");
reset_gps();
mock_set_tick(1000);
um982_parse_sentence(&gps,
"$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47");
ASSERT_NEAR(gps.latitude, 44.069006, 0.0001, "latitude");
ASSERT_NEAR(gps.longitude, -(121.0 + 18.85961/60.0), 0.0001, "longitude");
ASSERT_EQ_INT(gps.fix_quality, 1, "fix quality");
ASSERT_EQ_INT(gps.num_satellites, 12, "num sats");
ASSERT_NEAR(gps.hdop, 0.98, 0.01, "hdop");
ASSERT_NEAR(gps.altitude, 1113.0, 0.1, "altitude");
ASSERT_NEAR(gps.geoid_sep, -21.3, 0.1, "geoid sep");
PASS();
}
static void test_parse_gga_rtk_fixed(void)
{
TEST("GGA: RTK fixed (quality=4)");
reset_gps();
um982_parse_sentence(&gps,
"$GNGGA,023634.00,4004.73871635,N,11614.19729418,E,4,28,0.7,61.0988,M,-8.4923,M,,*5D");
ASSERT_EQ_INT(gps.fix_quality, 4, "RTK fixed");
ASSERT_EQ_INT(gps.num_satellites, 28, "num sats");
ASSERT_NEAR(gps.latitude, 40.0 + 4.73871635/60.0, 0.0000001, "latitude");
ASSERT_NEAR(gps.longitude, 116.0 + 14.19729418/60.0, 0.0000001, "longitude");
PASS();
}
static void test_parse_gga_no_fix(void)
{
TEST("GGA: no fix (quality=0)");
reset_gps();
/* Compute checksum for this sentence */
um982_parse_sentence(&gps,
"$GNGGA,235959.00,,,,,0,00,99.99,,,,,,*79");
ASSERT_EQ_INT(gps.fix_quality, 0, "no fix");
PASS();
}
/* ========================= RMC parsing tests ========================= */
static void test_parse_rmc_valid(void)
{
TEST("RMC: valid position and speed");
reset_gps();
mock_set_tick(2000);
um982_parse_sentence(&gps,
"$GNRMC,001031.00,A,4404.13993,N,12118.86023,W,0.146,,100117,,,A*7B");
ASSERT_EQ_INT(gps.rmc_status, 'A', "status");
ASSERT_NEAR(gps.latitude, 44.0 + 4.13993/60.0, 0.0001, "latitude");
ASSERT_NEAR(gps.longitude, -(121.0 + 18.86023/60.0), 0.0001, "longitude");
ASSERT_NEAR(gps.speed_knots, 0.146, 0.001, "speed");
PASS();
}
static void test_parse_rmc_void(void)
{
TEST("RMC: void status (no valid fix)");
reset_gps();
gps.latitude = 12.34; /* Pre-set to check it doesn't get overwritten */
um982_parse_sentence(&gps,
"$GNRMC,235959.00,V,,,,,,,100117,,,N*64");
ASSERT_EQ_INT(gps.rmc_status, 'V', "void status");
ASSERT_NEAR(gps.latitude, 12.34, 0.001, "lat should not change on void");
PASS();
}
/* ========================= THS parsing tests ========================= */
static void test_parse_ths_autonomous(void)
{
TEST("THS: autonomous heading 341.3344");
reset_gps();
mock_set_tick(3000);
um982_parse_sentence(&gps, "$GNTHS,341.3344,A*1F");
ASSERT_NEAR(gps.heading, 341.3344, 0.001, "heading");
ASSERT_EQ_INT(gps.heading_mode, 'A', "mode");
PASS();
}
static void test_parse_ths_not_valid(void)
{
TEST("THS: not valid mode");
reset_gps();
um982_parse_sentence(&gps, "$GNTHS,,V*10");
ASSERT_NAN(gps.heading, "heading should be NAN when empty");
ASSERT_EQ_INT(gps.heading_mode, 'V', "mode V");
PASS();
}
static void test_parse_ths_zero(void)
{
TEST("THS: heading exactly 0.0000");
reset_gps();
um982_parse_sentence(&gps, "$GNTHS,0.0000,A*19");
ASSERT_NEAR(gps.heading, 0.0, 0.001, "heading zero");
ASSERT_EQ_INT(gps.heading_mode, 'A', "mode A");
PASS();
}
static void test_parse_ths_360_boundary(void)
{
TEST("THS: heading near 360");
reset_gps();
um982_parse_sentence(&gps, "$GNTHS,359.9999,D*13");
ASSERT_NEAR(gps.heading, 359.9999, 0.001, "heading near 360");
ASSERT_EQ_INT(gps.heading_mode, 'D', "mode D");
PASS();
}
/* ========================= VTG parsing tests ========================= */
static void test_parse_vtg(void)
{
TEST("VTG: course and speed");
reset_gps();
um982_parse_sentence(&gps,
"$GPVTG,220.86,T,,M,2.550,N,4.724,K,A*34");
ASSERT_NEAR(gps.course_true, 220.86, 0.01, "course");
ASSERT_NEAR(gps.speed_knots, 2.550, 0.001, "speed knots");
ASSERT_NEAR(gps.speed_kmh, 4.724, 0.001, "speed kmh");
PASS();
}
/* ========================= Talker ID tests =========================== */
static void test_talker_gp(void)
{
TEST("talker: GP prefix parses correctly");
reset_gps();
um982_parse_sentence(&gps, "$GPTHS,123.4567,A*07");
ASSERT_NEAR(gps.heading, 123.4567, 0.001, "heading with GP");
PASS();
}
static void test_talker_gl(void)
{
TEST("talker: GL prefix parses correctly");
reset_gps();
um982_parse_sentence(&gps, "$GLTHS,123.4567,A*1B");
ASSERT_NEAR(gps.heading, 123.4567, 0.001, "heading with GL");
PASS();
}
/* ========================= Feed / line assembly tests ================ */
static void test_feed_single_sentence(void)
{
TEST("feed: single complete sentence with CRLF");
reset_gps();
mock_set_tick(5000);
const char *data = "$GNTHS,341.3344,A*1F\r\n";
um982_feed(&gps, (const uint8_t *)data, (uint16_t)strlen(data));
ASSERT_NEAR(gps.heading, 341.3344, 0.001, "heading");
PASS();
}
static void test_feed_multiple_sentences(void)
{
TEST("feed: multiple sentences in one chunk");
reset_gps();
mock_set_tick(5000);
const char *data =
"$GNTHS,100.0000,A*18\r\n"
"$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47\r\n";
um982_feed(&gps, (const uint8_t *)data, (uint16_t)strlen(data));
ASSERT_NEAR(gps.heading, 100.0, 0.01, "heading from THS");
ASSERT_EQ_INT(gps.fix_quality, 1, "fix from GGA");
PASS();
}
static void test_feed_partial_then_complete(void)
{
TEST("feed: partial bytes then complete");
reset_gps();
mock_set_tick(5000);
const char *part1 = "$GNTHS,200.";
const char *part2 = "5000,A*1E\r\n";
um982_feed(&gps, (const uint8_t *)part1, (uint16_t)strlen(part1));
/* Heading should not be set yet */
ASSERT_NAN(gps.heading, "should be NAN before complete");
um982_feed(&gps, (const uint8_t *)part2, (uint16_t)strlen(part2));
ASSERT_NEAR(gps.heading, 200.5, 0.01, "heading after complete");
PASS();
}
static void test_feed_bad_checksum_rejected(void)
{
TEST("feed: bad checksum sentence is rejected");
reset_gps();
mock_set_tick(5000);
const char *data = "$GNTHS,999.0000,A*FF\r\n";
um982_feed(&gps, (const uint8_t *)data, (uint16_t)strlen(data));
ASSERT_NAN(gps.heading, "heading should remain NAN");
PASS();
}
static void test_feed_versiona_response(void)
{
TEST("feed: VERSIONA response sets flag");
reset_gps();
const char *data = "#VERSIONA,79,GPS,FINE,2326,378237000,15434,0,18,889;\"UM982\"\r\n";
um982_feed(&gps, (const uint8_t *)data, (uint16_t)strlen(data));
ASSERT_TRUE(gps.version_received, "version_received should be true");
ASSERT_TRUE(gps.initialized, "VERSIONA should mark communication alive");
PASS();
}
/* ========================= Validity / age tests ====================== */
static void test_heading_valid_within_timeout(void)
{
TEST("validity: heading valid within timeout");
reset_gps();
mock_set_tick(10000);
um982_parse_sentence(&gps, "$GNTHS,341.3344,A*1F");
/* Still at tick 10000 */
ASSERT_TRUE(um982_is_heading_valid(&gps), "should be valid");
PASS();
}
static void test_heading_invalid_after_timeout(void)
{
TEST("validity: heading invalid after 2s timeout");
reset_gps();
mock_set_tick(10000);
um982_parse_sentence(&gps, "$GNTHS,341.3344,A*1F");
/* Advance past timeout */
mock_set_tick(12500);
ASSERT_FALSE(um982_is_heading_valid(&gps), "should be invalid after 2.5s");
PASS();
}
static void test_heading_invalid_mode_v(void)
{
TEST("validity: heading invalid with mode V");
reset_gps();
mock_set_tick(10000);
um982_parse_sentence(&gps, "$GNTHS,,V*10");
ASSERT_FALSE(um982_is_heading_valid(&gps), "mode V is invalid");
PASS();
}
static void test_position_valid(void)
{
TEST("validity: position valid with fix quality 1");
reset_gps();
mock_set_tick(10000);
um982_parse_sentence(&gps,
"$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47");
ASSERT_TRUE(um982_is_position_valid(&gps), "should be valid");
PASS();
}
static void test_position_invalid_no_fix(void)
{
TEST("validity: position invalid with no fix");
reset_gps();
mock_set_tick(10000);
um982_parse_sentence(&gps,
"$GNGGA,235959.00,,,,,0,00,99.99,,,,,,*79");
ASSERT_FALSE(um982_is_position_valid(&gps), "no fix = invalid");
PASS();
}
static void test_position_age_uses_last_valid_fix(void)
{
TEST("age: position age uses last valid fix, not no-fix GGA");
reset_gps();
mock_set_tick(10000);
um982_parse_sentence(&gps,
"$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47");
mock_set_tick(12000);
um982_parse_sentence(&gps,
"$GNGGA,235959.00,,,,,0,00,99.99,,,,,,*79");
mock_set_tick(12500);
ASSERT_EQ_INT(um982_position_age(&gps), 2500, "age should still be from last valid fix");
ASSERT_FALSE(um982_is_position_valid(&gps), "latest no-fix GGA should invalidate position");
PASS();
}
static void test_heading_age(void)
{
TEST("age: heading age computed correctly");
reset_gps();
mock_set_tick(10000);
um982_parse_sentence(&gps, "$GNTHS,341.3344,A*1F");
mock_set_tick(10500);
uint32_t age = um982_heading_age(&gps);
ASSERT_EQ_INT(age, 500, "age should be 500ms");
PASS();
}
/* ========================= Send command tests ======================== */
static void test_send_command_appends_crlf(void)
{
TEST("send_command: appends \\r\\n");
reset_gps();
um982_send_command(&gps, "GPGGA COM2 1");
/* Check that TX buffer contains "GPGGA COM2 1\r\n" */
const char *expected = "GPGGA COM2 1\r\n";
ASSERT_TRUE(mock_uart_tx_len == strlen(expected), "TX length");
ASSERT_TRUE(memcmp(mock_uart_tx_buf, expected, strlen(expected)) == 0,
"TX content should be 'GPGGA COM2 1\\r\\n'");
PASS();
}
static void test_send_command_null_safety(void)
{
TEST("send_command: NULL gps returns false");
ASSERT_FALSE(um982_send_command(NULL, "RESET"), "should return false");
PASS();
}
/* ========================= Init sequence tests ======================= */
static void test_init_sends_correct_commands(void)
{
TEST("init: sends correct command sequence");
spy_reset();
mock_uart_tx_clear();
/* Pre-load VERSIONA response so init succeeds */
const char *ver_resp = "#VERSIONA,79,GPS,FINE,2326,378237000,15434,0,18,889;\"UM982\"\r\n";
mock_uart_rx_load(&huart5, (const uint8_t *)ver_resp, (uint16_t)strlen(ver_resp));
UM982_GPS_t init_gps;
bool ok = um982_init(&init_gps, &huart5, 50.0f, 3.0f);
ASSERT_TRUE(ok, "init should succeed");
ASSERT_TRUE(init_gps.initialized, "should be initialized");
/* Verify TX buffer contains expected commands */
const char *tx = (const char *)mock_uart_tx_buf;
ASSERT_TRUE(strstr(tx, "UNLOG\r\n") != NULL, "should send UNLOG");
ASSERT_TRUE(strstr(tx, "CONFIG HEADING FIXLENGTH\r\n") != NULL, "should send CONFIG HEADING");
ASSERT_TRUE(strstr(tx, "CONFIG HEADING LENGTH 50 3\r\n") != NULL, "should send LENGTH");
ASSERT_TRUE(strstr(tx, "GPGGA COM2 1\r\n") != NULL, "should enable GGA");
ASSERT_TRUE(strstr(tx, "GPRMC COM2 1\r\n") != NULL, "should enable RMC");
ASSERT_TRUE(strstr(tx, "GPTHS COM2 0.2\r\n") != NULL, "should enable THS at 5Hz");
ASSERT_TRUE(strstr(tx, "SAVECONFIG\r\n") == NULL, "should NOT save config (NVM wear)");
ASSERT_TRUE(strstr(tx, "VERSIONA\r\n") != NULL, "should query version");
/* Verify command order: UNLOG should come before GPGGA */
const char *unlog_pos = strstr(tx, "UNLOG\r\n");
const char *gpgga_pos = strstr(tx, "GPGGA COM2 1\r\n");
ASSERT_TRUE(unlog_pos < gpgga_pos, "UNLOG should precede GPGGA");
PASS();
}
static void test_init_no_baseline(void)
{
TEST("init: baseline=0 skips LENGTH command");
spy_reset();
mock_uart_tx_clear();
const char *ver_resp = "#VERSIONA,79,GPS,FINE,2326,378237000,15434,0,18,889;\"UM982\"\r\n";
mock_uart_rx_load(&huart5, (const uint8_t *)ver_resp, (uint16_t)strlen(ver_resp));
UM982_GPS_t init_gps;
um982_init(&init_gps, &huart5, 0.0f, 0.0f);
const char *tx = (const char *)mock_uart_tx_buf;
ASSERT_TRUE(strstr(tx, "CONFIG HEADING LENGTH") == NULL, "should NOT send LENGTH");
PASS();
}
static void test_init_fails_no_version(void)
{
TEST("init: fails if no VERSIONA response");
spy_reset();
mock_uart_tx_clear();
/* Don't load any RX data — init should timeout */
UM982_GPS_t init_gps;
bool ok = um982_init(&init_gps, &huart5, 50.0f, 3.0f);
ASSERT_FALSE(ok, "init should fail without version response");
ASSERT_FALSE(init_gps.initialized, "should not be initialized");
PASS();
}
static void test_nmea_traffic_sets_initialized_without_versiona(void)
{
TEST("init state: supported NMEA traffic sets initialized");
reset_gps();
ASSERT_FALSE(gps.initialized, "should start uninitialized");
um982_parse_sentence(&gps, "$GNTHS,341.3344,A*1F");
ASSERT_TRUE(gps.initialized, "supported NMEA should mark communication alive");
PASS();
}
/* ========================= Edge case tests =========================== */
static void test_empty_fields_handled(void)
{
TEST("edge: GGA with empty lat/lon fields");
reset_gps();
gps.latitude = 99.99;
gps.longitude = 99.99;
/* GGA with empty position fields (no fix) */
um982_parse_sentence(&gps,
"$GNGGA,235959.00,,,,,0,00,99.99,,,,,,*79");
ASSERT_EQ_INT(gps.fix_quality, 0, "no fix");
/* Latitude/longitude should not be updated (fields are empty) */
ASSERT_NEAR(gps.latitude, 99.99, 0.01, "lat unchanged");
ASSERT_NEAR(gps.longitude, 99.99, 0.01, "lon unchanged");
PASS();
}
static void test_sentence_too_short(void)
{
TEST("edge: sentence too short to have formatter");
reset_gps();
/* Should not crash */
um982_parse_sentence(&gps, "$GN");
um982_parse_sentence(&gps, "$");
um982_parse_sentence(&gps, "");
um982_parse_sentence(&gps, NULL);
PASS();
}
static void test_line_overflow(void)
{
TEST("edge: oversized line is dropped");
reset_gps();
/* Create a line longer than UM982_LINE_BUF_SIZE */
char big[200];
memset(big, 'X', sizeof(big));
big[0] = '$';
big[198] = '\n';
big[199] = '\0';
um982_feed(&gps, (const uint8_t *)big, 199);
/* Should not crash, heading should still be NAN */
ASSERT_NAN(gps.heading, "no valid data from overflow");
PASS();
}
static void test_process_via_mock_uart(void)
{
TEST("process: reads from mock UART RX buffer");
reset_gps();
mock_set_tick(5000);
/* Load data into mock UART RX */
const char *data = "$GNTHS,275.1234,D*18\r\n";
mock_uart_rx_load(&huart5, (const uint8_t *)data, (uint16_t)strlen(data));
/* Call process() which reads from UART */
um982_process(&gps);
ASSERT_NEAR(gps.heading, 275.1234, 0.001, "heading via process()");
ASSERT_EQ_INT(gps.heading_mode, 'D', "mode D");
PASS();
}
/* ========================= PR #68 bug regression tests =============== */
/* These tests specifically verify the bugs found in the reverted PR #68 */
static void test_regression_sentence_id_with_gn_prefix(void)
{
TEST("regression: GN-prefixed GGA is correctly identified");
reset_gps();
/* PR #68 bug: strncmp(sentence, "GGA", 3) compared "GNG" vs "GGA" — never matched.
* Our fix: skip 2-char talker ID, compare at sentence+3. */
um982_parse_sentence(&gps,
"$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47");
ASSERT_EQ_INT(gps.fix_quality, 1, "GGA should parse with GN prefix");
ASSERT_NEAR(gps.latitude, 44.069006, 0.001, "latitude should be parsed");
PASS();
}
static void test_regression_longitude_3digit_degrees(void)
{
TEST("regression: 3-digit longitude degrees parsed correctly");
reset_gps();
/* PR #68 bug: hardcoded 2-digit degrees for longitude.
* 12118.85961 should be 121° 18.85961' = 121.314327° */
um982_parse_sentence(&gps,
"$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47");
ASSERT_NEAR(gps.longitude, -(121.0 + 18.85961/60.0), 0.0001,
"longitude 121° should not be parsed as 12°");
ASSERT_TRUE(gps.longitude < -100.0, "longitude should be > 100 degrees");
PASS();
}
static void test_regression_hemisphere_no_ptr_corrupt(void)
{
TEST("regression: hemisphere parsing doesn't corrupt field pointer");
reset_gps();
/* PR #68 bug: GGA/RMC hemisphere cases manually advanced ptr,
* desynchronizing from field counter. Our parser uses proper tokenizer. */
um982_parse_sentence(&gps,
"$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47");
/* After lat/lon, remaining fields should be correct */
ASSERT_EQ_INT(gps.num_satellites, 12, "sats after hemisphere");
ASSERT_NEAR(gps.hdop, 0.98, 0.01, "hdop after hemisphere");
ASSERT_NEAR(gps.altitude, 1113.0, 0.1, "altitude after hemisphere");
PASS();
}
static void test_regression_rmc_also_parsed(void)
{
TEST("regression: RMC sentence is actually parsed (not dead code)");
reset_gps();
/* PR #68 bug: identifySentence never matched GGA/RMC, so position
* parsing was dead code. */
um982_parse_sentence(&gps,
"$GNRMC,001031.00,A,4404.13993,N,12118.86023,W,0.146,,100117,,,A*7B");
ASSERT_TRUE(gps.latitude > 44.0, "RMC lat should be parsed");
ASSERT_TRUE(gps.longitude < -121.0, "RMC lon should be parsed");
ASSERT_NEAR(gps.speed_knots, 0.146, 0.001, "RMC speed");
PASS();
}
/* ========================= Main ====================================== */
int main(void)
{
printf("=== UM982 GPS Driver Tests ===\n\n");
printf("--- Checksum ---\n");
test_checksum_valid();
test_checksum_valid_ths();
test_checksum_invalid();
test_checksum_missing_star();
test_checksum_null();
test_checksum_no_dollar();
printf("\n--- Coordinate Parsing ---\n");
test_coord_latitude_north();
test_coord_latitude_south();
test_coord_longitude_3digit();
test_coord_longitude_east();
test_coord_empty();
test_coord_null();
test_coord_no_dot();
printf("\n--- GGA Parsing ---\n");
test_parse_gga_full();
test_parse_gga_rtk_fixed();
test_parse_gga_no_fix();
printf("\n--- RMC Parsing ---\n");
test_parse_rmc_valid();
test_parse_rmc_void();
printf("\n--- THS Parsing ---\n");
test_parse_ths_autonomous();
test_parse_ths_not_valid();
test_parse_ths_zero();
test_parse_ths_360_boundary();
printf("\n--- VTG Parsing ---\n");
test_parse_vtg();
printf("\n--- Talker IDs ---\n");
test_talker_gp();
test_talker_gl();
printf("\n--- Feed / Line Assembly ---\n");
test_feed_single_sentence();
test_feed_multiple_sentences();
test_feed_partial_then_complete();
test_feed_bad_checksum_rejected();
test_feed_versiona_response();
printf("\n--- Validity / Age ---\n");
test_heading_valid_within_timeout();
test_heading_invalid_after_timeout();
test_heading_invalid_mode_v();
test_position_valid();
test_position_invalid_no_fix();
test_position_age_uses_last_valid_fix();
test_heading_age();
printf("\n--- Send Command ---\n");
test_send_command_appends_crlf();
test_send_command_null_safety();
printf("\n--- Init Sequence ---\n");
test_init_sends_correct_commands();
test_init_no_baseline();
test_init_fails_no_version();
test_nmea_traffic_sets_initialized_without_versiona();
printf("\n--- Edge Cases ---\n");
test_empty_fields_handled();
test_sentence_too_short();
test_line_overflow();
test_process_via_mock_uart();
printf("\n--- PR #68 Regression ---\n");
test_regression_sentence_id_with_gn_prefix();
test_regression_longitude_3digit_degrees();
test_regression_hemisphere_no_ptr_corrupt();
test_regression_rmc_also_parsed();
printf("\n===============================================\n");
printf(" Results: %d passed, %d failed (of %d total)\n",
tests_passed, tests_failed, tests_passed + tests_failed);
printf("===============================================\n");
return tests_failed > 0 ? 1 : 0;
}
9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v
+10 -50
View File
@@ -32,50 +32,11 @@ localparam COMB_WIDTH = 28;
// adjacent DSP48E1 tiles — zero fabric delay, guaranteed to meet 400+ MHz
// on 7-series regardless of speed grade.
//
// Active-high reset derived from reset_n (inverted and REGISTERED).
// Active-high reset derived from reset_n (inverted).
// CEP (clock enable for P register) gated by data_valid.
//
// ----------------------------------------------------------------------------
// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
// ----------------------------------------------------------------------------
// Previously this was a combinational wire (`wire reset_h = ~reset_n`). Vivado
// collapsed all per-module inversions across the DDC hierarchy into a SINGLE
// shared LUT1, whose output fanned out to 702 loads (DSP48E1 RSTP/RSTB/RSTC
// plus FDRE R pins of all comb-stage DSP48E1s inferred via use_dsp="yes").
// Route delay alone on that net was 2.019–2.268 ns — nearly one full 2.5 ns
// period. Timing failed by 626 ps on the 400 MHz domain.
//
// Fix: convert reset_h to a REGISTERED signal with (* max_fanout = 50 *).
// Vivado treats max_fanout on a REG (not a wire) as authoritative and
// replicates the register into N copies, each placed near its ≈50 loads.
// Invariants preserved:
// I1 (correctness): reset_h is still active-high, equals ~reset_n
// after one clk edge; CIC reset is a RECEIVER-side
// synchronizer anyway (driven by reset_n_400m which
// is already sync'd in the parent DDC), so adding
// one more clk cycle of latency is safe.
// I2 (glitch-free): Registered output => inherently glitch-free,
// feeding DSP48E1 RST pins (which are synchronous
// to CLK, so they capture on the same edge anyway).
// I3 (power-up safety): reset_h is NOT async-reset itself. On power-up,
// FDRE INIT=0 starts reset_h LOW. First clk edge
// samples ~reset_n which is LOW on power-up (the
// parent DDC holds reset_n_400m low until the 2-
// stage synchronizer releases), so reset_h goes
// HIGH on cycle 1 and all DSPs see reset during
// the following cycles. System is held in reset
// for enough cycles that any initial register
// state garbage is overwritten. ✅
// I4 (reset de-assertion):reset_h goes LOW one cycle AFTER reset_n_400m
// goes HIGH. Downstream DSPs come out of reset on
// the next clk edge after that. Total latency
// from system reset release to first valid sample:
// 2 (sync chain) + 1 (reset_h reg) + 1 (first
// DSP output) = 4 cycles at 400 MHz = 10 ns.
// Negligible vs system reset assertion duration.
// ----------------------------------------------------------------------------
(* max_fanout = 50 *) reg reset_h = 1'b1; // INIT=1'b1: registers start in reset state on power-up
always @(posedge clk) reset_h <= ~reset_n;
// ============================================================================
wire reset_h = ~reset_n; // active-high reset for DSP48E1 RSTP
// Sign-extended input for integrator_0 C port (48-bit)
wire [ACC_WIDTH-1:0] data_in_c = {{(ACC_WIDTH-18){data_in[17]}}, data_in};
@@ -738,11 +699,10 @@ initial begin
end
// Decimation control + monitoring (integrators are now DSP48E1 instances)
// Sync reset via reset_h (registered, max_fanout=50) — eliminates the shared
// LUT1 inverter that previously fanned out to all fabric FDRE R pins plus
// DSP48E1 RST pins (702 loads total). See "RESET FAN-OUT INVARIANT" at top.
// Sync reset: enables FDRE inference for better timing at 400 MHz.
// Reset is already synchronous to clk via reset synchronizer in parent module.
always @(posedge clk) begin
if (reset_h) begin
if (!reset_n) begin
integrator_sampled <= 0;
decimation_counter <= 0;
data_valid_delayed <= 0;
@@ -795,9 +755,9 @@ always @(posedge clk) begin
end
// Pipeline the valid signal for comb section
// Sync reset via reset_h — same replicated-register source as DSP48E1 RSTs.
// Sync reset: matches decimation control block reset style.
always @(posedge clk) begin
if (reset_h) begin
if (!reset_n) begin
data_valid_comb <= 0;
data_valid_comb_pipe <= 0;
data_valid_comb_0_out <= 0;
@@ -832,7 +792,7 @@ end
// - Each stage: comb[i] = comb[i-1] - comb_delay[i][last]
always @(posedge clk) begin
if (reset_h) begin
if (!reset_n) begin
for (i = 0; i < STAGES; i = i + 1) begin
comb[i] <= 0;
for (j = 0; j < COMB_DELAY; j = j + 1) begin
9_Firmware/9_2_FPGA/constraints/README.md
+7 -8
View File
@@ -32,8 +32,8 @@ the `USB_MODE` parameter in `radar_system_top.v`:
| USB_MODE | Interface | Bus Width | Speed | Board Target |
|----------|-----------|-----------|-------|--------------|
| 0 | FT601 (USB 3.0) | 32-bit | 100 MHz | 200T premium dev board |
| 1 (default) | FT2232H (USB 2.0) | 8-bit | 60 MHz | 50T production board |
| 0 (default) | FT601 (USB 3.0) | 32-bit | 100 MHz | 200T premium dev board |
| 1 | FT2232H (USB 2.0) | 8-bit | 60 MHz | 50T production board |
### How USB_MODE Works
@@ -72,8 +72,7 @@ The parameter is set via a **wrapper module** that overrides the default:
```
- **200T dev board**: `radar_system_top` is used directly as the top module.
`USB_MODE` defaults to `1` (FT2232H) since production is the primary target.
Override with `.USB_MODE(0)` for FT601 builds.
`USB_MODE` defaults to `0` (FT601). No wrapper needed.
### RTL Files by USB Interface
@@ -159,7 +158,7 @@ The build scripts automatically select the correct top module and constraints:
You do NOT need to set `USB_MODE` manually. The top module selection handles it:
- `radar_system_top_50t` forces `USB_MODE=1` internally
- `radar_system_top` defaults to `USB_MODE=1` (FT2232H, production default)
- `radar_system_top` defaults to `USB_MODE=0`
## How to Select Constraints in Vivado
@@ -191,9 +190,9 @@ read_xdc constraints/te0713_te0701_minimal.xdc
| Target | Top module | USB_MODE | USB Interface | Notes |
|--------|------------|----------|---------------|-------|
| 50T Production (FTG256) | `radar_system_top_50t` | 1 | FT2232H (8-bit) | Wrapper sets USB_MODE=1, ties off FT601 |
| 200T Dev (FBG484) | `radar_system_top` | 0 (override) | FT601 (32-bit) | Build script overrides default USB_MODE=1 |
| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | 0 (override) | FT601 (32-bit) | Minimal bring-up wrapper |
| Trenz TE0713/TE0701 | `radar_system_top_te0713_dev` | 0 (override) | FT601 (32-bit) | Alternate SoM wrapper |
| 200T Dev (FBG484) | `radar_system_top` | 0 (default) | FT601 (32-bit) | No wrapper needed |
| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | 0 (default) | FT601 (32-bit) | Minimal bring-up wrapper |
| Trenz TE0713/TE0701 | `radar_system_top_te0713_dev` | 0 (default) | FT601 (32-bit) | Alternate SoM wrapper |
## Trenz Split Status
9_Firmware/9_2_FPGA/constraints/xc7a50t_ftg256.xdc
+8 -47
View File
@@ -70,10 +70,9 @@ set_input_jitter [get_clocks clk_100m] 0.1
# NOTE: The physical DAC (U3, AD9708) receives its clock directly from the
# AD9523 via a separate net (DAC_CLOCK), NOT from the FPGA. The FPGA
# uses this clock input for internal DAC data timing only. The RTL port
# `dac_clk` is an RTL output that assigns clk_120m directly. It has no
# physical pin on the 50T board and is left unconnected here. The port
# CANNOT be removed from the RTL because the 200T board uses it with
# ODDR clock forwarding (pin H17, see xc7a200t_fbg484.xdc).
# `dac_clk` is an output that assigns clk_120m directly — it has no
# separate physical pin on this board and should be removed from the
# RTL or left unconnected.
# FIX: Moved from C13 (IO_L12N = N-type) to D13 (IO_L12P = P-type MRCC).
# Clock inputs must use the P-type pin of an MRCC pair (PLIO-9 DRC).
set_property PACKAGE_PIN D13 [get_ports {clk_120m_dac}]
@@ -225,7 +224,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {stm32_mixers_enable}]
# DIG_5 = H11, DIG_6 = G12, DIG_7 = H12 — FPGA→STM32 status outputs
# DIG_5: AGC saturation flag (PD13 on STM32)
# DIG_6: AGC enable flag (PD14) — mirrors FPGA host_agc_enable to STM32
# DIG_6: reserved (PD14)
# DIG_7: reserved (PD15)
set_property PACKAGE_PIN H11 [get_ports {gpio_dig5}]
set_property PACKAGE_PIN G12 [get_ports {gpio_dig6}]
@@ -333,44 +332,6 @@ set_property DRIVE 8 [get_ports {ft_data[*]}]
# ft_clkout constrained above in CLOCK CONSTRAINTS section (C4, 60 MHz)
# --------------------------------------------------------------------------
# FT2232H Source-Synchronous Timing Constraints
# --------------------------------------------------------------------------
# FT2232H 245 Synchronous FIFO mode timing (60 MHz, period = 16.667 ns):
#
# FPGA Read Path (FT2232H drives data, FPGA samples):
# - Data valid before CLKOUT rising edge: t_vr(max) = 7.0 ns
# - Data hold after CLKOUT rising edge: t_hr(min) = 0.0 ns
# - Input delay max = period - t_vr = 16.667 - 7.0 = 9.667 ns
# - Input delay min = t_hr = 0.0 ns
#
# FPGA Write Path (FPGA drives data, FT2232H samples):
# - Data setup before next CLKOUT rising: t_su = 5.0 ns
# - Data hold after CLKOUT rising: t_hd = 0.0 ns
# - Output delay max = period - t_su = 16.667 - 5.0 = 11.667 ns
# - Output delay min = t_hd = 0.0 ns
# --------------------------------------------------------------------------
# Input delays: FT2232H → FPGA (data bus and status signals)
set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_data[*]}]
set_input_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_data[*]}]
set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_rxf_n}]
set_input_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_rxf_n}]
set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_txe_n}]
set_input_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_txe_n}]
# Output delays: FPGA → FT2232H (control strobes and data bus when writing)
set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_data[*]}]
set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_data[*]}]
set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_rd_n}]
set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_rd_n}]
set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_wr_n}]
set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_wr_n}]
set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_oe_n}]
set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_oe_n}]
set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_siwu}]
set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_siwu}]
# ============================================================================
# STATUS / DEBUG OUTPUTS — NO PHYSICAL CONNECTIONS
# ============================================================================
@@ -457,10 +418,10 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
# 4. JTAG: FPGA_TCK (L7), FPGA_TDI (N7), FPGA_TDO (N8), FPGA_TMS (M7).
# Dedicated pins — no XDC constraints needed.
#
# 5. dac_clk port: Not connected on the 50T board (DAC clocked directly from
# AD9523). The RTL port exists for 200T board compatibility, where the FPGA
# forwards the DAC clock via ODDR to pin H17 with generated clock and
# timing constraints (see xc7a200t_fbg484.xdc). Do NOT remove from RTL.
# 5. dac_clk port: The RTL top module declares `dac_clk` as an output, but
# the physical board wires the DAC clock (AD9708 CLOCK pin) directly from
# the AD9523, not from the FPGA. This port should be removed from the RTL
# or left unconnected. It currently just assigns clk_120m_dac passthrough.
#
# ============================================================================
# END OF CONSTRAINTS
9_Firmware/9_2_FPGA/ddc_400m.v
+328 -346
View File
@@ -1,66 +1,106 @@
`timescale 1ns / 1ps
module ddc_400m_enhanced (
input wire clk_400m, // 400MHz clock from ADC DCO
input wire clk_100m, // 100MHz system clock
input wire reset_n,
input wire mixers_enable,
input wire [7:0] adc_data, // ADC data at 400MHz
`timescale 1ns / 1ps
module ddc_400m_enhanced (
input wire clk_400m, // 400MHz clock from ADC DCO
input wire clk_100m, // 100MHz system clock
input wire reset_n,
input wire mixers_enable,
input wire [7:0] adc_data, // ADC data at 400MHz
input wire adc_data_valid_i, // Valid at 400MHz
input wire adc_data_valid_q,
output wire signed [17:0] baseband_i,
output wire signed [17:0] baseband_q,
input wire adc_data_valid_q,
output wire signed [17:0] baseband_i,
output wire signed [17:0] baseband_q,
output wire baseband_valid_i,
output wire baseband_valid_q,
output wire [1:0] ddc_status,
// Enhanced interfaces
output wire [7:0] ddc_diagnostics,
output wire baseband_valid_q,
output wire [1:0] ddc_status,
// Enhanced interfaces
output wire [7:0] ddc_diagnostics,
output wire mixer_saturation,
output wire filter_overflow,
input wire [1:0] test_mode,
input wire [15:0] test_phase_inc,
input wire force_saturation,
input wire reset_monitors,
output wire [31:0] debug_sample_count,
output wire [17:0] debug_internal_i,
output wire [17:0] debug_internal_q
);
// Parameters for numerical precision
parameter ADC_WIDTH = 8;
parameter NCO_WIDTH = 16;
parameter MIXER_WIDTH = 18;
parameter OUTPUT_WIDTH = 18;
// IF frequency parameters
parameter IF_FREQ = 120000000;
parameter FS = 400000000;
parameter PHASE_WIDTH = 32;
// Internal signals
wire signed [15:0] sin_out, cos_out;
wire nco_ready;
wire cic_valid;
wire fir_valid;
wire [17:0] cic_i_out, cic_q_out;
wire signed [17:0] fir_i_out, fir_q_out;
input wire [1:0] test_mode,
input wire [15:0] test_phase_inc,
input wire force_saturation,
input wire reset_monitors,
output wire [31:0] debug_sample_count,
output wire [17:0] debug_internal_i,
output wire [17:0] debug_internal_q
);
// Parameters for numerical precision
parameter ADC_WIDTH = 8;
parameter NCO_WIDTH = 16;
parameter MIXER_WIDTH = 18;
parameter OUTPUT_WIDTH = 18;
// IF frequency parameters
parameter IF_FREQ = 120000000;
parameter FS = 400000000;
parameter PHASE_WIDTH = 32;
// Internal signals
wire signed [15:0] sin_out, cos_out;
wire nco_ready;
wire cic_valid;
wire fir_valid;
wire [17:0] cic_i_out, cic_q_out;
wire signed [17:0] fir_i_out, fir_q_out;
// Diagnostic registers
reg [2:0] saturation_count;
reg overflow_detected;
reg [7:0] error_counter;
// ============================================================================
// 400 MHz Reset Synchronizer
//
// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
// Using it directly as an async reset in the 400 MHz domain causes the reset
// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
// domain, requiring 18.243ns of routing (WNS = -18.081ns).
//
// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
// path from reset_n to all 400 MHz registers). Reset deassertion is
// synchronized to clk_400m rising edge, preventing metastability.
//
// All 400 MHz submodules (NCO, CIC, mixers, LFSR) use reset_n_400m.
// All 100 MHz submodules (FIR, output stage) continue using reset_n directly
// (already synchronized to 100 MHz at radar_system_top level).
// ============================================================================
(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m;
(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
// Active-high reset for DSP48E1 RST ports (avoids LUT1 inverter fan-out)
(* max_fanout = 50 *) reg reset_400m;
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
reset_sync_400m <= 2'b00;
reset_400m <= 1'b1;
end else begin
reset_sync_400m <= {reset_sync_400m[0], 1'b1};
reset_400m <= ~reset_sync_400m[1];
end
end
// CDC synchronization for control signals (2-stage synchronizers)
(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
wire mixers_enable_sync;
wire force_saturation_sync;
// Debug monitoring signals
reg [31:0] sample_counter;
wire signed [17:0] debug_mixed_i_trunc;
wire signed [17:0] debug_mixed_q_trunc;
// Real-time status monitoring
reg [7:0] signal_power_i, signal_power_q;
reg [7:0] signal_power_i, signal_power_q;
// Internal mixing signals
// Pipeline: NCO fabric reg (1) + DSP48E1 AREG/BREG (1) + MREG (1) + PREG (1) + retiming (1) = 5 cycles
// The NCO fabric pipeline register was added to break the long NCO→DSP B-port route
@@ -78,112 +118,61 @@ reg [4:0] dsp_valid_pipe;
// Post-DSP retiming registers — breaks DSP48E1 CLK→P to fabric timing path
// This extra pipeline stage absorbs the 1.866ns DSP output prop delay + routing,
// ensuring WNS > 0 at 400 MHz regardless of placement seed
(* DONT_TOUCH = "TRUE" *) reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_retimed, mult_q_retimed;
// Output stage registers
reg signed [17:0] baseband_i_reg, baseband_q_reg;
reg baseband_valid_reg;
// ============================================================================
(* DONT_TOUCH = "TRUE" *) reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_retimed, mult_q_retimed;
// Output stage registers
reg signed [17:0] baseband_i_reg, baseband_q_reg;
reg baseband_valid_reg;
// ============================================================================
// Phase Dithering Signals
// ============================================================================
wire [7:0] phase_dither_bits;
reg [31:0] phase_inc_dithered;
reg [31:0] phase_inc_dithered;
// ============================================================================
// Debug Signal Assignments
// ============================================================================
assign debug_internal_i = mixed_i[25:8];
assign debug_internal_q = mixed_q[25:8];
assign debug_sample_count = sample_counter;
assign debug_mixed_i_trunc = mixed_i[25:8];
assign debug_mixed_q_trunc = mixed_q[25:8];
// ============================================================================
// Clock Domain Crossing for Control Signals (2-stage synchronizers)
// ============================================================================
// Debug Signal Assignments
// ============================================================================
assign debug_internal_i = mixed_i[25:8];
assign debug_internal_q = mixed_q[25:8];
assign debug_sample_count = sample_counter;
assign debug_mixed_i_trunc = mixed_i[25:8];
assign debug_mixed_q_trunc = mixed_q[25:8];
// ============================================================================
// 400 MHz Reset Synchronizer
//
// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
// Using it directly as an async reset in the 400 MHz domain causes the reset
// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
// domain, requiring 18.243ns of routing (WNS = -18.081ns).
//
// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
// path from reset_n to all 400 MHz registers). Reset deassertion is
//
// reset_400m : ACTIVE-HIGH registered reset with (* max_fanout = 50 *).
// This is THE signal fed to every synchronous 400 MHz FDRE
// and every DSP48E1 RST pin in this module and its children
// (NCO, CIC, LFSR). Vivado replicates the register (~14
// copies) so each replica drives ≈50 loads regionally,
// eliminating the single-LUT1 / 702-load net that caused
// WNS=-0.626 ns in Build N.
//
// System-level invariants preserved:
// I1 Reset assertion propagates to all 400 MHz regs within ≤3 clk edges
// (2 sync + 1 replicated-reg fanout). At 400 MHz = 7.5 ns << any
// system-level reset assertion duration.
// I2 Reset de-assertion is always synchronous to clk_400m (via
// reset_sync_400m), never glitches.
// I3 DSP48E1 RST pins are all fed from Q of a register — glitch-free.
// I4 No new CDC introduced: reset_400m is entirely in clk_400m domain.
// I5 Power-up: reset_n is asserted externally and mmcm_locked is low;
// reset_sync_400m stays 2'b00, reset_400m stays 1'b1, downstream
// FDREs stay cleared. Safe.
// ============================================================================
(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m = 2'b00;
(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
// Active-high replicated reset for all synchronous 400 MHz consumers
(* max_fanout = 50 *) reg reset_400m = 1'b1;
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
reset_sync_400m <= 2'b00;
reset_400m <= 1'b1;
end else begin
reset_sync_400m <= {reset_sync_400m[0], 1'b1};
reset_400m <= ~reset_sync_400m[1];
end
end
// CDC synchronization for control signals (2-stage synchronizers)
(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
wire mixers_enable_sync;
wire force_saturation_sync;
assign mixers_enable_sync = mixers_enable_sync_chain[1];
assign force_saturation_sync = force_saturation_sync_chain[1];
// Sync reset via reset_400m (replicated, max_fanout=50). Was async on
// reset_n_400m — see "400 MHz RESET DISTRIBUTION" comment above.
always @(posedge clk_400m) begin
if (reset_400m) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
mixers_enable_sync_chain <= 2'b00;
force_saturation_sync_chain <= 2'b00;
end else begin
mixers_enable_sync_chain <= {mixers_enable_sync_chain[0], mixers_enable};
force_saturation_sync_chain <= {force_saturation_sync_chain[0], force_saturation};
end
end
// ============================================================================
// Sample Counter and Debug Monitoring
// ============================================================================
always @(posedge clk_400m) begin
if (reset_400m || reset_monitors) begin
end
// ============================================================================
// Sample Counter and Debug Monitoring
// ============================================================================
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m || reset_monitors) begin
sample_counter <= 0;
error_counter <= 0;
end else if (adc_data_valid_i && adc_data_valid_q ) begin
sample_counter <= sample_counter + 1;
end
end
// ============================================================================
// Enhanced Phase Dithering Instance
// ============================================================================
error_counter <= 0;
end else if (adc_data_valid_i && adc_data_valid_q ) begin
sample_counter <= sample_counter + 1;
end
end
// ============================================================================
// Enhanced Phase Dithering Instance
// ============================================================================
lfsr_dither_enhanced #(
.DITHER_WIDTH(8)
) phase_dither_gen (
@@ -191,36 +180,36 @@ lfsr_dither_enhanced #(
.reset_n(reset_n_400m),
.enable(nco_ready),
.dither_out(phase_dither_bits)
);
// ============================================================================
// Phase Increment Calculation with Dithering
// ============================================================================
// Calculate phase increment for 120MHz IF at 400MHz sampling
localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
);
// ============================================================================
// Phase Increment Calculation with Dithering
// ============================================================================
// Calculate phase increment for 120MHz IF at 400MHz sampling
localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
// Apply dithering to reduce spurious tones (registered for 400 MHz timing)
always @(posedge clk_400m) begin
if (reset_400m)
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m)
phase_inc_dithered <= PHASE_INC_120MHZ;
else
phase_inc_dithered <= PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
end
// ============================================================================
// Enhanced NCO with Diagnostics
// ============================================================================
end
// ============================================================================
// Enhanced NCO with Diagnostics
// ============================================================================
nco_400m_enhanced nco_core (
.clk_400m(clk_400m),
.reset_n(reset_n_400m),
.frequency_tuning_word(phase_inc_dithered),
.phase_valid(mixers_enable),
.phase_offset(16'h0000),
.sin_out(sin_out),
.cos_out(cos_out),
.dds_ready(nco_ready)
);
.reset_n(reset_n_400m),
.frequency_tuning_word(phase_inc_dithered),
.phase_valid(mixers_enable),
.phase_offset(16'h0000),
.sin_out(sin_out),
.cos_out(cos_out),
.dds_ready(nco_ready)
);
// ============================================================================
// Enhanced Mixing Stage — DSP48E1 direct instantiation for 400 MHz timing
//
@@ -240,8 +229,8 @@ assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
{1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
// Valid pipeline: 5-stage shift register (1 NCO pipe + 3 DSP48E1 AREG+MREG+PREG + 1 retiming)
always @(posedge clk_400m) begin
if (reset_400m) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
dsp_valid_pipe <= 5'b00000;
end else begin
dsp_valid_pipe <= {dsp_valid_pipe[3:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
@@ -257,8 +246,8 @@ reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal; // Mod
reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg; // Models PREG
// Stage 0: NCO pipeline — breaks long NCO→DSP route (matches synthesis fabric registers)
always @(posedge clk_400m) begin
if (reset_400m) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
cos_nco_pipe <= 0;
sin_nco_pipe <= 0;
end else begin
@@ -268,8 +257,8 @@ always @(posedge clk_400m) begin
end
// Stage 1: AREG/BREG equivalent (uses pipelined NCO outputs)
always @(posedge clk_400m) begin
if (reset_400m) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
adc_signed_reg <= 0;
cos_pipe_reg <= 0;
sin_pipe_reg <= 0;
@@ -281,8 +270,8 @@ always @(posedge clk_400m) begin
end
// Stage 2: MREG equivalent
always @(posedge clk_400m) begin
if (reset_400m) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
mult_i_internal <= 0;
mult_q_internal <= 0;
end else begin
@@ -292,8 +281,8 @@ always @(posedge clk_400m) begin
end
// Stage 3: PREG equivalent
always @(posedge clk_400m) begin
if (reset_400m) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
mult_i_reg <= 0;
mult_q_reg <= 0;
end else begin
@@ -303,8 +292,8 @@ always @(posedge clk_400m) begin
end
// Stage 4: Post-DSP retiming register (matches synthesis path)
always @(posedge clk_400m) begin
if (reset_400m) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
mult_i_retimed <= 0;
mult_q_retimed <= 0;
end else begin
@@ -322,8 +311,8 @@ wire [47:0] dsp_p_i, dsp_p_q;
// (1.505ns routing observed in Build 26). These fabric registers are placed
// near the DSP by the placer, splitting the route into two shorter segments.
// DONT_TOUCH on the reg declaration (above) prevents absorption/retiming.
always @(posedge clk_400m) begin
if (reset_400m) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
cos_nco_pipe <= 0;
sin_nco_pipe <= 0;
end else begin
@@ -340,10 +329,11 @@ DSP48E1 #(
.USE_DPORT("FALSE"),
.USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48"),
// Pipeline register attributes — all enabled for max timing
.AREG(1),
.BREG(1),
.MREG(1),
.PREG(1),
.PREG(1), // P register enabled — absorbs CLK→P delay for timing closure
.ADREG(0),
.ACASCREG(1),
.BCASCREG(1),
@@ -354,6 +344,7 @@ DSP48E1 #(
.DREG(0),
.INMODEREG(0),
.OPMODEREG(0),
// Pattern detector (unused)
.AUTORESET_PATDET("NO_RESET"),
.MASK(48'h3fffffffffff),
.PATTERN(48'h000000000000),
@@ -505,8 +496,8 @@ wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_q_reg = dsp_p_q[MIXER_WIDTH+NCO_WID
// Stage 4: Post-DSP retiming register — breaks DSP48E1 CLK→P to fabric path
// Without this, the DSP output prop delay (1.866ns) + routing (0.515ns) exceeds
// the 2.500ns clock period at slow process corner
always @(posedge clk_400m) begin
if (reset_400m) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
mult_i_retimed <= 0;
mult_q_retimed <= 0;
end else begin
@@ -522,8 +513,8 @@ end
// force_saturation mux is intentionally AFTER the DSP48E1 output to avoid
// polluting the critical input path with extra logic
// ============================================================================
always @(posedge clk_400m) begin
if (reset_400m) begin
always @(posedge clk_400m or negedge reset_n_400m) begin
if (!reset_n_400m) begin
mixed_i <= 0;
mixed_q <= 0;
mixed_valid <= 0;
@@ -565,31 +556,31 @@ always @(posedge clk_400m) begin
mixer_overflow_q <= 0;
overflow_detected <= 1'b0;
end
end
// ============================================================================
// Enhanced CIC Decimators
// ============================================================================
wire cic_valid_i, cic_valid_q;
end
// ============================================================================
// Enhanced CIC Decimators
// ============================================================================
wire cic_valid_i, cic_valid_q;
cic_decimator_4x_enhanced cic_i_inst (
.clk(clk_400m),
.reset_n(reset_n_400m),
.data_in(mixed_i[33:16]),
.data_valid(mixed_valid),
.data_out(cic_i_out),
.data_out_valid(cic_valid_i)
);
.reset_n(reset_n_400m),
.data_in(mixed_i[33:16]),
.data_valid(mixed_valid),
.data_out(cic_i_out),
.data_out_valid(cic_valid_i)
);
cic_decimator_4x_enhanced cic_q_inst (
.clk(clk_400m),
.reset_n(reset_n_400m),
.data_in(mixed_q[33:16]),
.data_valid(mixed_valid),
.data_out(cic_q_out),
.data_out_valid(cic_valid_q)
);
.reset_n(reset_n_400m),
.data_in(mixed_q[33:16]),
.data_valid(mixed_valid),
.data_out(cic_q_out),
.data_out_valid(cic_valid_q)
);
assign cic_valid = cic_valid_i & cic_valid_q;
// ============================================================================
@@ -602,96 +593,96 @@ wire fir_valid_i, fir_valid_q;
wire fir_i_ready, fir_q_ready;
wire [17:0] fir_d_in_i, fir_d_in_q;
cdc_adc_to_processing #(
.WIDTH(18),
.STAGES(3)
cdc_adc_to_processing #(
.WIDTH(18),
.STAGES(3)
)CDC_FIR_i(
.src_clk(clk_400m),
.dst_clk(clk_100m),
.src_reset_n(reset_n_400m),
.dst_reset_n(reset_n),
.src_data(cic_i_out),
.src_valid(cic_valid_i),
.dst_data(fir_d_in_i),
.dst_valid(fir_in_valid_i)
.dst_reset_n(reset_n),
.src_data(cic_i_out),
.src_valid(cic_valid_i),
.dst_data(fir_d_in_i),
.dst_valid(fir_in_valid_i)
);
cdc_adc_to_processing #(
.WIDTH(18),
.STAGES(3)
cdc_adc_to_processing #(
.WIDTH(18),
.STAGES(3)
)CDC_FIR_q(
.src_clk(clk_400m),
.dst_clk(clk_100m),
.src_reset_n(reset_n_400m),
.dst_reset_n(reset_n),
.src_data(cic_q_out),
.src_valid(cic_valid_q),
.dst_data(fir_d_in_q),
.dst_valid(fir_in_valid_q)
);
.dst_reset_n(reset_n),
.src_data(cic_q_out),
.src_valid(cic_valid_q),
.dst_data(fir_d_in_q),
.dst_valid(fir_in_valid_q)
);
// ============================================================================
// FIR Filter Instances
// ============================================================================
// FIR I channel
fir_lowpass_parallel_enhanced fir_i_inst (
.clk(clk_100m),
.reset_n(reset_n),
.data_in(fir_d_in_i), // Use synchronized data
.data_valid(fir_in_valid_i), // Use synchronized valid
.data_out(fir_i_out),
.data_out_valid(fir_valid_i),
.fir_ready(fir_i_ready),
.filter_overflow()
);
// FIR Q channel
fir_lowpass_parallel_enhanced fir_q_inst (
.clk(clk_100m),
.reset_n(reset_n),
.data_in(fir_d_in_q), // Use synchronized data
.data_valid(fir_in_valid_q), // Use synchronized valid
.data_out(fir_q_out),
.data_out_valid(fir_valid_q),
.fir_ready(fir_q_ready),
.filter_overflow()
);
assign fir_valid = fir_valid_i & fir_valid_q;
// ============================================================================
// Enhanced Output Stage
// ============================================================================
always @(posedge clk_100m or negedge reset_n) begin
if (!reset_n) begin
baseband_i_reg <= 0;
baseband_q_reg <= 0;
baseband_valid_reg <= 0;
end else if (fir_valid) begin
baseband_i_reg <= fir_i_out;
baseband_q_reg <= fir_q_out;
baseband_valid_reg <= 1;
end else begin
baseband_valid_reg <= 0;
end
end
// ============================================================================
// Output Assignments
// ============================================================================
assign baseband_i = baseband_i_reg;
assign baseband_q = baseband_q_reg;
// FIR I channel
fir_lowpass_parallel_enhanced fir_i_inst (
.clk(clk_100m),
.reset_n(reset_n),
.data_in(fir_d_in_i), // Use synchronized data
.data_valid(fir_in_valid_i), // Use synchronized valid
.data_out(fir_i_out),
.data_out_valid(fir_valid_i),
.fir_ready(fir_i_ready),
.filter_overflow()
);
// FIR Q channel
fir_lowpass_parallel_enhanced fir_q_inst (
.clk(clk_100m),
.reset_n(reset_n),
.data_in(fir_d_in_q), // Use synchronized data
.data_valid(fir_in_valid_q), // Use synchronized valid
.data_out(fir_q_out),
.data_out_valid(fir_valid_q),
.fir_ready(fir_q_ready),
.filter_overflow()
);
assign fir_valid = fir_valid_i & fir_valid_q;
// ============================================================================
// Enhanced Output Stage
// ============================================================================
always @(posedge clk_100m or negedge reset_n) begin
if (!reset_n) begin
baseband_i_reg <= 0;
baseband_q_reg <= 0;
baseband_valid_reg <= 0;
end else if (fir_valid) begin
baseband_i_reg <= fir_i_out;
baseband_q_reg <= fir_q_out;
baseband_valid_reg <= 1;
end else begin
baseband_valid_reg <= 0;
end
end
// ============================================================================
// Output Assignments
// ============================================================================
assign baseband_i = baseband_i_reg;
assign baseband_q = baseband_q_reg;
assign baseband_valid_i = baseband_valid_reg;
assign baseband_valid_q = baseband_valid_reg;
assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
assign mixer_saturation = overflow_detected;
assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
// ============================================================================
// Enhanced Debug and Monitoring
// ============================================================================
assign baseband_valid_q = baseband_valid_reg;
assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
assign mixer_saturation = overflow_detected;
assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
// ============================================================================
// Enhanced Debug and Monitoring
// ============================================================================
reg [31:0] debug_cic_count, debug_fir_count, debug_bb_count;
`ifdef SIMULATION
@@ -708,10 +699,10 @@ always @(posedge clk_100m) begin
baseband_i, baseband_q, debug_bb_count);
end
end
`endif
// In ddc_400m.v, add these debug signals:
`endif
// In ddc_400m.v, add these debug signals:
// Debug monitoring (simulation only)
`ifdef SIMULATION
reg [31:0] debug_adc_count = 0;
@@ -732,67 +723,58 @@ always @(posedge clk_100m) begin
baseband_i, baseband_q, debug_baseband_count, $time);
end
end
`endif
endmodule
// ============================================================================
// Enhanced Phase Dithering Module
// ============================================================================
`timescale 1ns / 1ps
module lfsr_dither_enhanced #(
parameter DITHER_WIDTH = 8 // Increased for better dithering
)(
input wire clk,
input wire reset_n,
input wire enable,
output wire [DITHER_WIDTH-1:0] dither_out
);
reg [DITHER_WIDTH-1:0] lfsr_reg;
reg [15:0] cycle_counter;
reg lock_detected;
// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
wire feedback;
generate
if (DITHER_WIDTH == 4) begin
assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
end else if (DITHER_WIDTH == 8) begin
assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
end else begin
assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
end
endgenerate
// ============================================================================
// RESET FAN-OUT INVARIANT: registered active-high reset with max_fanout=50.
// See cic_decimator_4x_enhanced.v for full reasoning. reset_n here is driven
// by the parent DDC's reset_n_400m (already synchronized to clk_400m), so
// sync reset on the LFSR is safe. INIT=1'b1 holds LFSR in reset on power-up.
// ============================================================================
(* max_fanout = 50 *) reg reset_h = 1'b1;
always @(posedge clk) reset_h <= ~reset_n;
always @(posedge clk) begin
if (reset_h) begin
lfsr_reg <= {DITHER_WIDTH{1'b1}}; // Non-zero initial state
cycle_counter <= 0;
lock_detected <= 0;
end else if (enable) begin
lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
cycle_counter <= cycle_counter + 1;
// Detect LFSR lock after sufficient cycles
if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
lock_detected <= 1'b1;
end
end
end
assign dither_out = lfsr_reg;
endmodule
`endif
endmodule
// ============================================================================
// Enhanced Phase Dithering Module
// ============================================================================
`timescale 1ns / 1ps
module lfsr_dither_enhanced #(
parameter DITHER_WIDTH = 8 // Increased for better dithering
)(
input wire clk,
input wire reset_n,
input wire enable,
output wire [DITHER_WIDTH-1:0] dither_out
);
reg [DITHER_WIDTH-1:0] lfsr_reg;
reg [15:0] cycle_counter;
reg lock_detected;
// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
wire feedback;
generate
if (DITHER_WIDTH == 4) begin
assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
end else if (DITHER_WIDTH == 8) begin
assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
end else begin
assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
end
endgenerate
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
lfsr_reg <= {DITHER_WIDTH{1'b1}}; // Non-zero initial state
cycle_counter <= 0;
lock_detected <= 0;
end else if (enable) begin
lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
cycle_counter <= cycle_counter + 1;
// Detect LFSR lock after sufficient cycles
if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
lock_detected <= 1'b1;
end
end
end
assign dither_out = lfsr_reg;
endmodule
9_Firmware/9_2_FPGA/matched_filter_multi_segment.v
+7 -9
View File
@@ -18,10 +18,9 @@ module matched_filter_multi_segment (
input wire mc_new_elevation, // Toggle for new elevation (32)
input wire mc_new_azimuth, // Toggle for new azimuth (50)
input wire [15:0] long_chirp_real,
input wire [15:0] long_chirp_imag,
input wire [15:0] short_chirp_real,
input wire [15:0] short_chirp_imag,
// Reference chirp (upstream memory loader selects long/short via use_long_chirp)
input wire [15:0] ref_chirp_real,
input wire [15:0] ref_chirp_imag,
// Memory system interface
output reg [1:0] segment_request,
@@ -244,6 +243,7 @@ always @(posedge clk or negedge reset_n) begin
if (!use_long_chirp) begin
if (chirp_samples_collected >= SHORT_CHIRP_SAMPLES - 1) begin
state <= ST_ZERO_PAD;
chirp_complete <= 1; // Bug A fix: mark chirp done so ST_OUTPUT exits to IDLE
`ifdef SIMULATION
$display("[MULTI_SEG_FIXED] Short chirp: collected %d samples, starting zero-pad",
chirp_samples_collected + 1);
@@ -500,11 +500,9 @@ matched_filter_processing_chain m_f_p_c(
// Chirp Selection
.chirp_counter(chirp_counter),
// Reference Chirp Memory Interfaces
.long_chirp_real(long_chirp_real),
.long_chirp_imag(long_chirp_imag),
.short_chirp_real(short_chirp_real),
.short_chirp_imag(short_chirp_imag),
// Reference Chirp Memory Interface (single pair — upstream selects long/short)
.ref_chirp_real(ref_chirp_real),
.ref_chirp_imag(ref_chirp_imag),
// Output
.range_profile_i(fft_pc_i),
9_Firmware/9_2_FPGA/matched_filter_processing_chain.v
+13 -13
View File
@@ -15,7 +15,7 @@
* .clk, .reset_n
* .adc_data_i, .adc_data_q, .adc_valid <- from input buffer
* .chirp_counter <- 6-bit frame counter
* .long_chirp_real/imag, .short_chirp_real/imag <- reference (time-domain)
* .ref_chirp_real/imag <- reference (time-domain)
* .range_profile_i, .range_profile_q, .range_profile_valid -> output
* .chain_state -> 4-bit status
*
@@ -48,10 +48,10 @@ module matched_filter_processing_chain (
input wire [5:0] chirp_counter,
// Reference chirp (time-domain, latency-aligned by upstream buffer)
input wire [15:0] long_chirp_real,
input wire [15:0] long_chirp_imag,
input wire [15:0] short_chirp_real,
input wire [15:0] short_chirp_imag,
// Upstream chirp_memory_loader_param selects long/short reference
// via use_long_chirp — this single pair carries whichever is active.
input wire [15:0] ref_chirp_real,
input wire [15:0] ref_chirp_imag,
// Output: range profile (pulse-compressed)
output wire signed [15:0] range_profile_i,
@@ -189,8 +189,8 @@ always @(posedge clk or negedge reset_n) begin
// Store first sample (signal + reference)
fwd_buf_i[0] <= $signed(adc_data_i);
fwd_buf_q[0] <= $signed(adc_data_q);
ref_buf_i[0] <= $signed(long_chirp_real);
ref_buf_q[0] <= $signed(long_chirp_imag);
ref_buf_i[0] <= $signed(ref_chirp_real);
ref_buf_q[0] <= $signed(ref_chirp_imag);
fwd_in_count <= 1;
state <= ST_FWD_FFT;
end
@@ -205,8 +205,8 @@ always @(posedge clk or negedge reset_n) begin
if (adc_valid && fwd_in_count < FFT_SIZE) begin
fwd_buf_i[fwd_in_count] <= $signed(adc_data_i);
fwd_buf_q[fwd_in_count] <= $signed(adc_data_q);
ref_buf_i[fwd_in_count] <= $signed(long_chirp_real);
ref_buf_q[fwd_in_count] <= $signed(long_chirp_imag);
ref_buf_i[fwd_in_count] <= $signed(ref_chirp_real);
ref_buf_q[fwd_in_count] <= $signed(ref_chirp_imag);
fwd_in_count <= fwd_in_count + 1;
end
@@ -775,16 +775,16 @@ always @(posedge clk) begin : ref_bram_port
if (adc_valid) begin
we = 1'b1;
addr = 0;
wdata_i = $signed(long_chirp_real);
wdata_q = $signed(long_chirp_imag);
wdata_i = $signed(ref_chirp_real);
wdata_q = $signed(ref_chirp_imag);
end
end
ST_COLLECT: begin
if (adc_valid && collect_count < FFT_SIZE) begin
we = 1'b1;
addr = collect_count[ADDR_BITS-1:0];
wdata_i = $signed(long_chirp_real);
wdata_q = $signed(long_chirp_imag);
wdata_i = $signed(ref_chirp_real);
wdata_q = $signed(ref_chirp_imag);
end
end
ST_REF_FFT: begin
9_Firmware/9_2_FPGA/nco_400m_enhanced.v
+16 -35
View File
@@ -59,25 +59,6 @@ reg [1:0] quadrant_reg2; // Pass-through for Stage 5 MUX
// Valid pipeline: tracks 6-stage latency
reg [5:0] valid_pipe;
// ============================================================================
// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
// ============================================================================
// reset_h is an ACTIVE-HIGH, REGISTERED copy of ~reset_n with (* max_fanout=50 *).
// Vivado replicates this register (14+ copies) so each copy drives ≈50 loads
// regionally, avoiding the single-LUT1 / 702-load net that caused timing
// failure in Build N. It feeds:
// - DSP48E1 RSTP/RSTC on the phase-accumulator DSP (below)
// - All pipeline-stage fabric FDREs (synchronous reset)
// Invariants (see cic_decimator_4x_enhanced.v for full reasoning):
// I1 correctness: reset_h == ~reset_n one cycle later
// I2 glitch-free: registered output
// I3 power-up safe: INIT=1'b1 holds all downstream in reset until first
// valid clock edge; reset_n is low on power-up anyway
// I4 de-assert lat.: +1 cycle vs. direct async; negligible at 400 MHz
// ============================================================================
(* max_fanout = 50 *) reg reset_h = 1'b1;
always @(posedge clk_400m) reset_h <= ~reset_n;
// Use only the top 8 bits for LUT addressing (256-entry LUT equivalent)
wire [7:0] lut_address = phase_with_offset[31:24];
@@ -154,8 +135,8 @@ wire [15:0] cos_abs_w = sin_lut[63 - lut_index_pipe_cos];
// Stage 2: phase_with_offset adds phase offset
reg [31:0] phase_accumulator;
always @(posedge clk_400m) begin
if (reset_h) begin
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
phase_accumulator <= 32'h00000000;
phase_accum_reg <= 32'h00000000;
phase_with_offset <= 32'h00000000;
@@ -209,8 +190,8 @@ DSP48E1 #(
.RSTA(1'b0),
.RSTB(1'b0),
.RSTM(1'b0),
.RSTP(reset_h), // Reset P register (phase accumulator) — registered, max_fanout=50
.RSTC(reset_h), // Reset C register (tuning word) — registered, max_fanout=50
.RSTP(!reset_n), // Reset P register (phase accumulator) on !reset_n
.RSTC(!reset_n), // Reset C register (tuning word) on !reset_n
.RSTALLCARRYIN(1'b0),
.RSTALUMODE(1'b0),
.RSTCTRL(1'b0),
@@ -264,8 +245,8 @@ DSP48E1 #(
// Stage 1: Capture DSP48E1 P output into fabric register
// Stage 2: Add phase offset to captured value
// Split into two registered stages to break DSP48E1.P→CARRY4 critical path
always @(posedge clk_400m) begin
if (reset_h) begin
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
phase_accum_reg <= 32'h00000000;
phase_with_offset <= 32'h00000000;
end else if (phase_valid) begin
@@ -283,8 +264,8 @@ end
// Only 2 registers driven (lut_index_pipe + quadrant_pipe)
// Minimal fanout → short routes → easy timing
// ============================================================================
always @(posedge clk_400m) begin
if (reset_h) begin
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
lut_index_pipe_sin <= 6'b000000;
lut_index_pipe_cos <= 6'b000000;
quadrant_pipe <= 2'b00;
@@ -300,8 +281,8 @@ end
// Registered address → combinational LUT6 read → register
// Only 1 logic level (LUT6), trivial timing
// ============================================================================
always @(posedge clk_400m) begin
if (reset_h) begin
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
sin_abs_reg <= 16'h0000;
cos_abs_reg <= 16'h7FFF;
quadrant_reg <= 2'b00;
@@ -317,8 +298,8 @@ end
// CARRY4 x4 chain has registered inputs — easily fits in 2.5ns
// Also pass through abs values and quadrant for Stage 5
// ============================================================================
always @(posedge clk_400m) begin
if (reset_h) begin
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
sin_neg_reg <= 16'h0000;
cos_neg_reg <= -16'h7FFF;
sin_abs_reg2 <= 16'h0000;
@@ -337,8 +318,8 @@ end
// Stage 5: Quadrant sign application → final sin/cos output
// Uses pre-computed negated values from Stage 4 — pure MUX, no arithmetic
// ============================================================================
always @(posedge clk_400m) begin
if (reset_h) begin
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
sin_out <= 16'h0000;
cos_out <= 16'h7FFF;
end else if (valid_pipe[4]) begin
@@ -366,8 +347,8 @@ end
// ============================================================================
// Valid pipeline and dds_ready (6-stage latency)
// ============================================================================
always @(posedge clk_400m) begin
if (reset_h) begin
always @(posedge clk_400m or negedge reset_n) begin
if (!reset_n) begin
valid_pipe <= 6'b000000;
dds_ready <= 1'b0;
end else begin
9_Firmware/9_2_FPGA/radar_params.vh
+200
View File
@@ -0,0 +1,200 @@
// ============================================================================
// radar_params.vh — Single Source of Truth for AERIS-10 FPGA Parameters
// ============================================================================
//
// ALL modules in the FPGA processing chain MUST `include this file instead of
// hardcoding range bins, segment counts, chirp samples, or timing values.
//
// This file uses `define macros (not localparam) so it can be included at any
// scope. Each consuming module should include this file inside its body and
// optionally alias macros to localparams for readability.
//
// BOARD VARIANTS:
// SUPPORT_LONG_RANGE = 0 (50T, USB_MODE=1) — 3 km mode only, 64 range bins
// SUPPORT_LONG_RANGE = 1 (200T, USB_MODE=0) — 3 km + 20 km modes, up to 1024 bins
//
// RANGE MODES (runtime, via host_range_mode register, opcode 0x20):
// 2'b00 = 3 km (default on both boards)
// 2'b01 = 20 km (200T only; clamped to 3 km on 50T)
// 2'b10 = Reserved
// 2'b11 = Reserved
//
// USAGE:
// `include "radar_params.vh"
// Then reference `RP_FFT_SIZE, `RP_MAX_OUTPUT_BINS, etc.
//
// PHYSICAL CONSTANTS (derived from hardware):
// ADC clock: 400 MSPS
// CIC decimation: 4x
// Processing rate: 100 MSPS (post-DDC)
// Range per sample: c / (2 * 100e6) = 1.5 m
// Decimation factor: 16 (1024 FFT bins -> 64 output bins per segment)
// Range per dec. bin: 1.5 m * 16 = 24.0 m
// Carrier frequency: 10.5 GHz
//
// CHIRP BANDWIDTH (Phase 1 target — currently 20 MHz, planned 30 MHz):
// Range resolution: c / (2 * BW)
// 20 MHz -> 7.5 m
// 30 MHz -> 5.0 m
// NOTE: Range resolution is independent of range-per-bin. Resolution
// determines the minimum separation between two targets; range-per-bin
// determines the spatial sampling grid.
// ============================================================================
`ifndef RADAR_PARAMS_VH
`define RADAR_PARAMS_VH
// ============================================================================
// BOARD VARIANT — set at synthesis time, NOT runtime
// ============================================================================
// Default to 50T (conservative). Override in top-level or synthesis script:
// +define+SUPPORT_LONG_RANGE
// or via Vivado: set_property verilog_define {SUPPORT_LONG_RANGE} [current_fileset]
// Note: SUPPORT_LONG_RANGE is a flag define (ifdef/ifndef), not a value.
// `ifndef SUPPORT_LONG_RANGE means 50T (no long range).
// `ifdef SUPPORT_LONG_RANGE means 200T (long range supported).
// ============================================================================
// FFT AND PROCESSING CONSTANTS (fixed, both modes)
// ============================================================================
`define RP_FFT_SIZE 1024 // Range FFT points per segment
`define RP_OVERLAP_SAMPLES 128 // Overlap between adjacent segments
`define RP_SEGMENT_ADVANCE 896 // FFT_SIZE - OVERLAP = 1024 - 128
`define RP_DECIMATION_FACTOR 16 // Range bin decimation (1024 -> 64)
`define RP_BINS_PER_SEGMENT 64 // FFT_SIZE / DECIMATION_FACTOR
`define RP_DOPPLER_FFT_SIZE 16 // Per sub-frame Doppler FFT
`define RP_CHIRPS_PER_FRAME 32 // Total chirps (16 long + 16 short)
`define RP_CHIRPS_PER_SUBFRAME 16 // Chirps per Doppler sub-frame
`define RP_NUM_DOPPLER_BINS 32 // 2 sub-frames * 16 = 32
`define RP_DATA_WIDTH 16 // ADC/processing data width
// ============================================================================
// 3 KM MODE PARAMETERS (both 50T and 200T)
// ============================================================================
`define RP_LONG_CHIRP_SAMPLES_3KM 3000 // 30 us at 100 MSPS
`define RP_LONG_SEGMENTS_3KM 4 // ceil((3000-1024)/896) + 1 = 4
`define RP_OUTPUT_RANGE_BINS_3KM 64 // Downstream pipeline expects 64 range bins (NOTE: will become 128 after 2048-pt FFT upgrade)
`define RP_SHORT_CHIRP_SAMPLES 50 // 0.5 us at 100 MSPS (same both modes)
`define RP_SHORT_SEGMENTS 1 // Single segment for short chirp
// Derived 3 km limits
`define RP_MAX_RANGE_3KM 1536 // 64 bins * 24 m = 1536 m
// ============================================================================
// 20 KM MODE PARAMETERS (200T only)
// ============================================================================
`define RP_LONG_CHIRP_SAMPLES_20KM 13700 // 137 us at 100 MSPS (= listen window)
`define RP_LONG_SEGMENTS_20KM 16 // ceil((13700-1024)/896) + 1 = 16
`define RP_OUTPUT_RANGE_BINS_20KM 1024 // 16 segments * 64 dec. bins each
// Derived 20 km limits
`define RP_MAX_RANGE_20KM 24576 // 1024 bins * 24 m = 24576 m
// ============================================================================
// MAX VALUES (for sizing buffers — compile-time, based on board variant)
// ============================================================================
`ifdef SUPPORT_LONG_RANGE
`define RP_MAX_SEGMENTS 16
`define RP_MAX_OUTPUT_BINS 1024
`define RP_MAX_CHIRP_SAMPLES 13700
`else
`define RP_MAX_SEGMENTS 4
`define RP_MAX_OUTPUT_BINS 64
`define RP_MAX_CHIRP_SAMPLES 3000
`endif
// ============================================================================
// BIT WIDTHS (derived from MAX values)
// ============================================================================
// Segment index: ceil(log2(MAX_SEGMENTS))
// 50T: log2(4) = 2 bits
// 200T: log2(16) = 4 bits
`ifdef SUPPORT_LONG_RANGE
`define RP_SEGMENT_IDX_WIDTH 4
`define RP_RANGE_BIN_WIDTH 10
`define RP_CHIRP_MEM_ADDR_W 14 // log2(16*1024) = 14
`define RP_DOPPLER_MEM_ADDR_W 15 // log2(1024*32) = 15
`define RP_CFAR_MAG_ADDR_W 15 // log2(1024*32) = 15
`else
`define RP_SEGMENT_IDX_WIDTH 2
`define RP_RANGE_BIN_WIDTH 6
`define RP_CHIRP_MEM_ADDR_W 12 // log2(4*1024) = 12
`define RP_DOPPLER_MEM_ADDR_W 11 // log2(64*32) = 11
`define RP_CFAR_MAG_ADDR_W 11 // log2(64*32) = 11
`endif
// Derived depths (for memory declarations)
// Usage: reg [15:0] mem [0:`RP_CHIRP_MEM_DEPTH-1];
`define RP_CHIRP_MEM_DEPTH (`RP_MAX_SEGMENTS * `RP_FFT_SIZE)
`define RP_DOPPLER_MEM_DEPTH (`RP_MAX_OUTPUT_BINS * `RP_CHIRPS_PER_FRAME)
`define RP_CFAR_MAG_DEPTH (`RP_MAX_OUTPUT_BINS * `RP_NUM_DOPPLER_BINS)
// ============================================================================
// CHIRP TIMING DEFAULTS (100 MHz clock cycles)
// ============================================================================
// Reset defaults for host-configurable timing registers.
// Match radar_mode_controller.v parameters and main.cpp STM32 defaults.
`define RP_DEF_LONG_CHIRP_CYCLES 3000 // 30 us
`define RP_DEF_LONG_LISTEN_CYCLES 13700 // 137 us
`define RP_DEF_GUARD_CYCLES 17540 // 175.4 us
`define RP_DEF_SHORT_CHIRP_CYCLES 50 // 0.5 us
`define RP_DEF_SHORT_LISTEN_CYCLES 17450 // 174.5 us
`define RP_DEF_CHIRPS_PER_ELEV 32
// ============================================================================
// BLIND ZONE CONSTANTS (informational, for comments and GUI)
// ============================================================================
// Long chirp blind zone: c * 30 us / 2 = 4500 m
// Short chirp blind zone: c * 0.5 us / 2 = 75 m
`define RP_LONG_BLIND_ZONE_M 4500
`define RP_SHORT_BLIND_ZONE_M 75
// ============================================================================
// PHYSICAL CONSTANTS (integer-scaled for Verilog — use in comments/assertions)
// ============================================================================
// Range per ADC sample: 1.5 m (stored as 15 in units of 0.1 m)
// Range per decimated bin: 24.0 m (stored as 240 in units of 0.1 m)
// Processing rate: 100 MSPS
`define RP_RANGE_PER_SAMPLE_DM 15 // 1.5 m in decimeters
`define RP_RANGE_PER_BIN_DM 240 // 24.0 m in decimeters
`define RP_PROCESSING_RATE_MHZ 100
// ============================================================================
// AGC DEFAULTS
// ============================================================================
`define RP_DEF_AGC_TARGET 200
`define RP_DEF_AGC_ATTACK 1
`define RP_DEF_AGC_DECAY 1
`define RP_DEF_AGC_HOLDOFF 4
// ============================================================================
// CFAR DEFAULTS
// ============================================================================
`define RP_DEF_CFAR_GUARD 2
`define RP_DEF_CFAR_TRAIN 8
`define RP_DEF_CFAR_ALPHA 8'h30 // 3.0 in Q4.4
`define RP_DEF_CFAR_MODE 2'b00 // CA-CFAR
// ============================================================================
// DETECTION DEFAULTS
// ============================================================================
`define RP_DEF_DETECT_THRESHOLD 10000
// ============================================================================
// RANGE MODE ENCODING
// ============================================================================
`define RP_RANGE_MODE_3KM 2'b00
`define RP_RANGE_MODE_20KM 2'b01
`define RP_RANGE_MODE_RSVD2 2'b10
`define RP_RANGE_MODE_RSVD3 2'b11
`endif // RADAR_PARAMS_VH
9_Firmware/9_2_FPGA/radar_receiver_final.v
+36 -31
View File
@@ -11,10 +11,8 @@ module radar_receiver_final (
input wire adc_dco_n, // Data Clock Output N (400MHz LVDS)
output wire adc_pwdn,
// Chirp counter from transmitter (for matched filter indexing)
// Chirp counter from transmitter (for frame sync and matched filter)
input wire [5:0] chirp_counter,
// Frame-start pulse from transmitter (CDC-synchronized, 1 clk_100m cycle)
input wire tx_frame_start,
output wire [31:0] doppler_output,
output wire doppler_valid,
@@ -104,9 +102,9 @@ wire [7:0] gc_saturation_count; // Diagnostic: per-frame clipped sample counter
wire [7:0] gc_peak_magnitude; // Diagnostic: per-frame peak magnitude
wire [3:0] gc_current_gain; // Diagnostic: effective gain_shift
// Reference signals for the processing chain
wire [15:0] long_chirp_real, long_chirp_imag;
wire [15:0] short_chirp_real, short_chirp_imag;
// Reference signal for the processing chain (carries long OR short ref
// depending on use_long_chirp — selected by chirp_memory_loader_param)
wire [15:0] ref_chirp_real, ref_chirp_imag;
// ========== DOPPLER PROCESSING SIGNALS ==========
wire [31:0] range_data_32bit;
@@ -294,7 +292,8 @@ end
// sample_addr_wire removed — was unused implicit wire (synthesis warning)
// 4. CRITICAL: Reference Chirp Latency Buffer
// This aligns reference data with FFT output (2159 cycle delay)
// This aligns reference data with FFT output (3187 cycle delay)
// TODO: verify empirically during hardware bring-up with correlation test
wire [15:0] delayed_ref_i, delayed_ref_q;
wire mem_ready_delayed;
@@ -310,11 +309,10 @@ latency_buffer #(
.valid_out(mem_ready_delayed)
);
// Assign delayed reference signals
assign long_chirp_real = delayed_ref_i;
assign long_chirp_imag = delayed_ref_q;
assign short_chirp_real = delayed_ref_i;
assign short_chirp_imag = delayed_ref_q;
// Assign delayed reference signals (single pair — chirp_memory_loader_param
// selects long/short reference upstream via use_long_chirp)
assign ref_chirp_real = delayed_ref_i;
assign ref_chirp_imag = delayed_ref_q;
// 5. Dual Chirp Matched Filter
@@ -338,10 +336,8 @@ matched_filter_multi_segment mf_dual (
.mc_new_chirp(mc_new_chirp),
.mc_new_elevation(mc_new_elevation),
.mc_new_azimuth(mc_new_azimuth),
.long_chirp_real(delayed_ref_i), // From latency buffer
.long_chirp_imag(delayed_ref_q),
.short_chirp_real(delayed_ref_i), // Same for short chirp
.short_chirp_imag(delayed_ref_q),
.ref_chirp_real(delayed_ref_i), // From latency buffer (long or short ref)
.ref_chirp_imag(delayed_ref_q),
.segment_request(segment_request),
.mem_request(mem_request),
.sample_addr_out(sample_addr_from_chain),
@@ -394,31 +390,32 @@ mti_canceller #(
.mti_first_chirp(mti_first_chirp)
);
// ========== FRAME SYNC FROM TRANSMITTER ==========
// [FPGA-001 FIXED] Use the authoritative new_chirp_frame signal from the
// transmitter (via plfm_chirp_controller_enhanced), CDC-synchronized to
// clk_100m in radar_system_top. Previous code tried to derive frame
// boundaries from chirp_counter == 0, but that counter comes from the
// transmitter path (plfm_chirp_controller_enhanced) which does NOT wrap
// at chirps_per_elev — it overflows to N and only wraps at 6-bit rollover
// (64). This caused frame pulses at half the expected rate for N=32.
reg tx_frame_start_prev;
// ========== FRAME SYNC USING chirp_counter ==========
reg [5:0] chirp_counter_prev;
reg new_frame_pulse;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
tx_frame_start_prev <= 1'b0;
chirp_counter_prev <= 6'd0;
new_frame_pulse <= 1'b0;
end else begin
// Default: no pulse
new_frame_pulse <= 1'b0;
// Edge detect: tx_frame_start is a toggle-CDC derived pulse that
// may be 1 clock wide. Capture rising edge for clean 1-cycle pulse.
if (tx_frame_start && !tx_frame_start_prev) begin
new_frame_pulse <= 1'b1;
// Dynamic frame detection using host_chirps_per_elev.
// Detect frame boundary when chirp_counter changes AND is a
// multiple of host_chirps_per_elev (0, N, 2N, 3N, ...).
// Uses a modulo counter that resets at host_chirps_per_elev.
if (chirp_counter != chirp_counter_prev) begin
if (chirp_counter == 6'd0 ||
chirp_counter == host_chirps_per_elev ||
chirp_counter == {host_chirps_per_elev, 1'b0}) begin
new_frame_pulse <= 1'b1;
end
end
tx_frame_start_prev <= tx_frame_start;
// Store previous value
chirp_counter_prev <= chirp_counter;
end
end
@@ -484,6 +481,14 @@ always @(posedge clk or negedge reset_n) begin
`endif
chirps_in_current_frame <= 0;
end
// Monitor chirp counter pattern
if (chirp_counter != chirp_counter_prev) begin
`ifdef SIMULATION
$display("[TOP] chirp_counter: %0d ? %0d",
chirp_counter_prev, chirp_counter);
`endif
end
end
end
9_Firmware/9_2_FPGA/radar_system_top.v
+4 -8
View File
@@ -130,7 +130,7 @@ module radar_system_top (
// FPGA→STM32 GPIO outputs (DIG_5..DIG_7 on 50T board)
// Used by STM32 outer AGC loop to read saturation state without USB polling.
output wire gpio_dig5, // DIG_5 (H11→PD13): AGC saturation flag (1=clipping detected)
output wire gpio_dig6, // DIG_6 (G12→PD14): AGC enable flag (mirrors host_agc_enable)
output wire gpio_dig6, // DIG_6 (G12→PD14): reserved (tied low)
output wire gpio_dig7 // DIG_7 (H12→PD15): reserved (tied low)
);
@@ -142,7 +142,7 @@ module radar_system_top (
parameter USE_LONG_CHIRP = 1'b1; // Default to long chirp
parameter DOPPLER_ENABLE = 1'b1; // Enable Doppler processing
parameter USB_ENABLE = 1'b1; // Enable USB data transfer
parameter USB_MODE = 1; // 0=FT601 (32-bit, 200T), 1=FT2232H (8-bit, 50T production default)
parameter USB_MODE = 0; // 0=FT601 (32-bit, 200T), 1=FT2232H (8-bit, 50T)
// ============================================================================
// INTERNAL SIGNALS
@@ -505,8 +505,6 @@ radar_receiver_final rx_inst (
// Chirp counter from transmitter (CDC-synchronized from 120 MHz domain)
.chirp_counter(tx_current_chirp_sync),
// Frame-start pulse from transmitter (CDC-synchronized toggle→pulse)
.tx_frame_start(tx_new_chirp_frame_sync),
// ADC Physical Interface
.adc_d_p(adc_d_p),
@@ -1037,11 +1035,9 @@ assign system_status = status_reg;
// ============================================================================
// DIG_5: AGC saturation flag — high when per-frame saturation_count > 0.
// STM32 reads PD13 to detect clipping and adjust ADAR1000 VGA gain.
// DIG_6: AGC enable flag — mirrors host_agc_enable so STM32 outer-loop AGC
// tracks the FPGA register as single source of truth.
// DIG_7: Reserved (tied low for future use).
// DIG_6, DIG_7: Reserved (tied low for future use).
assign gpio_dig5 = (rx_agc_saturation_count != 8'd0);
assign gpio_dig6 = host_agc_enable;
assign gpio_dig6 = 1'b0;
assign gpio_dig7 = 1'b0;
// ============================================================================
9_Firmware/9_2_FPGA/radar_system_top_te0713_umft601x_dev.v
+1 -6
View File
@@ -138,12 +138,7 @@ usb_data_interface usb_inst (
.status_range_mode(2'b01),
.status_self_test_flags(5'b11111),
.status_self_test_detail(8'hA5),
.status_self_test_busy(1'b0),
// AGC status: tie off with benign defaults (no AGC on dev board)
.status_agc_current_gain(4'd0),
.status_agc_peak_magnitude(8'd0),
.status_agc_saturation_count(8'd0),
.status_agc_enable(1'b0)
.status_self_test_busy(1'b0)
);
endmodule
9_Firmware/9_2_FPGA/run_regression.sh
+128 -56
View File
@@ -70,7 +70,6 @@ PROD_RTL=(
xfft_16.v
fft_engine.v
usb_data_interface.v
usb_data_interface_ft2232h.v
edge_detector.v
radar_mode_controller.v
rx_gain_control.v
@@ -87,33 +86,6 @@ EXTRA_RTL=(
frequency_matched_filter.v
)
# ---------------------------------------------------------------------------
# Shared RTL file lists for integration / system tests
# Centralised here so a new module only needs adding once.
# ---------------------------------------------------------------------------
# Receiver chain (used by golden generate/compare tests)
RECEIVER_RTL=(
radar_receiver_final.v
radar_mode_controller.v
tb/ad9484_interface_400m_stub.v
ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v
cdc_modules.v fir_lowpass.v ddc_input_interface.v
chirp_memory_loader_param.v latency_buffer.v
matched_filter_multi_segment.v matched_filter_processing_chain.v
range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v
rx_gain_control.v mti_canceller.v
)
# Full system top (receiver chain + TX + USB + detection + self-test)
SYSTEM_RTL=(
radar_system_top.v
radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v
"${RECEIVER_RTL[@]}"
usb_data_interface.v usb_data_interface_ft2232h.v edge_detector.v
cfar_ca.v fpga_self_test.v
)
# ---- Layer A: iverilog -Wall compilation ----
run_lint_iverilog() {
local label="$1"
@@ -247,9 +219,26 @@ run_lint_static() {
fi
done
# CHECK 5 ($readmemh in synth code) and CHECK 6 (unused includes)
# require multi-line ifdef tracking / cross-file analysis. Not feasible
# with line-by-line regex. Omitted — use Vivado lint instead.
# --- Single-line regex checks across all production RTL ---
for f in "$@"; do
[[ -f "$f" ]] || continue
case "$f" in tb/*) continue ;; esac
local linenum=0
while IFS= read -r line; do
linenum=$((linenum + 1))
# CHECK 5: $readmemh / $readmemb in synthesizable code
# (Only valid in simulation blocks — flag if outside `ifdef SIMULATION)
# This is hard to check line-by-line without tracking ifdefs.
# Skip for v1.
# CHECK 6: Unused `include files (informational only)
# Skip for v1.
: # placeholder — prevents empty loop body
done < "$f"
done
if [[ "$err_count" -gt 0 ]]; then
echo -e "${RED}FAIL${NC} ($err_count errors, $warn_count warnings)"
@@ -264,6 +253,68 @@ run_lint_static() {
fi
}
# ---------------------------------------------------------------------------
# Helper: compile, run, and compare a matched-filter co-sim scenario
# run_mf_cosim <scenario_name> <define_flag>
# ---------------------------------------------------------------------------
run_mf_cosim() {
local name="$1"
local define="$2"
local vvp="tb/tb_mf_cosim_${name}.vvp"
local scenario_lower="$name"
printf " %-45s " "MF Co-Sim ($name)"
# Compile — build command as string to handle optional define
local cmd="iverilog -g2001 -DSIMULATION"
if [[ -n "$define" ]]; then
cmd="$cmd $define"
fi
cmd="$cmd -o $vvp tb/tb_mf_cosim.v matched_filter_processing_chain.v fft_engine.v chirp_memory_loader_param.v"
if ! eval "$cmd" 2>/tmp/iverilog_err_$$; then
echo -e "${RED}COMPILE FAIL${NC}"
ERRORS="$ERRORS\n MF Co-Sim ($name): compile error ($(head -1 /tmp/iverilog_err_$$))"
FAIL=$((FAIL + 1))
return
fi
# Run TB
local output
output=$(timeout 120 vvp "$vvp" 2>&1) || true
rm -f "$vvp"
# Check TB internal pass/fail
local tb_fail
tb_fail=$(echo "$output" | grep -Ec '^\[FAIL' || true)
if [[ "$tb_fail" -gt 0 ]]; then
echo -e "${RED}FAIL${NC} (TB internal failure)"
ERRORS="$ERRORS\n MF Co-Sim ($name): TB internal failure"
FAIL=$((FAIL + 1))
return
fi
# Run Python compare
if command -v python3 >/dev/null 2>&1; then
local compare_out
local compare_rc=0
compare_out=$(python3 tb/cosim/compare_mf.py "$scenario_lower" 2>&1) || compare_rc=$?
if [[ "$compare_rc" -ne 0 ]]; then
echo -e "${RED}FAIL${NC} (compare_mf.py mismatch)"
ERRORS="$ERRORS\n MF Co-Sim ($name): Python compare failed"
FAIL=$((FAIL + 1))
return
fi
else
echo -e "${YELLOW}SKIP${NC} (RTL passed, python3 not found — compare skipped)"
SKIP=$((SKIP + 1))
return
fi
echo -e "${GREEN}PASS${NC} (RTL + Python compare)"
PASS=$((PASS + 1))
}
# ---------------------------------------------------------------------------
# Helper: compile and run a single testbench
# run_test <name> <vvp_path> <iverilog_args...>
@@ -427,44 +478,65 @@ run_test "Full-Chain Real-Data (decim→Doppler, exact match)" \
doppler_processor.v xfft_16.v fft_engine.v
if [[ "$QUICK" -eq 0 ]]; then
# Golden generate
run_test "Receiver (golden generate)" \
tb/tb_rx_golden_reg.vvp \
-DGOLDEN_GENERATE \
tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
# Golden compare
run_test "Receiver (golden compare)" \
tb/tb_rx_compare_reg.vvp \
tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
# NOTE: The "Receiver golden generate/compare" pair was REMOVED because
# it was self-blessing: both passes ran the same RTL with the same
# deterministic stimulus, so the test always passed regardless of bugs.
# Real co-sim coverage is provided by:
# - tb_doppler_realdata.v (committed Python golden hex, exact match)
# - tb_fullchain_realdata.v (committed Python golden hex, exact match)
# A proper full-pipeline co-sim (DDC→MF→Decim→Doppler vs Python) is
# planned as a replacement (Phase C of CI test plan).
# Full system top (monitoring-only, legacy)
run_test "System Top (radar_system_tb)" \
tb/tb_system_reg.vvp \
tb/radar_system_tb.v "${SYSTEM_RTL[@]}"
tb/radar_system_tb.v radar_system_top.v \
radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v \
radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
cdc_modules.v fir_lowpass.v ddc_input_interface.v \
chirp_memory_loader_param.v latency_buffer.v \
matched_filter_multi_segment.v matched_filter_processing_chain.v \
range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
usb_data_interface.v edge_detector.v radar_mode_controller.v \
rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
# E2E integration (46 strict checks: TX, RX, USB R/W, CDC, safety, reset)
run_test "System E2E (tb_system_e2e)" \
tb/tb_system_e2e_reg.vvp \
tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
# USB_MODE=1 (FT2232H production) variants of system tests
run_test "System Top USB_MODE=1 (FT2232H)" \
tb/tb_system_ft2232h_reg.vvp \
-DUSB_MODE_1 \
tb/radar_system_tb.v "${SYSTEM_RTL[@]}"
run_test "System E2E USB_MODE=1 (FT2232H)" \
tb/tb_system_e2e_ft2232h_reg.vvp \
-DUSB_MODE_1 \
tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
tb/tb_system_e2e.v radar_system_top.v \
radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v \
radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
cdc_modules.v fir_lowpass.v ddc_input_interface.v \
chirp_memory_loader_param.v latency_buffer.v \
matched_filter_multi_segment.v matched_filter_processing_chain.v \
range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
usb_data_interface.v edge_detector.v radar_mode_controller.v \
rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
else
echo " (skipped receiver golden + system top + E2E — use without --quick)"
SKIP=$((SKIP + 6))
echo " (skipped system top + E2E — use without --quick)"
SKIP=$((SKIP + 2))
fi
echo ""
# ===========================================================================
# PHASE 2b: MATCHED FILTER CO-SIMULATION (RTL vs Python golden reference)
# Runs tb_mf_cosim.v for 4 scenarios, then compare_mf.py validates output
# against committed Python golden CSV files. In SIMULATION mode, thresholds
# are generous (behavioral vs fixed-point twiddles differ) — validates
# state machine mechanics, output count, and energy sanity.
# ===========================================================================
echo "--- PHASE 2b: Matched Filter Co-Sim ---"
run_mf_cosim "chirp" ""
run_mf_cosim "dc" "-DSCENARIO_DC"
run_mf_cosim "impulse" "-DSCENARIO_IMPULSE"
run_mf_cosim "tone5" "-DSCENARIO_TONE5"
echo ""
# ===========================================================================
# PHASE 3: UNIT TESTS — Signal Processing
# ===========================================================================
9_Firmware/9_2_FPGA/rx_gain_control.v
+7 -7
View File
@@ -169,11 +169,11 @@ endfunction
// =========================================================================
// Clamp a wider signed value to [-7, +7]
function signed [3:0] clamp_gain;
input signed [5:0] val; // 6-bit: covers [-22,+22] (max |gain|+step = 7+15)
input signed [4:0] val; // 5-bit to handle overflow from add
begin
if (val > 6'sd7)
if (val > 5'sd7)
clamp_gain = 4'sd7;
else if (val < -6'sd7)
else if (val < -5'sd7)
clamp_gain = -4'sd7;
else
clamp_gain = val[3:0];
@@ -246,15 +246,15 @@ always @(posedge clk or negedge reset_n) begin
// Use inclusive counts/peaks (accounting for simultaneous valid_in)
if (wire_frame_sat_incr || frame_sat_count > 8'd0) begin
// Clipping detected: reduce gain immediately (attack)
agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain[3], agc_gain}) -
$signed({2'b00, agc_attack}));
agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain}) -
$signed({1'b0, agc_attack}));
holdoff_counter <= agc_holdoff; // Reset holdoff
end else if ((wire_frame_peak_update ? max_iq[14:7] : frame_peak[14:7])
< agc_target) begin
// Signal too weak: increase gain after holdoff expires
if (holdoff_counter == 4'd0) begin
agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain[3], agc_gain}) +
$signed({2'b00, agc_decay}));
agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain}) +
$signed({1'b0, agc_decay}));
end else begin
holdoff_counter <= holdoff_counter - 4'd1;
end
9_Firmware/9_2_FPGA/scripts/200t/build_200t.tcl
-3
View File
@@ -108,9 +108,6 @@ add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "
set_property top $top_module [current_fileset]
set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
# Override USB_MODE to 0 (FT601) for 200T premium board.
# The RTL default is USB_MODE=1 (FT2232H, production 50T).
set_property generic {USB_MODE=0} [current_fileset]
# ==============================================================================
# 2. Synthesis
9_Firmware/9_2_FPGA/tb/cosim/compare_mf_chirp.csv
-1025
View File
File diff suppressed because it is too large Load Diff
9_Firmware/9_2_FPGA/tb/cosim/compare_mf_dc.csv
-1025
View File
File diff suppressed because it is too large Load Diff
9_Firmware/9_2_FPGA/tb/cosim/compare_mf_impulse.csv
-1025
View File
File diff suppressed because it is too large Load Diff
9_Firmware/9_2_FPGA/tb/cosim/compare_mf_tone5.csv
-1025
View File
File diff suppressed because it is too large Load Diff
9_Firmware/9_2_FPGA/tb/cosim/fpga_model.py
+3 -6
View File
@@ -291,12 +291,9 @@ class Mixer:
Convert 8-bit unsigned ADC to 18-bit signed.
RTL: adc_signed_w = {1'b0, adc_data, {9{1'b0}}} -
{1'b0, {8{1'b1}}, {9{1'b0}}} / 2
Verilog '/' binds tighter than '-', so the division applies
only to the second concatenation:
{1'b0, 8'hFF, 9'b0} = 0x1FE00
0x1FE00 / 2 = 0xFF00 = 65280
Result: (adc_data << 9) - 0xFF00
= (adc_data << 9) - (0xFF << 9) / 2
= (adc_data << 9) - (0xFF << 8) [integer division]
= (adc_data << 9) - 0x7F80
"""
adc_data_8bit = adc_data_8bit & 0xFF
# {1'b0, adc_data, 9'b0} = adc_data << 9, zero-padded to 18 bits
9_Firmware/9_2_FPGA/tb/cosim/real_data/golden_reference.py
+17 -8
View File
@@ -2,8 +2,8 @@
"""
golden_reference.py — AERIS-10 FPGA bit-accurate golden reference model
Uses ADI CN0566 Phaser radar data (10.525 GHz X-band FMCW) to validate
the FPGA signal processing pipeline stage by stage:
Uses ADI CN0566 Phaser radar data (10.525 GHz, used as test stimulus only) to
validate the FPGA signal processing pipeline stage by stage:
ADC → DDC (NCO+mixer+CIC+FIR) → Range FFT → Doppler FFT → Detection
@@ -90,7 +90,8 @@ HAMMING_Q15 = [
0x3088, 0x1B6D, 0x0E5C, 0x0A3D,
]
# ADI dataset parameters
# ADI dataset parameters — used ONLY for loading/requantizing ADI Phaser test data.
# These are NOT PLFM hardware parameters. See AERIS-10 constants below.
ADI_SAMPLE_RATE = 4e6 # 4 MSPS
ADI_IF_FREQ = 100e3 # 100 kHz IF
ADI_RF_FREQ = 9.9e9 # 9.9 GHz
@@ -99,9 +100,17 @@ ADI_RAMP_TIME = 300e-6 # 300 us
ADI_NUM_CHIRPS = 256
ADI_SAMPLES_PER_CHIRP = 1079
# AERIS-10 parameters
AERIS_FS = 400e6 # 400 MHz ADC clock
AERIS_IF = 120e6 # 120 MHz IF
# AERIS-10 hardware parameters (from ADF4382/AD9523/main.cpp configuration)
AERIS_FS = 400e6 # 400 MHz ADC clock (AD9523 OUT4)
AERIS_IF = 120e6 # 120 MHz IF (TX 10.5 GHz - RX 10.38 GHz)
AERIS_FS_PROCESSING = 100e6 # Post-DDC rate (400 MSPS / 4x CIC)
AERIS_CARRIER_HZ = 10.5e9 # TX LO (ADF4382, verified)
AERIS_RX_LO_HZ = 10.38e9 # RX LO (ADF4382)
AERIS_CHIRP_BW = 20e6 # Chirp bandwidth (target: 30 MHz Phase 1)
AERIS_LONG_CHIRP_S = 30e-6 # Long chirp duration
AERIS_PRI_S = 167e-6 # Pulse repetition interval
AERIS_DECIMATION = 16 # Range bin decimation (1024 → 64)
AERIS_RANGE_PER_BIN = 24.0 # Meters per decimated bin
# ===========================================================================
@@ -290,9 +299,9 @@ def run_ddc(adc_samples):
for n in range(n_samples):
# ADC sign conversion: RTL does offset binary → signed 18-bit
# adc_signed_w = {1'b0, adc_data, 9'b0} - {1'b0, 8'hFF, 9'b0}/2
# Exact: (adc_val << 9) - 0xFF00, where 0xFF00 = {1'b0,8'hFF,9'b0}/2
# Simplified: center around zero, scale to 18-bit
adc_val = int(adc_samples[n])
adc_signed = (adc_val << 9) - 0xFF00 # Exact RTL: {1'b0,adc,9'b0} - {1'b0,8'hFF,9'b0}/2
adc_signed = (adc_val - 128) << 9 # Approximate RTL sign conversion to 18-bit
adc_signed = saturate(adc_signed, 18)
# NCO lookup (ignoring dithering for golden reference)
9_Firmware/9_2_FPGA/tb/cosim/rtl_bb_dc.csv
+2455 -2455
View File
File diff suppressed because it is too large Load Diff
9_Firmware/9_2_FPGA/tb/cosim/rtl_mf_chirp.csv
-1025
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9_Firmware/9_2_FPGA/tb/cosim/rtl_mf_dc.csv
-1025
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9_Firmware/9_2_FPGA/tb/cosim/rtl_mf_impulse.csv
-1025
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9_Firmware/9_2_FPGA/tb/cosim/rtl_mf_tone5.csv
-1025
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9_Firmware/9_2_FPGA/tb/cosim/rx_final_doppler_out.csv
-2049
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9_Firmware/9_2_FPGA/tb/cosim/validate_mem_files.py
+3 -3
View File
@@ -421,13 +421,13 @@ def test_latency_buffer():
#
# For synthesis: the latency_buffer feeds ref data to the chain via
# chirp_memory_loader_param → latency_buffer → chain.
# But wait — looking at radar_receiver_final.v:
# Looking at radar_receiver_final.v:
# - mem_request drives valid_in on the latency buffer
# - The buffer delays {ref_i, ref_q} by LATENCY valid_in cycles
# - The delayed output feeds long_chirp_real/imag → chain
# - The delayed output feeds ref_chirp_real/imag → chain
#
# The purpose: the chain in the SYNTHESIS branch reads reference data
# via the long_chirp_real/imag ports DURING ST_FWD_FFT (while collecting
# via the ref_chirp_real/imag ports DURING ST_FWD_FFT (while collecting
# input samples). The reference data needs to arrive LATENCY cycles
# after the first mem_request, where LATENCY accounts for:
# - The fft_engine pipeline latency from input to output
9_Firmware/9_2_FPGA/tb/golden/golden_doppler.mem
-2176
View File
File diff suppressed because it is too large Load Diff
9_Firmware/9_2_FPGA/tb/radar_system_tb.v
+1 -11
View File
@@ -430,13 +430,7 @@ end
// DUT INSTANTIATION
// ============================================================================
radar_system_top #(
`ifdef USB_MODE_1
.USB_MODE(1) // FT2232H interface (production 50T board)
`else
.USB_MODE(0) // FT601 interface (200T dev board)
`endif
) dut (
radar_system_top dut (
// System Clocks
.clk_100m(clk_100m),
.clk_120m_dac(clk_120m_dac),
@@ -625,11 +619,7 @@ initial begin
// Optional: dump specific signals for debugging
$dumpvars(1, dut.tx_inst);
$dumpvars(1, dut.rx_inst);
`ifdef USB_MODE_1
$dumpvars(1, dut.gen_ft2232h.usb_inst);
`else
$dumpvars(1, dut.gen_ft601.usb_inst);
`endif
end
endmodule
9_Firmware/9_2_FPGA/tb/tb_matched_filter_processing_chain.v
+28 -54
View File
@@ -18,10 +18,8 @@ module tb_matched_filter_processing_chain;
reg [15:0] adc_data_q;
reg adc_valid;
reg [5:0] chirp_counter;
reg [15:0] long_chirp_real;
reg [15:0] long_chirp_imag;
reg [15:0] short_chirp_real;
reg [15:0] short_chirp_imag;
reg [15:0] ref_chirp_real;
reg [15:0] ref_chirp_imag;
wire signed [15:0] range_profile_i;
wire signed [15:0] range_profile_q;
wire range_profile_valid;
@@ -83,10 +81,8 @@ module tb_matched_filter_processing_chain;
.adc_data_q (adc_data_q),
.adc_valid (adc_valid),
.chirp_counter (chirp_counter),
.long_chirp_real (long_chirp_real),
.long_chirp_imag (long_chirp_imag),
.short_chirp_real (short_chirp_real),
.short_chirp_imag (short_chirp_imag),
.ref_chirp_real (ref_chirp_real),
.ref_chirp_imag (ref_chirp_imag),
.range_profile_i (range_profile_i),
.range_profile_q (range_profile_q),
.range_profile_valid (range_profile_valid),
@@ -133,10 +129,8 @@ module tb_matched_filter_processing_chain;
adc_data_i = 16'd0;
adc_data_q = 16'd0;
chirp_counter = 6'd0;
long_chirp_real = 16'd0;
long_chirp_imag = 16'd0;
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = 16'd0;
ref_chirp_imag = 16'd0;
cap_enable = 0;
cap_count = 0;
cap_max_abs = 0;
@@ -168,10 +162,8 @@ module tb_matched_filter_processing_chain;
angle = 6.28318530718 * tone_bin * k / (1.0 * FFT_SIZE);
adc_data_i = $rtoi(8000.0 * $cos(angle));
adc_data_q = $rtoi(8000.0 * $sin(angle));
long_chirp_real = $rtoi(8000.0 * $cos(angle));
long_chirp_imag = $rtoi(8000.0 * $sin(angle));
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = $rtoi(8000.0 * $cos(angle));
ref_chirp_imag = $rtoi(8000.0 * $sin(angle));
adc_valid = 1'b1;
@(posedge clk);
#1;
@@ -187,10 +179,8 @@ module tb_matched_filter_processing_chain;
for (k = 0; k < FFT_SIZE; k = k + 1) begin
adc_data_i = 16'sh1000;
adc_data_q = 16'sh0000;
long_chirp_real = 16'sh1000;
long_chirp_imag = 16'sh0000;
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = 16'sh1000;
ref_chirp_imag = 16'sh0000;
adc_valid = 1'b1;
@(posedge clk);
#1;
@@ -233,10 +223,8 @@ module tb_matched_filter_processing_chain;
for (k = 0; k < FFT_SIZE; k = k + 1) begin
adc_data_i = gold_sig_i[k];
adc_data_q = gold_sig_q[k];
long_chirp_real = gold_ref_i[k];
long_chirp_imag = gold_ref_q[k];
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = gold_ref_i[k];
ref_chirp_imag = gold_ref_q[k];
adc_valid = 1'b1;
@(posedge clk);
#1;
@@ -374,10 +362,8 @@ module tb_matched_filter_processing_chain;
for (i = 0; i < FFT_SIZE; i = i + 1) begin
adc_data_i = 16'd0;
adc_data_q = 16'd0;
long_chirp_real = 16'd0;
long_chirp_imag = 16'd0;
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = 16'd0;
ref_chirp_imag = 16'd0;
adc_valid = 1'b1;
@(posedge clk); #1;
end
@@ -449,10 +435,8 @@ module tb_matched_filter_processing_chain;
for (i = 0; i < FFT_SIZE; i = i + 1) begin
adc_data_i = $rtoi(8000.0 * $cos(6.28318530718 * 5 * i / 1024.0));
adc_data_q = $rtoi(8000.0 * $sin(6.28318530718 * 5 * i / 1024.0));
long_chirp_real = $rtoi(8000.0 * $cos(6.28318530718 * 10 * i / 1024.0));
long_chirp_imag = $rtoi(8000.0 * $sin(6.28318530718 * 10 * i / 1024.0));
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = $rtoi(8000.0 * $cos(6.28318530718 * 10 * i / 1024.0));
ref_chirp_imag = $rtoi(8000.0 * $sin(6.28318530718 * 10 * i / 1024.0));
adc_valid = 1'b1;
@(posedge clk); #1;
end
@@ -568,10 +552,8 @@ module tb_matched_filter_processing_chain;
for (i = 0; i < FFT_SIZE; i = i + 1) begin
adc_data_i = 16'sh7FFF;
adc_data_q = 16'sh7FFF;
long_chirp_real = 16'sh7FFF;
long_chirp_imag = 16'sh7FFF;
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = 16'sh7FFF;
ref_chirp_imag = 16'sh7FFF;
adc_valid = 1'b1;
@(posedge clk); #1;
end
@@ -589,10 +571,8 @@ module tb_matched_filter_processing_chain;
for (i = 0; i < FFT_SIZE; i = i + 1) begin
adc_data_i = 16'sh8000;
adc_data_q = 16'sh8000;
long_chirp_real = 16'sh8000;
long_chirp_imag = 16'sh8000;
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = 16'sh8000;
ref_chirp_imag = 16'sh8000;
adc_valid = 1'b1;
@(posedge clk); #1;
end
@@ -611,16 +591,14 @@ module tb_matched_filter_processing_chain;
if (i % 2 == 0) begin
adc_data_i = 16'sh7FFF;
adc_data_q = 16'sh7FFF;
long_chirp_real = 16'sh7FFF;
long_chirp_imag = 16'sh7FFF;
ref_chirp_real = 16'sh7FFF;
ref_chirp_imag = 16'sh7FFF;
end else begin
adc_data_i = 16'sh8000;
adc_data_q = 16'sh8000;
long_chirp_real = 16'sh8000;
long_chirp_imag = 16'sh8000;
ref_chirp_real = 16'sh8000;
ref_chirp_imag = 16'sh8000;
end
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
adc_valid = 1'b1;
@(posedge clk); #1;
end
@@ -641,10 +619,8 @@ module tb_matched_filter_processing_chain;
for (i = 0; i < 512; i = i + 1) begin
adc_data_i = 16'sh1000;
adc_data_q = 16'sh0000;
long_chirp_real = 16'sh1000;
long_chirp_imag = 16'sh0000;
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = 16'sh1000;
ref_chirp_imag = 16'sh0000;
adc_valid = 1'b1;
@(posedge clk); #1;
end
@@ -683,10 +659,8 @@ module tb_matched_filter_processing_chain;
for (i = 0; i < FFT_SIZE; i = i + 1) begin
adc_data_i = 16'sh1000;
adc_data_q = 16'sh0000;
long_chirp_real = 16'sh1000;
long_chirp_imag = 16'sh0000;
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = 16'sh1000;
ref_chirp_imag = 16'sh0000;
adc_valid = 1'b1;
@(posedge clk); #1;
9_Firmware/9_2_FPGA/tb/tb_mf_chain_synth.v
+24 -46
View File
@@ -28,10 +28,8 @@ module tb_mf_chain_synth;
reg [15:0] adc_data_q;
reg adc_valid;
reg [5:0] chirp_counter;
reg [15:0] long_chirp_real;
reg [15:0] long_chirp_imag;
reg [15:0] short_chirp_real;
reg [15:0] short_chirp_imag;
reg [15:0] ref_chirp_real;
reg [15:0] ref_chirp_imag;
wire signed [15:0] range_profile_i;
wire signed [15:0] range_profile_q;
wire range_profile_valid;
@@ -78,10 +76,8 @@ module tb_mf_chain_synth;
.adc_data_q (adc_data_q),
.adc_valid (adc_valid),
.chirp_counter (chirp_counter),
.long_chirp_real (long_chirp_real),
.long_chirp_imag (long_chirp_imag),
.short_chirp_real (short_chirp_real),
.short_chirp_imag (short_chirp_imag),
.ref_chirp_real (ref_chirp_real),
.ref_chirp_imag (ref_chirp_imag),
.range_profile_i (range_profile_i),
.range_profile_q (range_profile_q),
.range_profile_valid (range_profile_valid),
@@ -130,10 +126,8 @@ module tb_mf_chain_synth;
adc_data_i = 16'd0;
adc_data_q = 16'd0;
chirp_counter = 6'd0;
long_chirp_real = 16'd0;
long_chirp_imag = 16'd0;
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = 16'd0;
ref_chirp_imag = 16'd0;
cap_enable = 0;
cap_count = 0;
cap_max_abs = 0;
@@ -177,10 +171,8 @@ module tb_mf_chain_synth;
for (k = 0; k < FFT_SIZE; k = k + 1) begin
adc_data_i = 16'sh1000; // +4096
adc_data_q = 16'sh0000;
long_chirp_real = 16'sh1000;
long_chirp_imag = 16'sh0000;
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = 16'sh1000;
ref_chirp_imag = 16'sh0000;
adc_valid = 1'b1;
@(posedge clk);
#1;
@@ -199,10 +191,8 @@ module tb_mf_chain_synth;
angle = 6.28318530718 * tone_bin * k / (1.0 * FFT_SIZE);
adc_data_i = $rtoi(8000.0 * $cos(angle));
adc_data_q = $rtoi(8000.0 * $sin(angle));
long_chirp_real = $rtoi(8000.0 * $cos(angle));
long_chirp_imag = $rtoi(8000.0 * $sin(angle));
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = $rtoi(8000.0 * $cos(angle));
ref_chirp_imag = $rtoi(8000.0 * $sin(angle));
adc_valid = 1'b1;
@(posedge clk);
#1;
@@ -219,16 +209,14 @@ module tb_mf_chain_synth;
if (k == 0) begin
adc_data_i = 16'sh4000; // 0.5 in Q15
adc_data_q = 16'sh0000;
long_chirp_real = 16'sh4000;
long_chirp_imag = 16'sh0000;
ref_chirp_real = 16'sh4000;
ref_chirp_imag = 16'sh0000;
end else begin
adc_data_i = 16'sh0000;
adc_data_q = 16'sh0000;
long_chirp_real = 16'sh0000;
long_chirp_imag = 16'sh0000;
ref_chirp_real = 16'sh0000;
ref_chirp_imag = 16'sh0000;
end
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
adc_valid = 1'b1;
@(posedge clk);
#1;
@@ -309,10 +297,8 @@ module tb_mf_chain_synth;
for (i = 0; i < FFT_SIZE; i = i + 1) begin
adc_data_i = 16'd0;
adc_data_q = 16'd0;
long_chirp_real = 16'd0;
long_chirp_imag = 16'd0;
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = 16'd0;
ref_chirp_imag = 16'd0;
adc_valid = 1'b1;
@(posedge clk); #1;
end
@@ -379,10 +365,8 @@ module tb_mf_chain_synth;
for (i = 0; i < 512; i = i + 1) begin
adc_data_i = 16'sh1000;
adc_data_q = 16'sh0000;
long_chirp_real = 16'sh1000;
long_chirp_imag = 16'sh0000;
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = 16'sh1000;
ref_chirp_imag = 16'sh0000;
adc_valid = 1'b1;
@(posedge clk); #1;
end
@@ -439,10 +423,8 @@ module tb_mf_chain_synth;
for (i = 0; i < FFT_SIZE; i = i + 1) begin
adc_data_i = $rtoi(8000.0 * $cos(6.28318530718 * 5 * i / 1024.0));
adc_data_q = $rtoi(8000.0 * $sin(6.28318530718 * 5 * i / 1024.0));
long_chirp_real = $rtoi(8000.0 * $cos(6.28318530718 * 10 * i / 1024.0));
long_chirp_imag = $rtoi(8000.0 * $sin(6.28318530718 * 10 * i / 1024.0));
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = $rtoi(8000.0 * $cos(6.28318530718 * 10 * i / 1024.0));
ref_chirp_imag = $rtoi(8000.0 * $sin(6.28318530718 * 10 * i / 1024.0));
adc_valid = 1'b1;
@(posedge clk); #1;
end
@@ -469,10 +451,8 @@ module tb_mf_chain_synth;
for (i = 0; i < FFT_SIZE; i = i + 1) begin
adc_data_i = 16'sh7FFF;
adc_data_q = 16'sh7FFF;
long_chirp_real = 16'sh7FFF;
long_chirp_imag = 16'sh7FFF;
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = 16'sh7FFF;
ref_chirp_imag = 16'sh7FFF;
adc_valid = 1'b1;
@(posedge clk); #1;
end
@@ -495,10 +475,8 @@ module tb_mf_chain_synth;
for (i = 0; i < FFT_SIZE; i = i + 1) begin
adc_data_i = 16'sh1000;
adc_data_q = 16'sh0000;
long_chirp_real = 16'sh1000;
long_chirp_imag = 16'sh0000;
short_chirp_real = 16'd0;
short_chirp_imag = 16'd0;
ref_chirp_real = 16'sh1000;
ref_chirp_imag = 16'sh0000;
adc_valid = 1'b1;
@(posedge clk); #1;
9_Firmware/9_2_FPGA/tb/tb_mf_cosim.v
+10 -18
View File
@@ -88,10 +88,8 @@ reg [15:0] adc_data_i;
reg [15:0] adc_data_q;
reg adc_valid;
reg [5:0] chirp_counter;
reg [15:0] long_chirp_real;
reg [15:0] long_chirp_imag;
reg [15:0] short_chirp_real;
reg [15:0] short_chirp_imag;
reg [15:0] ref_chirp_real;
reg [15:0] ref_chirp_imag;
wire signed [15:0] range_profile_i;
wire signed [15:0] range_profile_q;
@@ -108,10 +106,8 @@ matched_filter_processing_chain dut (
.adc_data_q(adc_data_q),
.adc_valid(adc_valid),
.chirp_counter(chirp_counter),
.long_chirp_real(long_chirp_real),
.long_chirp_imag(long_chirp_imag),
.short_chirp_real(short_chirp_real),
.short_chirp_imag(short_chirp_imag),
.ref_chirp_real(ref_chirp_real),
.ref_chirp_imag(ref_chirp_imag),
.range_profile_i(range_profile_i),
.range_profile_q(range_profile_q),
.range_profile_valid(range_profile_valid),
@@ -157,10 +153,8 @@ task apply_reset;
adc_data_q <= 16'd0;
adc_valid <= 1'b0;
chirp_counter <= 6'd0;
long_chirp_real <= 16'd0;
long_chirp_imag <= 16'd0;
short_chirp_real <= 16'd0;
short_chirp_imag <= 16'd0;
ref_chirp_real <= 16'd0;
ref_chirp_imag <= 16'd0;
repeat(4) @(posedge clk);
reset_n <= 1'b1;
@(posedge clk);
@@ -201,18 +195,16 @@ initial begin
@(posedge clk);
adc_data_i <= sig_mem_i[i];
adc_data_q <= sig_mem_q[i];
long_chirp_real <= ref_mem_i[i];
long_chirp_imag <= ref_mem_q[i];
short_chirp_real <= 16'd0;
short_chirp_imag <= 16'd0;
ref_chirp_real <= ref_mem_i[i];
ref_chirp_imag <= ref_mem_q[i];
adc_valid <= 1'b1;
end
@(posedge clk);
adc_valid <= 1'b0;
adc_data_i <= 16'd0;
adc_data_q <= 16'd0;
long_chirp_real <= 16'd0;
long_chirp_imag <= 16'd0;
ref_chirp_real <= 16'd0;
ref_chirp_imag <= 16'd0;
$display("All samples fed. Waiting for processing...");
9_Firmware/9_2_FPGA/tb/tb_multiseg_cosim.v
+10 -16
View File
@@ -56,10 +56,8 @@ reg [5:0] chirp_counter;
reg mc_new_chirp;
reg mc_new_elevation;
reg mc_new_azimuth;
reg [15:0] long_chirp_real;
reg [15:0] long_chirp_imag;
reg [15:0] short_chirp_real;
reg [15:0] short_chirp_imag;
reg [15:0] ref_chirp_real;
reg [15:0] ref_chirp_imag;
reg mem_ready;
wire signed [15:0] pc_i_w;
@@ -84,10 +82,8 @@ matched_filter_multi_segment dut (
.mc_new_chirp(mc_new_chirp),
.mc_new_elevation(mc_new_elevation),
.mc_new_azimuth(mc_new_azimuth),
.long_chirp_real(long_chirp_real),
.long_chirp_imag(long_chirp_imag),
.short_chirp_real(short_chirp_real),
.short_chirp_imag(short_chirp_imag),
.ref_chirp_real(ref_chirp_real),
.ref_chirp_imag(ref_chirp_imag),
.segment_request(segment_request),
.sample_addr_out(sample_addr_out),
.mem_request(mem_request),
@@ -123,11 +119,11 @@ end
always @(posedge clk) begin
if (mem_request) begin
if (use_long_chirp) begin
long_chirp_real <= ref_mem_i[{segment_request, sample_addr_out}];
long_chirp_imag <= ref_mem_q[{segment_request, sample_addr_out}];
ref_chirp_real <= ref_mem_i[{segment_request, sample_addr_out}];
ref_chirp_imag <= ref_mem_q[{segment_request, sample_addr_out}];
end else begin
short_chirp_real <= ref_mem_i[sample_addr_out];
short_chirp_imag <= ref_mem_q[sample_addr_out];
ref_chirp_real <= ref_mem_i[sample_addr_out];
ref_chirp_imag <= ref_mem_q[sample_addr_out];
end
mem_ready <= 1'b1;
end else begin
@@ -176,10 +172,8 @@ task apply_reset;
mc_new_chirp <= 1'b0;
mc_new_elevation <= 1'b0;
mc_new_azimuth <= 1'b0;
long_chirp_real <= 16'd0;
long_chirp_imag <= 16'd0;
short_chirp_real <= 16'd0;
short_chirp_imag <= 16'd0;
ref_chirp_real <= 16'd0;
ref_chirp_imag <= 16'd0;
mem_ready <= 1'b0;
repeat(10) @(posedge clk);
reset_n <= 1'b1;
9_Firmware/9_2_FPGA/tb/tb_radar_receiver_final.v
+8 -176
View File
@@ -7,43 +7,21 @@
// -> matched_filter_multi_segment -> range_bin_decimator
// -> doppler_processor_optimized -> doppler_output
//
// ============================================================================
// TWO MODES (compile-time define):
//
// 1. GOLDEN_GENERATE mode (-DGOLDEN_GENERATE):
// Dumps all Doppler output samples to golden reference files.
// Run once on known-good RTL:
// iverilog -g2001 -DSIMULATION -DGOLDEN_GENERATE -o tb_golden_gen.vvp \
// <src files> tb/tb_radar_receiver_final.v
// mkdir -p tb/golden
// vvp tb_golden_gen.vvp
//
// 2. Default mode (no GOLDEN_GENERATE):
// Loads golden files, compares each Doppler output against reference,
// and runs physics-based bounds checks.
// iverilog -g2001 -DSIMULATION -o tb_radar_receiver_final.vvp \
// <src files> tb/tb_radar_receiver_final.v
// vvp tb_radar_receiver_final.vvp
//
// PREREQUISITES:
// - The directory tb/golden/ must exist before running either mode.
// Create it with: mkdir -p tb/golden
//
// TAP POINTS:
// Tap 1 (DDC output) - bounds checking only (CDC jitter -> non-deterministic)
// Signals: dut.ddc_out_i [17:0], dut.ddc_out_q [17:0], dut.ddc_valid_i
// Tap 2 (Doppler output) - golden compared (deterministic after MF buffering)
// Tap 2 (Doppler output) - structural + bounds checks (deterministic after MF)
// Signals: doppler_output[31:0], doppler_valid, doppler_bin[4:0],
// range_bin_out[5:0]
//
// Golden file: tb/golden/golden_doppler.mem
// 2048 entries of 32-bit hex, indexed by range_bin*32 + doppler_bin
//
// Strategy:
// - Uses behavioral stub for ad9484_interface_400m (no Xilinx primitives)
// - Overrides radar_mode_controller timing params for fast simulation
// - Feeds 120 MHz tone at ADC input (IF frequency -> DDC passband)
// - Verifies structural correctness + golden comparison + bounds checks
// - Verifies structural correctness (S1-S10) + physics bounds checks (B1-B5)
// - Bit-accurate golden comparison is done by the MF co-sim tests
// (tb_mf_cosim.v + compare_mf.py) and full-chain co-sim tests
// (tb_doppler_realdata.v, tb_fullchain_realdata.v), not here.
//
// Convention: check task, VCD dump, CSV output, pass/fail summary
// ============================================================================
@@ -96,31 +74,15 @@ end
reg [5:0] chirp_counter;
reg mc_new_chirp_prev;
// Frame-start pulse: mirrors the real transmitter's new_chirp_frame signal.
// In the real system this fires on IDLE→LONG_CHIRP transitions in the chirp
// controller. Here we derive it from the mode controller's chirp_count
// wrapping back to 0 (which wraps correctly at cfg_chirps_per_elev).
reg tx_frame_start;
reg [5:0] rmc_chirp_prev;
always @(posedge clk_100m or negedge reset_n) begin
if (!reset_n) begin
chirp_counter <= 6'd0;
mc_new_chirp_prev <= 1'b0;
tx_frame_start <= 1'b0;
rmc_chirp_prev <= 6'd0;
end else begin
mc_new_chirp_prev <= dut.mc_new_chirp;
if (dut.mc_new_chirp != mc_new_chirp_prev) begin
chirp_counter <= chirp_counter + 1;
end
// Detect when the internal mode controller's chirp_count wraps to 0
tx_frame_start <= 1'b0;
if (dut.rmc_chirp_count == 6'd0 && rmc_chirp_prev != 6'd0) begin
tx_frame_start <= 1'b1;
end
rmc_chirp_prev <= dut.rmc_chirp_count;
end
end
@@ -144,7 +106,6 @@ radar_receiver_final dut (
.adc_pwdn(),
.chirp_counter(chirp_counter),
.tx_frame_start(tx_frame_start),
.doppler_output(doppler_output),
.doppler_valid(doppler_valid),
@@ -211,46 +172,6 @@ task check;
end
endtask
// ============================================================================
// GOLDEN MEMORY DECLARATIONS AND LOAD/STORE LOGIC
// ============================================================================
localparam GOLDEN_ENTRIES = 2048; // 64 range bins * 32 Doppler bins
localparam GOLDEN_TOLERANCE = 2; // +/- 2 LSB tolerance for comparison
reg [31:0] golden_doppler [0:2047];
// -- Golden comparison tracking --
integer golden_match_count;
integer golden_mismatch_count;
integer golden_max_err_i;
integer golden_max_err_q;
integer golden_compare_count;
`ifdef GOLDEN_GENERATE
// In generate mode, we just initialize the array to X/0
// and fill it as outputs arrive
integer gi;
initial begin
for (gi = 0; gi < GOLDEN_ENTRIES; gi = gi + 1)
golden_doppler[gi] = 32'd0;
golden_match_count = 0;
golden_mismatch_count = 0;
golden_max_err_i = 0;
golden_max_err_q = 0;
golden_compare_count = 0;
end
`else
// In comparison mode, load the golden reference
initial begin
$readmemh("tb/golden/golden_doppler.mem", golden_doppler);
golden_match_count = 0;
golden_mismatch_count = 0;
golden_max_err_i = 0;
golden_max_err_q = 0;
golden_compare_count = 0;
end
`endif
// ============================================================================
// DDC ENERGY ACCUMULATOR (Bounds Check B1)
// ============================================================================
@@ -274,7 +195,7 @@ always @(posedge clk_100m) begin
end
// ============================================================================
// DOPPLER OUTPUT CAPTURE, GOLDEN COMPARISON, AND DUPLICATE DETECTION
// DOPPLER OUTPUT CAPTURE AND DUPLICATE DETECTION
// ============================================================================
integer doppler_output_count;
integer doppler_frame_count;
@@ -328,13 +249,6 @@ end
// Monitor doppler outputs -- only after reset released
always @(posedge clk_100m) begin
if (reset_n && doppler_valid) begin : doppler_capture_block
// ---- Signed intermediates for golden comparison ----
reg signed [16:0] actual_i, actual_q;
reg signed [16:0] expected_i, expected_q;
reg signed [16:0] err_i_signed, err_q_signed;
integer abs_err_i, abs_err_q;
integer gidx;
reg [31:0] expected_val;
// ---- Magnitude intermediates for B2 ----
reg signed [16:0] mag_i_signed, mag_q_signed;
integer mag_i, mag_q, mag_sum;
@@ -367,9 +281,6 @@ always @(posedge clk_100m) begin
if ((doppler_output_count % 256) == 0)
$display("[INFO] %0d doppler outputs so far (t=%0t)", doppler_output_count, $time);
// ---- Golden index computation ----
gidx = range_bin_out * 32 + doppler_bin;
// ---- Duplicate detection (B5) ----
if (range_bin_out < 64 && doppler_bin < 32) begin
if (index_seen[range_bin_out][doppler_bin]) begin
@@ -393,44 +304,6 @@ always @(posedge clk_100m) begin
if (mag_sum > peak_dbin_mag[range_bin_out])
peak_dbin_mag[range_bin_out] = mag_sum;
end
`ifdef GOLDEN_GENERATE
// ---- GOLDEN GENERATE: store output ----
if (gidx < GOLDEN_ENTRIES)
golden_doppler[gidx] = doppler_output;
`else
// ---- GOLDEN COMPARE: check against reference ----
if (gidx < GOLDEN_ENTRIES) begin
expected_val = golden_doppler[gidx];
actual_i = $signed(doppler_output[15:0]);
actual_q = $signed(doppler_output[31:16]);
expected_i = $signed(expected_val[15:0]);
expected_q = $signed(expected_val[31:16]);
err_i_signed = actual_i - expected_i;
err_q_signed = actual_q - expected_q;
abs_err_i = (err_i_signed < 0) ? -err_i_signed : err_i_signed;
abs_err_q = (err_q_signed < 0) ? -err_q_signed : err_q_signed;
golden_compare_count = golden_compare_count + 1;
if (abs_err_i > golden_max_err_i) golden_max_err_i = abs_err_i;
if (abs_err_q > golden_max_err_q) golden_max_err_q = abs_err_q;
if (abs_err_i <= GOLDEN_TOLERANCE && abs_err_q <= GOLDEN_TOLERANCE) begin
golden_match_count = golden_match_count + 1;
end else begin
golden_mismatch_count = golden_mismatch_count + 1;
if (golden_mismatch_count <= 20)
$display("[MISMATCH] idx=%0d rbin=%0d dbin=%0d actual=%08h expected=%08h err_i=%0d err_q=%0d",
gidx, range_bin_out, doppler_bin,
doppler_output, expected_val,
abs_err_i, abs_err_q);
end
end
`endif
end
// Track frame completions via doppler_proc -- only after reset
@@ -573,13 +446,6 @@ initial begin
end
end
// ---- DUMP GOLDEN FILE (generate mode only) ----
`ifdef GOLDEN_GENERATE
$writememh("tb/golden/golden_doppler.mem", golden_doppler);
$display("[GOLDEN_GENERATE] Wrote tb/golden/golden_doppler.mem (%0d entries captured)",
doppler_output_count);
`endif
// ================================================================
// RUN CHECKS
// ================================================================
@@ -666,33 +532,7 @@ initial begin
"S10: DDC produced substantial output (>100 valid samples)");
// ================================================================
// GOLDEN COMPARISON REPORT
// ================================================================
`ifdef GOLDEN_GENERATE
$display("");
$display("Golden comparison: SKIPPED (GOLDEN_GENERATE mode)");
$display(" Wrote golden reference with %0d Doppler samples", doppler_output_count);
`else
$display("");
$display("------------------------------------------------------------");
$display("GOLDEN COMPARISON (tolerance=%0d LSB)", GOLDEN_TOLERANCE);
$display("------------------------------------------------------------");
$display("Golden comparison: %0d/%0d match (tolerance=%0d LSB)",
golden_match_count, golden_compare_count, GOLDEN_TOLERANCE);
$display(" Mismatches: %0d (I-ch max_err=%0d, Q-ch max_err=%0d)",
golden_mismatch_count, golden_max_err_i, golden_max_err_q);
// CHECK G1: All golden comparisons match
if (golden_compare_count > 0) begin
check(golden_mismatch_count == 0,
"G1: All Doppler outputs match golden reference within tolerance");
end else begin
check(0, "G1: All Doppler outputs match golden reference (NO COMPARISONS)");
end
`endif
// ================================================================
// BOUNDS CHECKS (active in both modes)
// BOUNDS CHECKS
// ================================================================
$display("");
$display("------------------------------------------------------------");
@@ -765,16 +605,8 @@ initial begin
// ================================================================
$display("");
$display("============================================================");
$display("INTEGRATION TEST -- GOLDEN COMPARISON + BOUNDS");
$display("INTEGRATION TEST -- STRUCTURAL + BOUNDS");
$display("============================================================");
`ifdef GOLDEN_GENERATE
$display("Mode: GOLDEN_GENERATE (reference dump, comparison skipped)");
`else
$display("Golden comparison: %0d/%0d match (tolerance=%0d LSB)",
golden_match_count, golden_compare_count, GOLDEN_TOLERANCE);
$display(" Mismatches: %0d (I-ch max_err=%0d, Q-ch max_err=%0d)",
golden_mismatch_count, golden_max_err_i, golden_max_err_q);
`endif
$display("Bounds checks:");
$display(" B1: DDC RMS energy in range [%0d, %0d]",
(ddc_energy_acc > 0) ? 1 : 0, DDC_MAX_ENERGY);
9_Firmware/9_2_FPGA/tb/tb_system_e2e.v
+8 -14
View File
@@ -382,13 +382,7 @@ end
// ============================================================================
// DUT INSTANTIATION
// ============================================================================
radar_system_top #(
`ifdef USB_MODE_1
.USB_MODE(1) // FT2232H interface (production 50T board)
`else
.USB_MODE(0) // FT601 interface (200T dev board)
`endif
) dut (
radar_system_top dut (
.clk_100m(clk_100m),
.clk_120m_dac(clk_120m_dac),
.ft601_clk_in(ft601_clk_in),
@@ -560,10 +554,10 @@ initial begin
do_reset;
// CRITICAL: Configure stream control to range-only BEFORE any chirps
// fire. The USB write FSM gates on pending flags: if doppler stream is
// enabled but no Doppler data arrives (needs 32 chirps/frame), the FSM
// stays in IDLE waiting for doppler_data_pending. With the write FSM
// not in IDLE, the read FSM cannot activate (bus arbitration rule).
// fire. The USB write FSM blocks on doppler_valid_ft if doppler stream
// is enabled but no Doppler data arrives (needs 32 chirps/frame).
// Without this, the write FSM deadlocks and the read FSM can never
// activate (it requires write FSM == IDLE).
bfm_send_cmd(8'h04, 8'h00, 16'h0001); // stream_control = range only
// Wait for stream_control CDC to propagate (2-stage sync in ft601_clk)
// Must be long enough that stream_ctrl_sync_1 is updated before any
@@ -784,7 +778,7 @@ initial begin
// Restore defaults for subsequent tests
bfm_send_cmd(8'h01, 8'h00, 16'h0001); // mode = auto-scan
bfm_send_cmd(8'h04, 8'h00, 16'h0001); // keep range-only (TB lacks 32-chirp doppler data)
bfm_send_cmd(8'h04, 8'h00, 16'h0001); // keep range-only (prevents write FSM deadlock)
bfm_send_cmd(8'h10, 8'h00, 16'd3000); // restore long chirp cycles
$display("");
@@ -919,7 +913,7 @@ initial begin
// Need to re-send configuration since reset clears all registers
stm32_mixers_enable = 1;
ft601_txe = 0;
bfm_send_cmd(8'h04, 8'h00, 16'h0001); // stream_control = range only (TB lacks doppler data)
bfm_send_cmd(8'h04, 8'h00, 16'h0001); // stream_control = range only (prevent deadlock)
#500; // Wait for stream_control CDC
bfm_send_cmd(8'h01, 8'h00, 16'h0001); // auto-scan
bfm_send_cmd(8'h10, 8'h00, 16'd100); // short timing
@@ -953,7 +947,7 @@ initial begin
check(dut.host_stream_control == 3'b000,
"G10.2: All streams disabled (stream_control = 3'b000)");
// G10.3: Re-enable range only (TB uses range-only — no doppler processing)
// G10.3: Re-enable range only (keep range-only to prevent write FSM deadlock)
bfm_send_cmd(8'h04, 8'h00, 16'h0001); // stream_control = 3'b001
check(dut.host_stream_control == 3'b001,
"G10.3: Range stream re-enabled (stream_control = 3'b001)");
9_Firmware/9_2_FPGA/tb/tb_usb_data_interface.v
+207 -177
View File
@@ -6,11 +6,15 @@ module tb_usb_data_interface;
localparam CLK_PERIOD = 10.0; // 100 MHz main clock
localparam FT_CLK_PERIOD = 10.0; // 100 MHz FT601 clock (asynchronous)
// State definitions (mirror the DUT — 4-state packed-word FSM)
localparam [3:0] S_IDLE = 4'd0,
S_SEND_DATA_WORD = 4'd1,
S_SEND_STATUS = 4'd2,
S_WAIT_ACK = 4'd3;
// State definitions (mirror the DUT)
localparam [2:0] S_IDLE = 3'd0,
S_SEND_HEADER = 3'd1,
S_SEND_RANGE = 3'd2,
S_SEND_DOPPLER = 3'd3,
S_SEND_DETECT = 3'd4,
S_SEND_FOOTER = 3'd5,
S_WAIT_ACK = 3'd6,
S_SEND_STATUS = 3'd7; // Gap 2: status readback
// ── Signals ────────────────────────────────────────────────
reg clk;
@@ -215,9 +219,9 @@ module tb_usb_data_interface;
end
endtask
// ── Helper: wait for DUT to reach a specific write FSM state ──
// ── Helper: wait for DUT to reach a specific state ─────────
task wait_for_state;
input [3:0] target;
input [2:0] target;
input integer max_cyc;
integer cnt;
begin
@@ -276,7 +280,7 @@ module tb_usb_data_interface;
// Set data_pending flags directly via hierarchical access.
// This is the standard TB technique for internal state setup —
// bypasses the CDC path for immediate, reliable flag setting.
// Call BEFORE assert_range_valid in tests that need doppler/cfar data.
// Call BEFORE assert_range_valid in tests that need SEND_DOPPLER/DETECT.
task preload_pending_data;
begin
@(posedge ft601_clk_in);
@@ -350,26 +354,24 @@ module tb_usb_data_interface;
end
endtask
// Drive a complete data packet through the new 3-word packed FSM.
// Pre-loads pending flags, triggers range_valid, and waits for IDLE.
// With the new FSM, all data is pre-packed in IDLE then sent as 3 words.
// Drive a complete packet through the FSM by sequentially providing
// range, doppler (4x), and cfar valid pulses.
task drive_full_packet;
input [31:0] rng;
input [15:0] dr;
input [15:0] di;
input det;
begin
// Set doppler/cfar captured values via CDC inputs
@(posedge clk);
doppler_real = dr;
doppler_imag = di;
cfar_detection = det;
@(posedge clk);
// Pre-load pending flags so FSM includes doppler/cfar in packet
// Pre-load pending flags so FSM enters doppler/cfar states
preload_pending_data;
// Trigger the packet
assert_range_valid(rng);
// Wait for complete packet cycle: IDLE → SEND_DATA_WORD(×3) → WAIT_ACK → IDLE
wait_for_state(S_SEND_DOPPLER, 100);
pulse_doppler_once(dr, di);
pulse_doppler_once(dr, di);
pulse_doppler_once(dr, di);
pulse_doppler_once(dr, di);
wait_for_state(S_SEND_DETECT, 100);
pulse_cfar_once(det);
wait_for_state(S_IDLE, 100);
end
endtask
@@ -412,138 +414,101 @@ module tb_usb_data_interface;
"ft601_siwu_n=1 after reset");
// ════════════════════════════════════════════════════════
// TEST GROUP 2: Data packet word packing
// TEST GROUP 2: Range data packet
//
// New FSM packs 11-byte data into 3 × 32-bit words:
// Word 0: {HEADER, range[31:24], range[23:16], range[15:8]}
// Word 1: {range[7:0], dop_re_hi, dop_re_lo, dop_im_hi}
// Word 2: {dop_im_lo, detection, FOOTER, 0x00} BE=1110
//
// The DUT uses range_data_ready (1-cycle delayed range_valid_ft)
// to trigger packing. Doppler/CFAR _cap registers must be
// pre-loaded via hierarchical access because no valid pulse is
// given in this test (we only want to verify packing, not CDC).
// Use backpressure to freeze the FSM at specific states
// so we can reliably sample outputs.
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 2: Data Packet Word Packing ---");
$display("\n--- Test Group 2: Range Data Packet ---");
apply_reset;
ft601_txe = 1; // Stall so we can inspect packed words
// Set known doppler/cfar values on clk-domain inputs
@(posedge clk);
doppler_real = 16'hABCD;
doppler_imag = 16'hEF01;
cfar_detection = 1'b1;
@(posedge clk);
// Pre-load pending flags AND captured-data registers directly.
// No doppler/cfar valid pulses are given, so the CDC capture path
// never fires — we must set the _cap registers via hierarchical
// access for the word-packing checks to be meaningful.
// Stall at SEND_HEADER so we can verify first range word later
ft601_txe = 1;
preload_pending_data;
@(posedge ft601_clk_in);
uut.doppler_real_cap = 16'hABCD;
uut.doppler_imag_cap = 16'hEF01;
uut.cfar_detection_cap = 1'b1;
@(posedge ft601_clk_in);
assert_range_valid(32'hDEAD_BEEF);
// FSM should be in SEND_DATA_WORD, stalled on ft601_txe=1
wait_for_state(S_SEND_DATA_WORD, 50);
wait_for_state(S_SEND_HEADER, 50);
repeat (2) @(posedge ft601_clk_in); #1;
check(uut.current_state === S_SEND_HEADER,
"Stalled in SEND_HEADER (backpressure)");
check(uut.current_state === S_SEND_DATA_WORD,
"Stalled in SEND_DATA_WORD (backpressure)");
// Verify pre-packed words
// range_profile = 0xDEAD_BEEF → range[31:24]=0xDE, [23:16]=0xAD, [15:8]=0xBE, [7:0]=0xEF
// Word 0: {0xAA, 0xDE, 0xAD, 0xBE}
check(uut.data_pkt_word0 === {8'hAA, 8'hDE, 8'hAD, 8'hBE},
"Word 0: {HEADER=AA, range[31:8]}");
// Word 1: {0xEF, 0xAB, 0xCD, 0xEF}
check(uut.data_pkt_word1 === {8'hEF, 8'hAB, 8'hCD, 8'hEF},
"Word 1: {range[7:0], dop_re, dop_im_hi}");
// Word 2: {0x01, detection_byte, 0x55, 0x00}
// detection_byte bit 7 = frame_start (sample_counter==0 → 1), bit 0 = cfar=1
// so detection_byte = 8'b1000_0001 = 8'h81
check(uut.data_pkt_word2 === {8'h01, 8'h81, 8'h55, 8'h00},
"Word 2: {dop_im_lo, det=81, FOOTER=55, pad=00}");
check(uut.data_pkt_be2 === 4'b1110,
"Word 2 BE=1110 (3 valid bytes + 1 pad)");
// Release backpressure and verify word 0 appears on bus.
// On the first posedge with !ft601_txe the FSM drives word 0 and
// advances data_word_idx 0→1 via NBA. After #1 the NBA has
// resolved, so we see idx=1 and ft601_data_out=word0.
// Release: FSM drives header then moves to SEND_RANGE_DATA
ft601_txe = 0;
@(posedge ft601_clk_in); #1;
// Now the FSM registered the header output and will transition
// At the NEXT posedge the state becomes SEND_RANGE_DATA
@(posedge ft601_clk_in); #1;
check(uut.current_state === S_SEND_RANGE,
"Entered SEND_RANGE_DATA after header");
// The first range word should be on the data bus (byte_counter=0 just
// drove range_profile_cap, byte_counter incremented to 1)
check(uut.ft601_data_out === 32'hDEAD_BEEF || uut.byte_counter <= 8'd1,
"Range data word 0 driven (range_profile_cap)");
check(uut.ft601_data_out === {8'hAA, 8'hDE, 8'hAD, 8'hBE},
"Word 0 driven on data bus after backpressure release");
check(ft601_wr_n === 1'b0,
"Write strobe active during SEND_DATA_WORD");
"Write strobe active during range data");
check(ft601_be === 4'b1111,
"Byte enable=1111 for word 0");
check(uut.ft601_data_oe === 1'b1,
"Data bus output enabled during SEND_DATA_WORD");
"Byte enable=1111 for range data");
// Next posedge: FSM drives word 1, advances idx 1→2.
// After NBA: idx=2, ft601_data_out=word1.
@(posedge ft601_clk_in); #1;
check(uut.data_word_idx === 2'd2,
"data_word_idx advanced past word 1 (now 2)");
check(uut.ft601_data_out === {8'hEF, 8'hAB, 8'hCD, 8'hEF},
"Word 1 driven on data bus");
check(ft601_be === 4'b1111,
"Byte enable=1111 for word 1");
// Next posedge: FSM drives word 2, idx resets 2→0,
// and current_state transitions to WAIT_ACK.
@(posedge ft601_clk_in); #1;
check(uut.current_state === S_WAIT_ACK,
"Transitioned to WAIT_ACK after 3 data words");
check(uut.ft601_data_out === {8'h01, 8'h81, 8'h55, 8'h00},
"Word 2 driven on data bus");
check(ft601_be === 4'b1110,
"Byte enable=1110 for word 2 (last byte is pad)");
// Then back to IDLE
@(posedge ft601_clk_in); #1;
check(uut.current_state === S_IDLE,
"Returned to IDLE after WAIT_ACK");
// Wait for all 4 range words to complete
wait_for_state(S_SEND_DOPPLER, 50);
#1;
check(uut.current_state === S_SEND_DOPPLER,
"Advanced to SEND_DOPPLER_DATA after 4 range words");
// ════════════════════════════════════════════════════════
// TEST GROUP 3: Header and footer verification
// TEST GROUP 3: Header verification (stall to observe)
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 3: Header and Footer Verification ---");
$display("\n--- Test Group 3: Header Verification ---");
apply_reset;
ft601_txe = 1; // Stall to inspect
ft601_txe = 1; // Stall at SEND_HEADER
@(posedge clk);
doppler_real = 16'h0000;
doppler_imag = 16'h0000;
cfar_detection = 1'b0;
range_profile = 32'hCAFE_BABE;
range_valid = 1;
repeat (4) @(posedge ft601_clk_in);
@(posedge clk);
preload_pending_data;
assert_range_valid(32'hCAFE_BABE);
range_valid = 0;
repeat (3) @(posedge ft601_clk_in);
wait_for_state(S_SEND_DATA_WORD, 50);
wait_for_state(S_SEND_HEADER, 50);
repeat (2) @(posedge ft601_clk_in); #1;
// Header is in byte 3 (MSB) of word 0
check(uut.data_pkt_word0[31:24] === 8'hAA,
"Header byte 0xAA in word 0 MSB");
// Footer is in byte 1 (bits [15:8]) of word 2
check(uut.data_pkt_word2[15:8] === 8'h55,
"Footer byte 0x55 in word 2");
check(uut.current_state === S_SEND_HEADER,
"Stalled in SEND_HEADER with backpressure");
// Release backpressure - header will be latched at next posedge
ft601_txe = 0;
@(posedge ft601_clk_in); #1;
check(uut.ft601_data_out[7:0] === 8'hAA,
"Header byte 0xAA on data bus");
check(ft601_be === 4'b0001,
"Byte enable=0001 for header (lower byte only)");
check(ft601_wr_n === 1'b0,
"Write strobe active during header");
check(uut.ft601_data_oe === 1'b1,
"Data bus output enabled during header");
// ════════════════════════════════════════════════════════
// TEST GROUP 4: Doppler data capture verification
// TEST GROUP 4: Doppler data verification
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 4: Doppler Data Capture ---");
$display("\n--- Test Group 4: Doppler Data Verification ---");
apply_reset;
ft601_txe = 0;
// Preload only doppler pending (not cfar) so the FSM sends
// doppler data. After doppler, SEND_DETECT sees cfar_data_pending=0
// and skips to SEND_FOOTER, then WAIT_ACK, then IDLE.
preload_doppler_pending;
assert_range_valid(32'h0000_0001);
wait_for_state(S_SEND_DOPPLER, 100);
#1;
check(uut.current_state === S_SEND_DOPPLER,
"Reached SEND_DOPPLER_DATA");
// Provide doppler data via valid pulse (updates captured values)
@(posedge clk);
doppler_real = 16'hAAAA;
@@ -559,70 +524,110 @@ module tb_usb_data_interface;
check(uut.doppler_imag_cap === 16'h5555,
"doppler_imag captured correctly");
// Drive a packet with pending doppler + cfar (both needed for gating
// since all streams are enabled after reset/apply_reset).
preload_pending_data;
assert_range_valid(32'h0000_0001);
// The FSM has doppler_data_pending set and sends 4 bytes, then
// transitions past SEND_DETECT (cfar_data_pending=0) to IDLE.
wait_for_state(S_IDLE, 100);
#1;
check(uut.current_state === S_IDLE,
"Packet completed with doppler data");
check(uut.doppler_data_pending === 1'b0,
"doppler_data_pending cleared after packet");
"Doppler done, packet completed");
// ════════════════════════════════════════════════════════
// TEST GROUP 5: CFAR detection data
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 5: CFAR Detection Data ---");
// Start a new packet with both doppler and cfar pending to verify
// cfar data is properly sent in SEND_DETECTION_DATA.
apply_reset;
ft601_txe = 0;
preload_pending_data;
assert_range_valid(32'h0000_0002);
// FSM races through: HEADER -> RANGE -> DOPPLER -> DETECT -> FOOTER -> IDLE
// All pending flags consumed proves SEND_DETECT was entered.
wait_for_state(S_IDLE, 200);
#1;
check(uut.cfar_data_pending === 1'b0,
"cfar_data_pending cleared after packet");
"Starting in SEND_DETECTION_DATA");
// Verify the full packet completed with cfar data consumed
check(uut.current_state === S_IDLE &&
uut.doppler_data_pending === 1'b0 &&
uut.cfar_data_pending === 1'b0,
"CFAR detection sent, all pending flags cleared");
"CFAR detection sent, FSM advanced past SEND_DETECTION_DATA");
// ════════════════════════════════════════════════════════
// TEST GROUP 6: Footer retained after packet
// TEST GROUP 6: Footer check
//
// Strategy: drive packet with ft601_txe=0 all the way through.
// The SEND_FOOTER state is only active for 1 cycle, but we can
// poll the state machine at each ft601_clk_in edge to observe
// it. We use a monitor-style approach: run the packet and
// capture what ft601_data_out contains when we see SEND_FOOTER.
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 6: Footer Retention ---");
$display("\n--- Test Group 6: Footer Check ---");
apply_reset;
ft601_txe = 0;
@(posedge clk);
cfar_detection = 1'b1;
@(posedge clk);
// Drive packet through range data
preload_pending_data;
assert_range_valid(32'hFACE_FEED);
wait_for_state(S_SEND_DOPPLER, 100);
// Feed doppler data (need 4 pulses)
pulse_doppler_once(16'h1111, 16'h2222);
pulse_doppler_once(16'h1111, 16'h2222);
pulse_doppler_once(16'h1111, 16'h2222);
pulse_doppler_once(16'h1111, 16'h2222);
wait_for_state(S_SEND_DETECT, 100);
// Feed cfar data, but keep ft601_txe=0 so it flows through
pulse_cfar_once(1'b1);
// Now the FSM should pass through SEND_FOOTER quickly.
// Use wait_for_state to reach SEND_FOOTER, or it may already
// be at WAIT_ACK/IDLE. Let's catch WAIT_ACK or IDLE.
// The footer values are latched into registers, so we can
// verify them even after the state transitions.
// Key verification: the FOOTER constant (0x55) must have been
// driven. We check this by looking at the constant definition.
// Since we can't easily freeze the FSM at SEND_FOOTER without
// also stalling SEND_DETECTION_DATA (both check ft601_txe),
// we verify the footer indirectly:
// 1. The packet completed (reached IDLE/WAIT_ACK)
// 2. ft601_data_out last held 0x55 during SEND_FOOTER
wait_for_state(S_IDLE, 100);
#1;
// If we reached IDLE, the full sequence ran including footer
check(uut.current_state === S_IDLE,
"Full packet incl. footer completed, back in IDLE");
// The last word driven was word 2 which contains footer 0x55.
// WAIT_ACK and IDLE don't overwrite ft601_data_out, so it retains
// the last driven value.
check(uut.ft601_data_out[15:8] === 8'h55,
"ft601_data_out retains footer 0x55 in word 2 position");
// The registered ft601_data_out should still hold 0x55 from
// SEND_FOOTER (WAIT_ACK and IDLE don't overwrite ft601_data_out).
// Actually, looking at the DUT: WAIT_ACK only sets wr_n=1 and
// data_oe=0, it doesn't change ft601_data_out. So it retains 0x55.
check(uut.ft601_data_out[7:0] === 8'h55,
"ft601_data_out retains footer 0x55 after packet");
// Verify WAIT_ACK → IDLE transition
// Verify WAIT_ACK behavior by doing another packet and catching it
apply_reset;
ft601_txe = 0;
preload_pending_data;
assert_range_valid(32'h1234_5678);
wait_for_state(S_SEND_DOPPLER, 100);
pulse_doppler_once(16'hABCD, 16'hEF01);
pulse_doppler_once(16'hABCD, 16'hEF01);
pulse_doppler_once(16'hABCD, 16'hEF01);
pulse_doppler_once(16'hABCD, 16'hEF01);
wait_for_state(S_SEND_DETECT, 100);
pulse_cfar_once(1'b0);
// WAIT_ACK lasts exactly 1 ft601_clk_in cycle then goes IDLE.
// Poll for IDLE (which means WAIT_ACK already happened).
wait_for_state(S_IDLE, 100);
#1;
check(uut.current_state === S_IDLE,
"Returned to IDLE after WAIT_ACK");
check(ft601_wr_n === 1'b1,
"ft601_wr_n deasserted in IDLE");
"ft601_wr_n deasserted in IDLE (was deasserted in WAIT_ACK)");
check(uut.ft601_data_oe === 1'b0,
"Data bus released in IDLE");
"Data bus released in IDLE (was released in WAIT_ACK)");
// ════════════════════════════════════════════════════════
// TEST GROUP 7: Full packet sequence (end-to-end)
@@ -641,24 +646,23 @@ module tb_usb_data_interface;
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 8: FIFO Backpressure ---");
apply_reset;
ft601_txe = 1; // FIFO full — stall
ft601_txe = 1;
preload_pending_data;
assert_range_valid(32'hBBBB_CCCC);
wait_for_state(S_SEND_DATA_WORD, 50);
wait_for_state(S_SEND_HEADER, 50);
repeat (10) @(posedge ft601_clk_in); #1;
check(uut.current_state === S_SEND_DATA_WORD,
"Stalled in SEND_DATA_WORD when ft601_txe=1 (FIFO full)");
check(uut.current_state === S_SEND_HEADER,
"Stalled in SEND_HEADER when ft601_txe=1 (FIFO full)");
check(ft601_wr_n === 1'b1,
"ft601_wr_n not asserted during backpressure stall");
ft601_txe = 0;
repeat (6) @(posedge ft601_clk_in); #1;
repeat (2) @(posedge ft601_clk_in); #1;
check(uut.current_state === S_IDLE || uut.current_state === S_WAIT_ACK,
"Resumed and completed after backpressure released");
check(uut.current_state !== S_SEND_HEADER,
"Resumed from SEND_HEADER after backpressure released");
// ════════════════════════════════════════════════════════
// TEST GROUP 9: Clock divider
@@ -701,6 +705,13 @@ module tb_usb_data_interface;
ft601_txe = 0;
preload_pending_data;
assert_range_valid(32'h1111_2222);
wait_for_state(S_SEND_DOPPLER, 100);
pulse_doppler_once(16'h3333, 16'h4444);
pulse_doppler_once(16'h3333, 16'h4444);
pulse_doppler_once(16'h3333, 16'h4444);
pulse_doppler_once(16'h3333, 16'h4444);
wait_for_state(S_SEND_DETECT, 100);
pulse_cfar_once(1'b0);
wait_for_state(S_WAIT_ACK, 50);
#1;
@@ -794,7 +805,7 @@ module tb_usb_data_interface;
// Start a write packet
preload_pending_data;
assert_range_valid(32'hFACE_FEED);
wait_for_state(S_SEND_DATA_WORD, 50);
wait_for_state(S_SEND_HEADER, 50);
@(posedge ft601_clk_in); #1;
// While write FSM is active, assert RXF=0 (host has data)
@@ -807,6 +818,13 @@ module tb_usb_data_interface;
// Deassert RXF, complete the write packet
ft601_rxf = 1;
wait_for_state(S_SEND_DOPPLER, 100);
pulse_doppler_once(16'hAAAA, 16'hBBBB);
pulse_doppler_once(16'hAAAA, 16'hBBBB);
pulse_doppler_once(16'hAAAA, 16'hBBBB);
pulse_doppler_once(16'hAAAA, 16'hBBBB);
wait_for_state(S_SEND_DETECT, 100);
pulse_cfar_once(1'b1);
wait_for_state(S_IDLE, 100);
@(posedge ft601_clk_in); #1;
@@ -823,42 +841,32 @@ module tb_usb_data_interface;
// ════════════════════════════════════════════════════════
// TEST GROUP 15: Stream Control Gating (Gap 2)
// Verify that disabling individual streams causes the write
// FSM to zero those fields in the packed words.
// FSM to skip those data phases.
// ════════════════════════════════════════════════════════
$display("\n--- Test Group 15: Stream Control Gating (Gap 2) ---");
// 15a: Disable doppler stream (stream_control = 3'b101 = range + cfar only)
apply_reset;
ft601_txe = 1; // Stall to inspect packed words
ft601_txe = 0;
stream_control = 3'b101; // range + cfar, no doppler
// Wait for CDC propagation (2-stage sync)
repeat (6) @(posedge ft601_clk_in);
@(posedge clk);
doppler_real = 16'hAAAA;
doppler_imag = 16'hBBBB;
cfar_detection = 1'b1;
@(posedge clk);
// Preload cfar pending so the FSM enters the SEND_DETECT data path
// (without it, SEND_DETECT skips immediately on !cfar_data_pending).
preload_cfar_pending;
// Drive range valid — triggers write FSM
assert_range_valid(32'hAA11_BB22);
wait_for_state(S_SEND_DATA_WORD, 200);
repeat (2) @(posedge ft601_clk_in); #1;
// With doppler disabled, doppler fields in words 1 and 2 should be zero
// Word 1: {range[7:0], 0x00, 0x00, 0x00} (doppler zeroed)
check(uut.data_pkt_word1[23:0] === 24'h000000,
"Stream gate: doppler bytes zeroed in word 1 when disabled");
// Word 2 byte 3 (dop_im_lo) should also be zero
check(uut.data_pkt_word2[31:24] === 8'h00,
"Stream gate: dop_im_lo zeroed in word 2 when disabled");
// Let it complete
ft601_txe = 0;
wait_for_state(S_IDLE, 100);
// FSM: IDLE -> SEND_HEADER -> SEND_RANGE (doppler disabled) -> SEND_DETECT -> FOOTER
// The FSM races through SEND_DETECT in 1 cycle (cfar_data_pending is consumed).
// Verify the packet completed correctly (doppler was skipped).
wait_for_state(S_IDLE, 200);
#1;
// Reaching IDLE proves: HEADER -> RANGE -> (skip DOPPLER) -> DETECT -> FOOTER -> ACK -> IDLE.
// cfar_data_pending consumed confirms SEND_DETECT was entered.
check(uut.current_state === S_IDLE && uut.cfar_data_pending === 1'b0,
"Stream gate: reached SEND_DETECT (range sent, doppler skipped)");
check(uut.current_state === S_IDLE,
"Stream gate: packet completed without doppler");
@@ -943,6 +951,28 @@ module tb_usb_data_interface;
"Status readback: returned to IDLE after 8-word response");
// Verify the status snapshot was captured correctly.
// status_words[0] = {0xFF, 3'b000, mode[1:0], 5'b0, stream_ctrl[2:0], cfar_threshold[15:0]}
// = {8'hFF, 3'b000, 2'b01, 5'b00000, 3'b101, 16'hABCD}
// = 0xFF_09_05_ABCD... let's compute:
// Byte 3: 0xFF = 8'hFF
// Byte 2: {3'b000, 2'b01} = 5'b00001 + 3 high bits of next field...
// Actually the packing is: {8'hFF, 3'b000, status_radar_mode[1:0], 5'b00000, status_stream_ctrl[2:0], status_cfar_threshold[15:0]}
// = {8'hFF, 3'b000, 2'b01, 5'b00000, 3'b101, 16'hABCD}
// = 8'hFF, 5'b00001, 8'b00000101, 16'hABCD
// = FF_09_05_ABCD? Let me compute carefully:
// Bits [31:24] = 8'hFF = 0xFF
// Bits [23:21] = 3'b000
// Bits [20:19] = 2'b01 (mode)
// Bits [18:14] = 5'b00000
// Bits [13:11] = 3'b101 (stream_ctrl)
// Bits [10:0] = ... wait, cfar_threshold is 16 bits → [15:0]
// Total bits = 8+3+2+5+3+16 = 37 bits — won't fit in 32!
// Re-reading the RTL: the packing at line 241 is:
// {8'hFF, 3'b000, status_radar_mode, 5'b00000, status_stream_ctrl, status_cfar_threshold}
// = 8 + 3 + 2 + 5 + 3 + 16 = 37 bits
// This would be truncated to 32 bits. Let me re-read the actual RTL to check.
// For now, just verify status_words[1] (word index 1 in the packet = idx 2 in FSM)
// status_words[1] = {status_long_chirp, status_long_listen} = {16'd3000, 16'd13700}
check(uut.status_words[1] === {16'd3000, 16'd13700},
"Status readback: word 1 = {long_chirp, long_listen}");
check(uut.status_words[2] === {16'd17540, 16'd50},
9_Firmware/9_2_FPGA/usb_data_interface.v
+130 -187
View File
@@ -1,17 +1,3 @@
/**
* usb_data_interface.v
*
* FT601 USB 3.0 SuperSpeed FIFO Interface (32-bit bus, 100 MHz ft601_clk).
* Used on the 200T premium dev board. Production 50T board uses
* usb_data_interface_ft2232h.v (FT2232H, 8-bit, 60 MHz) instead.
*
* USB disconnect recovery:
* A clock-activity watchdog in the clk domain detects when ft601_clk_in
* stops (USB cable unplugged). After ~0.65 ms of silence (65536 system
* clocks) it asserts ft601_clk_lost, which is OR'd into the FT-domain
* reset so FSMs and FIFOs return to a clean state. When ft601_clk_in
* resumes, a 2-stage reset synchronizer deasserts the reset cleanly.
*/
module usb_data_interface (
input wire clk, // Main clock (100MHz recommended)
input wire reset_n,
@@ -29,18 +15,13 @@ module usb_data_interface (
// FT601 Interface (Slave FIFO mode)
// Data bus
inout wire [31:0] ft601_data, // 32-bit bidirectional data bus
output reg [3:0] ft601_be, // Byte enable (active-HIGH per DS_FT600Q-FT601Q Table 3.2)
output reg [3:0] ft601_be, // Byte enable (4 lanes for 32-bit mode)
// Control signals
// VESTIGIAL OUTPUTS — kept for 200T board port compatibility.
// On the 200T, these are constrained to physical pins G21 (TXE) and
// G22 (RXF) in xc7a200t_fbg484.xdc. Removing them from the RTL would
// break the 200T build. They are reset to 1 and never driven; the
// actual FT601 flow-control inputs are ft601_txe and ft601_rxf below.
output reg ft601_txe_n, // VESTIGIAL: unused output, always 1
output reg ft601_rxf_n, // VESTIGIAL: unused output, always 1
input wire ft601_txe, // TXE: Transmit FIFO Not Full (active-low: 0 = space available)
input wire ft601_rxf, // RXF: Receive FIFO Not Empty (active-low: 0 = data available)
output reg ft601_txe_n, // Transmit enable (active low)
output reg ft601_rxf_n, // Receive enable (active low)
input wire ft601_txe, // TXE: Transmit FIFO Not Full (high = space available to write)
input wire ft601_rxf, // RXF: Receive FIFO Not Empty (high = data available to read)
output reg ft601_wr_n, // Write strobe (active low)
output reg ft601_rd_n, // Read strobe (active low)
output reg ft601_oe_n, // Output enable (active low)
@@ -116,26 +97,21 @@ localparam FT601_BURST_SIZE = 512; // Max burst size in bytes
// ============================================================================
// WRITE FSM State definitions (Verilog-2001 compatible)
// ============================================================================
// Rewritten: data packet is now 3 x 32-bit writes (11 payload bytes + 1 pad).
// Word 0: {HEADER, range[31:24], range[23:16], range[15:8]} BE=1111
// Word 1: {range[7:0], doppler_real[15:8], doppler_real[7:0], doppler_imag[15:8]} BE=1111
// Word 2: {doppler_imag[7:0], detection, FOOTER, 8'h00} BE=1110
localparam [3:0] IDLE = 4'd0,
SEND_DATA_WORD = 4'd1,
SEND_STATUS = 4'd2,
WAIT_ACK = 4'd3;
localparam [2:0] IDLE = 3'd0,
SEND_HEADER = 3'd1,
SEND_RANGE_DATA = 3'd2,
SEND_DOPPLER_DATA = 3'd3,
SEND_DETECTION_DATA = 3'd4,
SEND_FOOTER = 3'd5,
WAIT_ACK = 3'd6,
SEND_STATUS = 3'd7; // Gap 2: status readback
reg [3:0] current_state;
reg [1:0] data_word_idx; // 0..2 for 3-word data packet
reg [2:0] current_state;
reg [7:0] byte_counter;
reg [31:0] data_buffer;
reg [31:0] ft601_data_out;
reg ft601_data_oe; // Output enable for bidirectional data bus
// Pre-packed data words (registered snapshot of CDC'd data)
reg [31:0] data_pkt_word0;
reg [31:0] data_pkt_word1;
reg [31:0] data_pkt_word2;
reg [3:0] data_pkt_be2; // BE for last word (BE=1110 since byte 3 is pad)
// ============================================================================
// READ FSM State definitions (Gap 4: USB Read Path)
// ============================================================================
@@ -208,67 +184,6 @@ always @(posedge clk or negedge reset_n) begin
end
end
// ============================================================================
// CLOCK-ACTIVITY WATCHDOG (clk domain)
// ============================================================================
// Detects when ft601_clk_in stops (USB cable unplugged). A toggle register
// in the ft601_clk domain flips every edge. The clk domain synchronizes it
// and checks for transitions. If no transition is seen for 2^16 = 65536
// clk cycles (~0.65 ms at 100 MHz), ft601_clk_lost asserts.
// Toggle register: flips every ft601_clk edge (ft601_clk domain)
reg ft601_heartbeat;
always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
if (!ft601_reset_n)
ft601_heartbeat <= 1'b0;
else
ft601_heartbeat <= ~ft601_heartbeat;
end
// Synchronize heartbeat into clk domain (2-stage)
(* ASYNC_REG = "TRUE" *) reg [1:0] ft601_hb_sync;
reg ft601_hb_prev;
reg [15:0] ft601_clk_timeout;
reg ft601_clk_lost;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
ft601_hb_sync <= 2'b00;
ft601_hb_prev <= 1'b0;
ft601_clk_timeout <= 16'd0;
ft601_clk_lost <= 1'b0;
end else begin
ft601_hb_sync <= {ft601_hb_sync[0], ft601_heartbeat};
ft601_hb_prev <= ft601_hb_sync[1];
if (ft601_hb_sync[1] != ft601_hb_prev) begin
// ft601_clk is alive — reset counter, clear lost flag
ft601_clk_timeout <= 16'd0;
ft601_clk_lost <= 1'b0;
end else if (!ft601_clk_lost) begin
if (ft601_clk_timeout == 16'hFFFF)
ft601_clk_lost <= 1'b1;
else
ft601_clk_timeout <= ft601_clk_timeout + 16'd1;
end
end
end
// Effective FT601-domain reset: asserted by global reset OR clock loss.
// Deassertion synchronized to ft601_clk via 2-stage sync to avoid
// metastability on the recovery edge.
(* ASYNC_REG = "TRUE" *) reg [1:0] ft601_reset_sync;
wire ft601_reset_raw_n = ft601_reset_n & ~ft601_clk_lost;
always @(posedge ft601_clk_in or negedge ft601_reset_raw_n) begin
if (!ft601_reset_raw_n)
ft601_reset_sync <= 2'b00;
else
ft601_reset_sync <= {ft601_reset_sync[0], 1'b1};
end
wire ft601_effective_reset_n = ft601_reset_sync[1];
// FT601-domain captured data (sampled from holding regs on sync'd edge)
reg [31:0] range_profile_cap;
reg [15:0] doppler_real_cap;
@@ -282,18 +197,6 @@ reg cfar_detection_cap;
reg doppler_data_pending;
reg cfar_data_pending;
// 1-cycle delayed range trigger. range_valid_ft fires on the same clock
// edge that range_profile_cap is captured (non-blocking). If the FSM
// reads range_profile_cap on that same edge it sees the STALE value.
// Delaying the trigger by one cycle guarantees the capture register has
// settled before the FSM packs the data words.
reg range_data_ready;
// Frame sync: sample counter (ft601_clk domain, wraps at NUM_CELLS)
// Bit 7 of detection byte is set when sample_counter == 0 (frame start).
localparam [11:0] NUM_CELLS = 12'd2048; // 64 range x 32 doppler
reg [11:0] sample_counter;
// Gap 2: CDC for stream_control (clk_100m -> ft601_clk_in)
// stream_control changes infrequently (only on host USB command), so
// per-bit 2-stage synchronizers are sufficient. No Gray coding needed
@@ -325,8 +228,8 @@ wire range_valid_ft;
wire doppler_valid_ft;
wire cfar_valid_ft;
always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
if (!ft601_effective_reset_n) begin
always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
if (!ft601_reset_n) begin
range_valid_sync <= 2'b00;
doppler_valid_sync <= 2'b00;
cfar_valid_sync <= 2'b00;
@@ -337,7 +240,6 @@ always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
doppler_real_cap <= 16'd0;
doppler_imag_cap <= 16'd0;
cfar_detection_cap <= 1'b0;
range_data_ready <= 1'b0;
// Fix #5: Default to range-only on reset (prevents write FSM deadlock)
stream_ctrl_sync_0 <= 3'b001;
stream_ctrl_sync_1 <= 3'b001;
@@ -374,7 +276,7 @@ always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
// Word 4: AGC metrics + range_mode
status_words[4] <= {status_agc_current_gain, // [31:28]
status_agc_peak_magnitude, // [27:20]
status_agc_saturation_count, // [19:12] 8-bit saturation count
status_agc_saturation_count, // [19:12]
status_agc_enable, // [11]
9'd0, // [10:2] reserved
status_range_mode}; // [1:0]
@@ -400,10 +302,6 @@ always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
if (cfar_valid_sync[1] && !cfar_valid_sync_d) begin
cfar_detection_cap <= cfar_detection_hold;
end
// 1-cycle delayed trigger: ensures range_profile_cap has settled
// before the FSM reads it for word packing.
range_data_ready <= range_valid_ft;
end
end
@@ -416,11 +314,11 @@ assign cfar_valid_ft = cfar_valid_sync[1] && !cfar_valid_sync_d;
// FT601 data bus direction control
assign ft601_data = ft601_data_oe ? ft601_data_out : 32'hzzzz_zzzz;
always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
if (!ft601_effective_reset_n) begin
always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
if (!ft601_reset_n) begin
current_state <= IDLE;
read_state <= RD_IDLE;
data_word_idx <= 2'd0;
byte_counter <= 0;
ft601_data_out <= 0;
ft601_data_oe <= 0;
ft601_be <= 4'b1111; // All bytes enabled for 32-bit mode
@@ -438,11 +336,6 @@ always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
cmd_value <= 16'd0;
doppler_data_pending <= 1'b0;
cfar_data_pending <= 1'b0;
data_pkt_word0 <= 32'd0;
data_pkt_word1 <= 32'd0;
data_pkt_word2 <= 32'd0;
data_pkt_be2 <= 4'b1110;
sample_counter <= 12'd0;
// NOTE: ft601_clk_out is driven by the clk-domain always block below.
// Do NOT assign it here (ft601_clk_in domain) — causes multi-driven net.
end else begin
@@ -531,66 +424,124 @@ always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
current_state <= SEND_STATUS;
status_word_idx <= 3'd0;
end
// Trigger on range_data_ready (1 cycle after range_valid_ft)
// so that range_profile_cap has settled from the CDC block.
// Gate on pending flags: only send when all enabled
// streams have fresh data (avoids stale doppler/CFAR)
else if (range_data_ready && stream_range_en
&& (!stream_doppler_en || doppler_data_pending)
&& (!stream_cfar_en || cfar_data_pending)) begin
// Trigger write FSM on range_valid edge (primary data source).
// Doppler/cfar data_pending flags are checked inside
// SEND_DOPPLER_DATA and SEND_DETECTION_DATA to skip or send.
// Do NOT trigger on pending flags alone — they're sticky and
// would cause repeated packet starts without new range data.
else if (range_valid_ft && stream_range_en) begin
// Don't start write if a read is about to begin
if (ft601_rxf) begin // rxf=1 means no host data pending
// Pack 11-byte data packet into 3 x 32-bit words
// Doppler fields zeroed when stream disabled
// CFAR field zeroed when stream disabled
data_pkt_word0 <= {HEADER,
range_profile_cap[31:24],
range_profile_cap[23:16],
range_profile_cap[15:8]};
data_pkt_word1 <= {range_profile_cap[7:0],
stream_doppler_en ? doppler_real_cap[15:8] : 8'd0,
stream_doppler_en ? doppler_real_cap[7:0] : 8'd0,
stream_doppler_en ? doppler_imag_cap[15:8] : 8'd0};
data_pkt_word2 <= {stream_doppler_en ? doppler_imag_cap[7:0] : 8'd0,
stream_cfar_en
? {(sample_counter == 12'd0), 6'b0, cfar_detection_cap}
: {(sample_counter == 12'd0), 7'd0},
FOOTER,
8'h00}; // pad byte
data_pkt_be2 <= 4'b1110; // 3 valid bytes + 1 pad
data_word_idx <= 2'd0;
current_state <= SEND_DATA_WORD;
current_state <= SEND_HEADER;
byte_counter <= 0;
end
end
end
SEND_DATA_WORD: begin
SEND_HEADER: begin
if (!ft601_txe) begin // FT601 TX FIFO not empty
ft601_data_oe <= 1;
ft601_data_out <= {24'b0, HEADER};
ft601_be <= 4'b0001; // Only lower byte valid
ft601_wr_n <= 0; // Assert write strobe
// Gap 2: skip to first enabled stream
if (stream_range_en)
current_state <= SEND_RANGE_DATA;
else if (stream_doppler_en)
current_state <= SEND_DOPPLER_DATA;
else if (stream_cfar_en)
current_state <= SEND_DETECTION_DATA;
else
current_state <= SEND_FOOTER; // No streams — send footer only
end
end
SEND_RANGE_DATA: begin
if (!ft601_txe) begin
ft601_data_oe <= 1;
ft601_wr_n <= 0;
case (data_word_idx)
2'd0: begin
ft601_data_out <= data_pkt_word0;
ft601_be <= 4'b1111;
end
2'd1: begin
ft601_data_out <= data_pkt_word1;
ft601_be <= 4'b1111;
end
2'd2: begin
ft601_data_out <= data_pkt_word2;
ft601_be <= data_pkt_be2;
end
default: ;
ft601_be <= 4'b1111; // All bytes valid for 32-bit word
case (byte_counter)
0: ft601_data_out <= range_profile_cap;
1: ft601_data_out <= {range_profile_cap[23:0], 8'h00};
2: ft601_data_out <= {range_profile_cap[15:0], 16'h0000};
3: ft601_data_out <= {range_profile_cap[7:0], 24'h000000};
endcase
if (data_word_idx == 2'd2) begin
data_word_idx <= 2'd0;
current_state <= WAIT_ACK;
ft601_wr_n <= 0;
if (byte_counter == 3) begin
byte_counter <= 0;
// Gap 2: skip disabled streams
if (stream_doppler_en)
current_state <= SEND_DOPPLER_DATA;
else if (stream_cfar_en)
current_state <= SEND_DETECTION_DATA;
else
current_state <= SEND_FOOTER;
end else begin
data_word_idx <= data_word_idx + 2'd1;
byte_counter <= byte_counter + 1;
end
end
end
SEND_DOPPLER_DATA: begin
if (!ft601_txe && doppler_data_pending) begin
ft601_data_oe <= 1;
ft601_be <= 4'b1111;
case (byte_counter)
0: ft601_data_out <= {doppler_real_cap, doppler_imag_cap};
1: ft601_data_out <= {doppler_imag_cap, doppler_real_cap[15:8], 8'h00};
2: ft601_data_out <= {doppler_real_cap[7:0], doppler_imag_cap[15:8], 16'h0000};
3: ft601_data_out <= {doppler_imag_cap[7:0], 24'h000000};
endcase
ft601_wr_n <= 0;
if (byte_counter == 3) begin
byte_counter <= 0;
doppler_data_pending <= 1'b0;
if (stream_cfar_en)
current_state <= SEND_DETECTION_DATA;
else
current_state <= SEND_FOOTER;
end else begin
byte_counter <= byte_counter + 1;
end
end else if (!doppler_data_pending) begin
// No doppler data available yet — skip to next stream
byte_counter <= 0;
if (stream_cfar_en)
current_state <= SEND_DETECTION_DATA;
else
current_state <= SEND_FOOTER;
end
end
SEND_DETECTION_DATA: begin
if (!ft601_txe && cfar_data_pending) begin
ft601_data_oe <= 1;
ft601_be <= 4'b0001;
ft601_data_out <= {24'b0, 7'b0, cfar_detection_cap};
ft601_wr_n <= 0;
cfar_data_pending <= 1'b0;
current_state <= SEND_FOOTER;
end else if (!cfar_data_pending) begin
// No CFAR data available yet — skip to footer
current_state <= SEND_FOOTER;
end
end
SEND_FOOTER: begin
if (!ft601_txe) begin
ft601_data_oe <= 1;
ft601_be <= 4'b0001;
ft601_data_out <= {24'b0, FOOTER};
ft601_wr_n <= 0;
current_state <= WAIT_ACK;
end
end
// Gap 2: Status readback — send 6 x 32-bit status words
// Format: HEADER, status_words[0..5], FOOTER
@@ -630,14 +581,6 @@ always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
WAIT_ACK: begin
ft601_wr_n <= 1;
ft601_data_oe <= 0; // Release data bus
// Clear pending flags — data consumed
doppler_data_pending <= 1'b0;
cfar_data_pending <= 1'b0;
// Advance frame sync counter
if (sample_counter == NUM_CELLS - 12'd1)
sample_counter <= 12'd0;
else
sample_counter <= sample_counter + 12'd1;
current_state <= IDLE;
end
endcase
@@ -670,8 +613,8 @@ ODDR #(
`else
// Simulation: behavioral clock forwarding
reg ft601_clk_out_sim;
always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
if (!ft601_effective_reset_n)
always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
if (!ft601_reset_n)
ft601_clk_out_sim <= 1'b0;
else
ft601_clk_out_sim <= 1'b1;
9_Firmware/9_2_FPGA/usb_data_interface_ft2232h.v
+19 -131
View File
@@ -36,13 +36,6 @@
* Clock domains:
* clk = 100 MHz system clock (radar data domain)
* ft_clk = 60 MHz from FT2232H CLKOUT (USB FIFO domain)
*
* USB disconnect recovery:
* A clock-activity watchdog in the clk domain detects when ft_clk stops
* (USB cable unplugged). After ~0.65 ms of silence (65536 system clocks)
* it asserts ft_clk_lost, which is OR'd into the FT-domain reset so
* FSMs and FIFOs return to a clean state. When ft_clk resumes, a 2-stage
* reset synchronizer deasserts the reset cleanly in the ft_clk domain.
*/
module usb_data_interface_ft2232h (
@@ -66,9 +59,7 @@ module usb_data_interface_ft2232h (
output reg ft_rd_n, // Read strobe (active low)
output reg ft_wr_n, // Write strobe (active low)
output reg ft_oe_n, // Output enable (active low) — bus direction
output reg ft_siwu, // Send Immediate / WakeUp — UNUSED: held low.
// SIWU could flush the TX FIFO for lower latency
// but is not needed at current data rates. Deferred.
output reg ft_siwu, // Send Immediate / WakeUp
// Clock from FT2232H (directly used — no ODDR forwarding needed)
input wire ft_clk, // 60 MHz from FT2232H CLKOUT
@@ -143,7 +134,6 @@ localparam [2:0] RD_IDLE = 3'd0,
reg [2:0] rd_state;
reg [1:0] rd_byte_cnt; // 0..3 for 4-byte command word
reg [31:0] rd_shift_reg; // Shift register to assemble 4-byte command
reg rd_cmd_complete; // Set when all 4 bytes received (distinguishes from abort)
// ============================================================================
// DATA BUS DIRECTION CONTROL
@@ -202,70 +192,6 @@ always @(posedge clk or negedge reset_n) begin
end
end
// ============================================================================
// CLOCK-ACTIVITY WATCHDOG (clk domain)
// ============================================================================
// Detects when ft_clk stops (USB cable unplugged). A toggle register in the
// ft_clk domain flips every ft_clk edge. The clk domain synchronizes it and
// checks for transitions. If no transition is seen for 2^16 = 65536 clk
// cycles (~0.65 ms at 100 MHz), ft_clk_lost asserts.
//
// ft_clk_lost feeds into the effective reset for the ft_clk domain so that
// FSMs and capture registers return to a clean state automatically.
// Toggle register: flips every ft_clk edge (ft_clk domain)
reg ft_heartbeat;
always @(posedge ft_clk or negedge ft_reset_n) begin
if (!ft_reset_n)
ft_heartbeat <= 1'b0;
else
ft_heartbeat <= ~ft_heartbeat;
end
// Synchronize heartbeat into clk domain (2-stage)
(* ASYNC_REG = "TRUE" *) reg [1:0] ft_hb_sync;
reg ft_hb_prev;
reg [15:0] ft_clk_timeout;
reg ft_clk_lost;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
ft_hb_sync <= 2'b00;
ft_hb_prev <= 1'b0;
ft_clk_timeout <= 16'd0;
ft_clk_lost <= 1'b0;
end else begin
ft_hb_sync <= {ft_hb_sync[0], ft_heartbeat};
ft_hb_prev <= ft_hb_sync[1];
if (ft_hb_sync[1] != ft_hb_prev) begin
// ft_clk is alive — reset counter, clear lost flag
ft_clk_timeout <= 16'd0;
ft_clk_lost <= 1'b0;
end else if (!ft_clk_lost) begin
if (ft_clk_timeout == 16'hFFFF)
ft_clk_lost <= 1'b1;
else
ft_clk_timeout <= ft_clk_timeout + 16'd1;
end
end
end
// Effective FT-domain reset: asserted by global reset OR clock loss.
// Deassertion synchronized to ft_clk via 2-stage sync to avoid
// metastability on the recovery edge.
(* ASYNC_REG = "TRUE" *) reg [1:0] ft_reset_sync;
wire ft_reset_raw_n = ft_reset_n & ~ft_clk_lost;
always @(posedge ft_clk or negedge ft_reset_raw_n) begin
if (!ft_reset_raw_n)
ft_reset_sync <= 2'b00;
else
ft_reset_sync <= {ft_reset_sync[0], 1'b1};
end
wire ft_effective_reset_n = ft_reset_sync[1];
// --- 3-stage synchronizers (ft_clk domain) ---
// 3 stages for better MTBF at 60 MHz
@@ -302,25 +228,12 @@ reg cfar_detection_cap;
reg doppler_data_pending;
reg cfar_data_pending;
// 1-cycle delayed range trigger. range_valid_ft fires on the same clock
// edge that range_profile_cap is captured (non-blocking). If the FSM
// reads range_profile_cap on that same edge it sees the STALE value.
// Delaying the trigger by one cycle guarantees the capture register has
// settled before the byte mux reads it.
reg range_data_ready;
// Frame sync: sample counter (ft_clk domain, wraps at NUM_CELLS)
// Bit 7 of detection byte is set when sample_counter == 0 (frame start).
// This allows the Python host to resynchronize without a protocol change.
localparam [11:0] NUM_CELLS = 12'd2048; // 64 range x 32 doppler
reg [11:0] sample_counter;
// Status snapshot (ft_clk domain)
reg [31:0] status_words [0:5];
integer si; // status_words loop index
always @(posedge ft_clk or negedge ft_effective_reset_n) begin
if (!ft_effective_reset_n) begin
always @(posedge ft_clk or negedge ft_reset_n) begin
if (!ft_reset_n) begin
range_toggle_sync <= 3'b000;
doppler_toggle_sync <= 3'b000;
cfar_toggle_sync <= 3'b000;
@@ -333,7 +246,6 @@ always @(posedge ft_clk or negedge ft_effective_reset_n) begin
doppler_real_cap <= 16'd0;
doppler_imag_cap <= 16'd0;
cfar_detection_cap <= 1'b0;
range_data_ready <= 1'b0;
// Default to range-only on reset (prevents write FSM deadlock)
stream_ctrl_sync_0 <= 3'b001;
stream_ctrl_sync_1 <= 3'b001;
@@ -367,10 +279,6 @@ always @(posedge ft_clk or negedge ft_effective_reset_n) begin
if (cfar_valid_ft)
cfar_detection_cap <= cfar_detection_hold;
// 1-cycle delayed trigger: ensures range_profile_cap has settled
// before the FSM reads it via the byte mux.
range_data_ready <= range_valid_ft;
// Status snapshot on request
if (status_req_ft) begin
// Word 0: {0xFF[31:24], mode[23:22], stream[21:19], 3'b000[18:16], threshold[15:0]}
@@ -407,16 +315,11 @@ always @(*) begin
5'd2: data_pkt_byte = range_profile_cap[23:16];
5'd3: data_pkt_byte = range_profile_cap[15:8];
5'd4: data_pkt_byte = range_profile_cap[7:0]; // range LSB
// Doppler fields: zero when stream_doppler_en is off
5'd5: data_pkt_byte = stream_doppler_en ? doppler_real_cap[15:8] : 8'd0;
5'd6: data_pkt_byte = stream_doppler_en ? doppler_real_cap[7:0] : 8'd0;
5'd7: data_pkt_byte = stream_doppler_en ? doppler_imag_cap[15:8] : 8'd0;
5'd8: data_pkt_byte = stream_doppler_en ? doppler_imag_cap[7:0] : 8'd0;
// Detection field: zero when stream_cfar_en is off
// Bit 7 = frame_start flag (sample_counter == 0), bit 0 = cfar_detection
5'd9: data_pkt_byte = stream_cfar_en
? {(sample_counter == 12'd0), 6'b0, cfar_detection_cap}
: {(sample_counter == 12'd0), 7'd0};
5'd5: data_pkt_byte = doppler_real_cap[15:8]; // doppler_real MSB
5'd6: data_pkt_byte = doppler_real_cap[7:0]; // doppler_real LSB
5'd7: data_pkt_byte = doppler_imag_cap[15:8]; // doppler_imag MSB
5'd8: data_pkt_byte = doppler_imag_cap[7:0]; // doppler_imag LSB
5'd9: data_pkt_byte = {7'b0, cfar_detection_cap}; // detection
5'd10: data_pkt_byte = FOOTER;
default: data_pkt_byte = 8'h00;
endcase
@@ -473,13 +376,12 @@ end
// Write FSM and Read FSM share the bus. Write FSM operates when Read FSM
// is idle. Read FSM takes priority when host has data available.
always @(posedge ft_clk or negedge ft_effective_reset_n) begin
if (!ft_effective_reset_n) begin
always @(posedge ft_clk or negedge ft_reset_n) begin
if (!ft_reset_n) begin
wr_state <= WR_IDLE;
wr_byte_idx <= 5'd0;
rd_state <= RD_IDLE;
rd_byte_cnt <= 2'd0;
rd_cmd_complete <= 1'b0;
rd_shift_reg <= 32'd0;
ft_data_out <= 8'd0;
ft_data_oe <= 1'b0;
@@ -494,7 +396,6 @@ always @(posedge ft_clk or negedge ft_effective_reset_n) begin
cmd_value <= 16'd0;
doppler_data_pending <= 1'b0;
cfar_data_pending <= 1'b0;
sample_counter <= 12'd0;
end else begin
// Default: clear one-shot signals
cmd_valid <= 1'b0;
@@ -536,19 +437,17 @@ always @(posedge ft_clk or negedge ft_effective_reset_n) begin
rd_shift_reg <= {rd_shift_reg[23:0], ft_data};
if (rd_byte_cnt == 2'd3) begin
// All 4 bytes received
ft_rd_n <= 1'b1;
rd_byte_cnt <= 2'd0;
rd_cmd_complete <= 1'b1;
rd_state <= RD_DEASSERT;
ft_rd_n <= 1'b1;
rd_byte_cnt <= 2'd0;
rd_state <= RD_DEASSERT;
end else begin
rd_byte_cnt <= rd_byte_cnt + 2'd1;
// Keep reading if more data available
if (ft_rxf_n) begin
// Host ran out of data mid-command — abort
ft_rd_n <= 1'b1;
rd_byte_cnt <= 2'd0;
rd_cmd_complete <= 1'b0;
rd_state <= RD_DEASSERT;
ft_rd_n <= 1'b1;
rd_byte_cnt <= 2'd0;
rd_state <= RD_DEASSERT;
end
end
end
@@ -557,8 +456,7 @@ always @(posedge ft_clk or negedge ft_effective_reset_n) begin
// Deassert OE (1 cycle after RD deasserted)
ft_oe_n <= 1'b1;
// Only process if we received a full 4-byte command
if (rd_cmd_complete) begin
rd_cmd_complete <= 1'b0;
if (rd_byte_cnt == 2'd0) begin
rd_state <= RD_PROCESS;
end else begin
// Incomplete command — discard
@@ -593,13 +491,8 @@ always @(posedge ft_clk or negedge ft_effective_reset_n) begin
wr_state <= WR_STATUS_SEND;
wr_byte_idx <= 5'd0;
end
// Trigger on range_data_ready (1 cycle after range_valid_ft)
// so that range_profile_cap has settled from the CDC block.
// Gate on pending flags: only send when all enabled
// streams have fresh data (avoids stale doppler/CFAR)
else if (range_data_ready && stream_range_en
&& (!stream_doppler_en || doppler_data_pending)
&& (!stream_cfar_en || cfar_data_pending)) begin
// Trigger on range_valid edge (primary data trigger)
else if (range_valid_ft && stream_range_en) begin
if (ft_rxf_n) begin // No host read pending
wr_state <= WR_DATA_SEND;
wr_byte_idx <= 5'd0;
@@ -645,11 +538,6 @@ always @(posedge ft_clk or negedge ft_effective_reset_n) begin
// Clear pending flags — data consumed
doppler_data_pending <= 1'b0;
cfar_data_pending <= 1'b0;
// Advance frame sync counter
if (sample_counter == NUM_CELLS - 12'd1)
sample_counter <= 12'd0;
else
sample_counter <= sample_counter + 12'd1;
wr_state <= WR_IDLE;
end
9_Firmware/9_3_GUI/GUI_PyQt_Map.py
+5 -5
View File
@@ -108,7 +108,7 @@ class GPSData:
@dataclass
class RadarSettings:
"""Radar system configuration"""
system_frequency: float = 10e9 # Hz
system_frequency: float = 10.5e9 # Hz (PLFM TX LO)
chirp_duration_1: float = 30e-6 # Long chirp duration (s)
chirp_duration_2: float = 0.5e-6 # Short chirp duration (s)
chirps_per_position: int = 32
@@ -116,8 +116,8 @@ class RadarSettings:
freq_max: float = 30e6 # Hz
prf1: float = 1000 # PRF 1 (Hz)
prf2: float = 2000 # PRF 2 (Hz)
max_distance: float = 50000 # Max detection range (m)
coverage_radius: float = 50000 # Map coverage radius (m)
max_distance: float = 1536 # Max detection range (m) -- 64 bins x 24 m
coverage_radius: float = 1536 # Map coverage radius (m)
class TileServer(Enum):
@@ -198,7 +198,7 @@ class RadarMapWidget(QWidget):
pitch=0.0
)
self._targets: list[RadarTarget] = []
self._coverage_radius = 50000 # meters
self._coverage_radius = 1536 # meters (64 bins x 24 m, 3 km mode)
self._tile_server = TileServer.OPENSTREETMAP
self._show_coverage = True
self._show_trails = False
@@ -1088,7 +1088,7 @@ class TargetSimulator(QObject):
new_range = target.range - target.velocity * 0.5 # 0.5 second update
# Check if target is still in range
if new_range < 500 or new_range > 50000:
if new_range < 50 or new_range > 1536:
# Remove this target and add a new one
continue
9_Firmware/9_3_GUI/GUI_V5.py
+5 -5
View File
@@ -81,7 +81,7 @@ class RadarTarget:
@dataclass
class RadarSettings:
system_frequency: float = 10e9
system_frequency: float = 10.5e9
chirp_duration_1: float = 30e-6 # Long chirp duration
chirp_duration_2: float = 0.5e-6 # Short chirp duration
chirps_per_position: int = 32
@@ -89,8 +89,8 @@ class RadarSettings:
freq_max: float = 30e6
prf1: float = 1000
prf2: float = 2000
max_distance: float = 50000
map_size: float = 50000 # Map size in meters
max_distance: float = 1536
map_size: float = 1536 # Map size in meters (64 bins x 24 m)
@dataclass
@@ -1196,8 +1196,8 @@ class RadarGUI:
("Frequency Max (Hz):", "freq_max", 30e6),
("PRF1 (Hz):", "prf1", 1000),
("PRF2 (Hz):", "prf2", 2000),
("Max Distance (m):", "max_distance", 50000),
("Map Size (m):", "map_size", 50000),
("Max Distance (m):", "max_distance", 1536),
("Map Size (m):", "map_size", 1536),
("Google Maps API Key:", "google_maps_api_key", "YOUR_GOOGLE_MAPS_API_KEY"),
]
9_Firmware/9_3_GUI/GUI_V5_Demo.py
+5 -5
View File
@@ -77,7 +77,7 @@ class RadarTarget:
@dataclass
class RadarSettings:
system_frequency: float = 10e9
system_frequency: float = 10.5e9
chirp_duration_1: float = 30e-6 # Long chirp duration
chirp_duration_2: float = 0.5e-6 # Short chirp duration
chirps_per_position: int = 32
@@ -85,8 +85,8 @@ class RadarSettings:
freq_max: float = 30e6
prf1: float = 1000
prf2: float = 2000
max_distance: float = 50000
map_size: float = 50000 # Map size in meters
max_distance: float = 1536
map_size: float = 1536 # Map size in meters (64 bins x 24 m)
@dataclass
@@ -1254,8 +1254,8 @@ class RadarGUI:
("Frequency Max (Hz):", "freq_max", 30e6),
("PRF1 (Hz):", "prf1", 1000),
("PRF2 (Hz):", "prf2", 2000),
("Max Distance (m):", "max_distance", 50000),
("Map Size (m):", "map_size", 50000),
("Max Distance (m):", "max_distance", 1536),
("Map Size (m):", "map_size", 1536),
]
self.settings_vars = {}
9_Firmware/9_3_GUI/GUI_V6.py
+5 -11
View File
@@ -1,9 +1,3 @@
# =============================================================================
# DEPRECATED: GUI V6 is superseded by GUI_V65_Tk (tkinter) and V7 (PyQt6).
# This file is retained for reference only. Do not use for new development.
# Removal planned for next major release.
# =============================================================================
import tkinter as tk
from tkinter import ttk, messagebox
import threading
@@ -70,7 +64,7 @@ class RadarTarget:
@dataclass
class RadarSettings:
system_frequency: float = 10e9
system_frequency: float = 10.5e9
chirp_duration_1: float = 30e-6 # Long chirp duration
chirp_duration_2: float = 0.5e-6 # Short chirp duration
chirps_per_position: int = 32
@@ -78,8 +72,8 @@ class RadarSettings:
freq_max: float = 30e6
prf1: float = 1000
prf2: float = 2000
max_distance: float = 50000
map_size: float = 50000 # Map size in meters
max_distance: float = 1536
map_size: float = 1536 # Map size in meters (64 bins x 24 m)
@dataclass
class GPSData:
@@ -1659,8 +1653,8 @@ class RadarGUI:
('Frequency Max (Hz):', 'freq_max', 30e6),
('PRF1 (Hz):', 'prf1', 1000),
('PRF2 (Hz):', 'prf2', 2000),
('Max Distance (m):', 'max_distance', 50000),
('Map Size (m):', 'map_size', 50000),
('Max Distance (m):', 'max_distance', 1536),
('Map Size (m):', 'map_size', 1536),
('Google Maps API Key:', 'google_maps_api_key', 'YOUR_GOOGLE_MAPS_API_KEY')
]
9_Firmware/9_3_GUI/GUI_V65_Tk.py
+23 -49
View File
@@ -59,7 +59,7 @@ except (ModuleNotFoundError, ImportError):
# Import protocol layer (no GUI deps)
from radar_protocol import (
RadarProtocol, FT2232HConnection, FT601Connection,
RadarProtocol, FT2232HConnection,
DataRecorder, RadarAcquisition,
RadarFrame, StatusResponse,
NUM_RANGE_BINS, NUM_DOPPLER_BINS, WATERFALL_DEPTH,
@@ -98,10 +98,10 @@ class DemoTarget:
__slots__ = ("azimuth", "classification", "id", "range_m", "snr", "velocity")
# Physical range grid: 64 bins x ~24 m/bin = ~1536 m max
# Bin spacing = c / (2 * Fs) * decimation, where Fs = 100 MHz DDC output.
_RANGE_PER_BIN: float = (3e8 / (2 * 100e6)) * 16 # ~24 m
_MAX_RANGE: float = _RANGE_PER_BIN * NUM_RANGE_BINS # ~1536 m
# Physical range grid: matched-filter receiver, 100 MSPS post-DDC, 16:1 decimation
# range_per_bin = c / (2 * 100e6) * 16 = 24.0 m
_RANGE_PER_BIN: float = (3e8 / (2 * 100e6)) * 16 # 24.0 m
_MAX_RANGE: float = _RANGE_PER_BIN * NUM_RANGE_BINS # 1536 m
def __init__(self, tid: int):
self.id = tid
@@ -188,10 +188,10 @@ class DemoSimulator:
mag = np.zeros((NUM_RANGE_BINS, NUM_DOPPLER_BINS), dtype=np.float64)
det = np.zeros((NUM_RANGE_BINS, NUM_DOPPLER_BINS), dtype=np.uint8)
# Range/Doppler scaling: bin spacing = c/(2*Fs)*decimation
range_per_bin = (3e8 / (2 * 100e6)) * 16 # ~24 m/bin
# Range/Doppler scaling -- matched-filter receiver, 100 MSPS, 16:1 decimation
range_per_bin = (3e8 / (2 * 100e6)) * 16 # 24.0 m/bin
max_range = range_per_bin * NUM_RANGE_BINS
vel_per_bin = 5.34 # m/s per Doppler bin (radar_scene.py: lam/(2*16*PRI))
vel_per_bin = 2.67 # m/s per Doppler bin (lam/(2*32*167us))
for t in targets:
if t.range_m > max_range or t.range_m < 0:
@@ -386,14 +386,15 @@ class RadarDashboard:
UPDATE_INTERVAL_MS = 100 # 10 Hz display refresh
# Radar parameters used for range-axis scaling.
SAMPLE_RATE = 100e6 # Hz — DDC output I/Q rate (matched filter input)
# Matched-filter receiver: range_per_bin = c / (2 * fs_processing) * decimation
# = 3e8 / (2 * 100e6) * 16 = 24.0 m/bin
BANDWIDTH = 20e6 # Hz — chirp bandwidth (for display/info only)
C = 3e8 # m/s — speed of light
def __init__(self, root: tk.Tk, mock: bool,
def __init__(self, root: tk.Tk, connection: FT2232HConnection,
recorder: DataRecorder, device_index: int = 0):
self.root = root
self._mock = mock
self.conn: FT2232HConnection | FT601Connection | None = None
self.conn = connection
self.recorder = recorder
self.device_index = device_index
@@ -487,16 +488,6 @@ class RadarDashboard:
style="Accent.TButton")
self.btn_connect.pack(side="right", padx=4)
# USB Interface selector (production FT2232H / premium FT601)
self._usb_iface_var = tk.StringVar(value="FT2232H (Production)")
self.cmb_usb_iface = ttk.Combobox(
top, textvariable=self._usb_iface_var,
values=["FT2232H (Production)", "FT601 (Premium)"],
state="readonly", width=20,
)
self.cmb_usb_iface.pack(side="right", padx=4)
ttk.Label(top, text="USB:", font=("Menlo", 10)).pack(side="right")
self.btn_record = ttk.Button(top, text="Record", command=self._on_record)
self.btn_record.pack(side="right", padx=4)
@@ -526,9 +517,9 @@ class RadarDashboard:
self._build_log_tab(tab_log)
def _build_display_tab(self, parent):
# Compute physical axis limits
# Bin spacing = c / (2 * Fs_ddc) for matched-filter processing.
range_per_bin = self.C / (2.0 * self.SAMPLE_RATE) * 16 # ~24 m
# Compute physical axis limits -- matched-filter receiver
# Range per bin: c / (2 * fs_processing) * decimation_factor = 24.0 m
range_per_bin = self.C / (2.0 * 100e6) * 16 # 24.0 m
max_range = range_per_bin * NUM_RANGE_BINS
doppler_bin_lo = 0
@@ -1029,17 +1020,15 @@ class RadarDashboard:
# ------------------------------------------------------------ Actions
def _on_connect(self):
if self.conn is not None and self.conn.is_open:
if self.conn.is_open:
# Disconnect
if self._acq_thread is not None:
self._acq_thread.stop()
self._acq_thread.join(timeout=2)
self._acq_thread = None
self.conn.close()
self.conn = None
self.lbl_status.config(text="DISCONNECTED", foreground=RED)
self.btn_connect.config(text="Connect")
self.cmb_usb_iface.config(state="readonly")
log.info("Disconnected")
return
@@ -1049,16 +1038,6 @@ class RadarDashboard:
if self._replay_active:
self._replay_stop()
# Create connection based on USB Interface selector
iface = self._usb_iface_var.get()
if "FT601" in iface:
self.conn = FT601Connection(mock=self._mock)
else:
self.conn = FT2232HConnection(mock=self._mock)
# Disable interface selector while connecting/connected
self.cmb_usb_iface.config(state="disabled")
# Open connection in a background thread to avoid blocking the GUI
self.lbl_status.config(text="CONNECTING...", foreground=YELLOW)
self.btn_connect.config(state="disabled")
@@ -1085,8 +1064,6 @@ class RadarDashboard:
else:
self.lbl_status.config(text="CONNECT FAILED", foreground=RED)
self.btn_connect.config(text="Connect")
self.cmb_usb_iface.config(state="readonly")
self.conn = None
def _on_record(self):
if self.recorder.recording:
@@ -1135,9 +1112,6 @@ class RadarDashboard:
f"Opcode 0x{opcode:02X} is hardware-only (ignored in replay)"))
return
cmd = RadarProtocol.build_command(opcode, value)
if self.conn is None:
log.warning("No connection — command not sent")
return
ok = self.conn.write(cmd)
log.info(f"CMD 0x{opcode:02X} val={value} ({'OK' if ok else 'FAIL'})")
@@ -1176,7 +1150,7 @@ class RadarDashboard:
if self._replay_active or self._replay_ctrl is not None:
self._replay_stop()
if self._acq_thread is not None:
if self.conn is not None and self.conn.is_open:
if self.conn.is_open:
self._on_connect() # disconnect
else:
# Connection dropped unexpectedly — just clean up the thread
@@ -1575,17 +1549,17 @@ def main():
args = parser.parse_args()
if args.live:
mock = False
conn = FT2232HConnection(mock=False)
mode_str = "LIVE"
else:
mock = True
conn = FT2232HConnection(mock=True)
mode_str = "MOCK"
recorder = DataRecorder()
root = tk.Tk()
dashboard = RadarDashboard(root, mock, recorder, device_index=args.device)
dashboard = RadarDashboard(root, conn, recorder, device_index=args.device)
if args.record:
filepath = os.path.join(
@@ -1610,8 +1584,8 @@ def main():
if dashboard._acq_thread is not None:
dashboard._acq_thread.stop()
dashboard._acq_thread.join(timeout=2)
if dashboard.conn is not None and dashboard.conn.is_open:
dashboard.conn.close()
if conn.is_open:
conn.close()
if recorder.recording:
recorder.stop()
root.destroy()
9_Firmware/9_3_GUI/GUI_V6_Demo.py
+2 -8
View File
@@ -1,11 +1,5 @@
#!/usr/bin/env python3
# =============================================================================
# DEPRECATED: GUI V6 Demo is superseded by GUI_V65_Tk and V7.
# This file is retained for reference only. Do not use for new development.
# Removal planned for next major release.
# =============================================================================
"""
Radar System GUI - Fully Functional Demo Version
All buttons work, simulated radar data is generated in real-time
@@ -51,7 +45,7 @@ class RadarSettings:
range_bins: int = 1024
doppler_bins: int = 32
prf: float = 1000
max_range: float = 5000
max_range: float = 1536
max_velocity: float = 100
cfar_threshold: float = 13.0
@@ -583,7 +577,7 @@ class RadarDemoGUI:
('Range Bins:', 'range_bins', 1024, 256, 2048),
('Doppler Bins:', 'doppler_bins', 32, 8, 128),
('PRF (Hz):', 'prf', 1000, 100, 10000),
('Max Range (m):', 'max_range', 5000, 100, 50000),
('Max Range (m):', 'max_range', 1536, 100, 25000),
('Max Velocity (m/s):', 'max_vel', 100, 10, 500),
('CFAR Threshold (dB):', 'cfar', 13.0, 5.0, 30.0)
]
9_Firmware/9_3_GUI/GUI_versions.txt
+1 -1
View File
@@ -6,7 +6,7 @@ GUI_V4 ==> Added pitch correction
GUI_V5 ==> Added Mercury Color
GUI_V6 ==> Added USB3 FT601 support [DEPRECATED — superseded by V65/V7]
GUI_V6 ==> Added USB3 FT601 support
GUI_V65_Tk ==> Board bring-up dashboard (FT2232H reader, real-time R-D heatmap, CFAR overlay, waterfall, host commands, HDF5 recording, replay, demo mode)
radar_protocol ==> Protocol layer (packet parsing, command building, FT2232H connection, data recorder, acquisition thread)
9_Firmware/9_3_GUI/adi_agc_analysis.py
-338
View File
@@ -1,338 +0,0 @@
# ruff: noqa: T201
#!/usr/bin/env python3
"""
One-off AGC saturation analysis for ADI CN0566 raw IQ captures.
Bit-accurate simulation of rx_gain_control.v AGC inner loop applied
to real captured IQ data. Three scenarios per dataset:
Row 1 — AGC OFF: Fixed gain_shift=0 (pass-through). Shows raw clipping.
Row 2 — AGC ON: Auto-adjusts from gain_shift=0. Clipping clears.
Row 3 — AGC delayed: OFF for first half, ON at midpoint.
Shows the transition: clipping → AGC activates → clears.
Key RTL details modelled exactly:
- gain_shift[3]=direction (0=amplify/left, 1=attenuate/right), [2:0]=amount
- Internal agc_gain is signed -7..+7
- Peak is measured PRE-gain (raw input |sample|, upper 8 of 15 bits)
- Saturation is measured POST-gain (overflow from shift)
- Attack: gain -= agc_attack when any sample clips (immediate)
- Decay: gain += agc_decay when peak < target AND holdoff expired
- Hold: when peak >= target AND no saturation, hold gain, reset holdoff
Usage:
python adi_agc_analysis.py
python adi_agc_analysis.py --data /path/to/file.npy --label "my capture"
"""
import argparse
import sys
from pathlib import Path
import matplotlib.pyplot as plt
import numpy as np
from v7.agc_sim import (
encoding_to_signed,
apply_gain_shift,
quantize_iq,
AGCConfig,
AGCState,
process_agc_frame,
)
# ---------------------------------------------------------------------------
# FPGA AGC parameters (rx_gain_control.v reset defaults)
# ---------------------------------------------------------------------------
AGC_TARGET = 200 # host_agc_target (8-bit, default 200)
ADC_RAIL = 4095 # 12-bit ADC max absolute value
# ---------------------------------------------------------------------------
# Per-frame AGC simulation using v7.agc_sim (bit-accurate to RTL)
# ---------------------------------------------------------------------------
def simulate_agc(frames: np.ndarray, agc_enabled: bool = True,
enable_at_frame: int = 0,
initial_gain_enc: int = 0x00) -> dict:
"""Simulate FPGA inner-loop AGC across all frames.
Parameters
----------
frames : (N, chirps, samples) complex — raw ADC captures (12-bit range)
agc_enabled : if False, gain stays fixed
enable_at_frame : frame index where AGC activates
initial_gain_enc : gain_shift[3:0] encoding when AGC enables (default 0x00 = pass-through)
"""
n_frames = frames.shape[0]
# Output arrays
out_gain_enc = np.zeros(n_frames, dtype=int)
out_gain_signed = np.zeros(n_frames, dtype=int)
out_peak_mag = np.zeros(n_frames, dtype=int)
out_sat_count = np.zeros(n_frames, dtype=int)
out_sat_rate = np.zeros(n_frames, dtype=float)
out_rms_post = np.zeros(n_frames, dtype=float)
# AGC state — managed by process_agc_frame()
state = AGCState(
gain=encoding_to_signed(initial_gain_enc),
holdoff_counter=0,
was_enabled=False,
)
for i in range(n_frames):
frame_i, frame_q = quantize_iq(frames[i])
agc_active = agc_enabled and (i >= enable_at_frame)
# Build per-frame config (enable toggles at enable_at_frame)
config = AGCConfig(enabled=agc_active)
result = process_agc_frame(frame_i, frame_q, config, state)
# RMS of shifted signal
rms = float(np.sqrt(np.mean(
result.shifted_i.astype(np.float64)**2
+ result.shifted_q.astype(np.float64)**2)))
total_samples = frame_i.size + frame_q.size
sat_rate = result.overflow_raw / total_samples if total_samples > 0 else 0.0
# Record outputs
out_gain_enc[i] = result.gain_enc
out_gain_signed[i] = result.gain_signed
out_peak_mag[i] = result.peak_mag_8bit
out_sat_count[i] = result.saturation_count
out_sat_rate[i] = sat_rate
out_rms_post[i] = rms
return {
"gain_enc": out_gain_enc,
"gain_signed": out_gain_signed,
"peak_mag": out_peak_mag,
"sat_count": out_sat_count,
"sat_rate": out_sat_rate,
"rms_post": out_rms_post,
}
# ---------------------------------------------------------------------------
# Range-Doppler processing for heatmap display
# ---------------------------------------------------------------------------
def process_frame_rd(frame: np.ndarray, gain_enc: int,
n_range: int = 64,
n_doppler: int = 32) -> np.ndarray:
"""Range-Doppler magnitude for one frame with gain applied."""
frame_i, frame_q = quantize_iq(frame)
si, sq, _ = apply_gain_shift(frame_i, frame_q, gain_enc)
iq = si.astype(np.float64) + 1j * sq.astype(np.float64)
n_chirps, _ = iq.shape
range_fft = np.fft.fft(iq, axis=1)[:, :n_range]
doppler_fft = np.fft.fftshift(np.fft.fft(range_fft, axis=0), axes=0)
center = n_chirps // 2
half_d = n_doppler // 2
doppler_fft = doppler_fft[center - half_d:center + half_d, :]
rd_mag = np.abs(doppler_fft.real) + np.abs(doppler_fft.imag)
return rd_mag.T # (n_range, n_doppler)
# ---------------------------------------------------------------------------
# Plotting
# ---------------------------------------------------------------------------
def plot_scenario(axes, data: np.ndarray, agc: dict, title: str,
enable_frame: int = 0):
"""Plot one AGC scenario across 5 axes."""
n = data.shape[0]
xs = np.arange(n)
# Range-Doppler heatmap
if enable_frame > 0 and enable_frame < n:
f_before = max(0, enable_frame - 1)
f_after = min(n - 1, n - 2)
rd_before = process_frame_rd(data[f_before], int(agc["gain_enc"][f_before]))
rd_after = process_frame_rd(data[f_after], int(agc["gain_enc"][f_after]))
combined = np.hstack([rd_before, rd_after])
im = axes[0].imshow(
20 * np.log10(combined + 1), aspect="auto", origin="lower",
cmap="inferno", interpolation="nearest")
axes[0].axvline(x=rd_before.shape[1] - 0.5, color="cyan",
linewidth=2, linestyle="--")
axes[0].set_title(f"{title}\nL: f{f_before} (pre) | R: f{f_after} (post)")
else:
worst = int(np.argmax(agc["sat_count"]))
best = int(np.argmin(agc["sat_count"]))
f_show = worst if agc["sat_count"][worst] > 0 else best
rd = process_frame_rd(data[f_show], int(agc["gain_enc"][f_show]))
im = axes[0].imshow(
20 * np.log10(rd + 1), aspect="auto", origin="lower",
cmap="inferno", interpolation="nearest")
axes[0].set_title(f"{title}\nFrame {f_show}")
axes[0].set_xlabel("Doppler bin")
axes[0].set_ylabel("Range bin")
plt.colorbar(im, ax=axes[0], label="dB", shrink=0.8)
# Signed gain history (the real AGC state)
axes[1].plot(xs, agc["gain_signed"], color="#00ff88", linewidth=1.5)
axes[1].axhline(y=0, color="gray", linestyle=":", alpha=0.5,
label="Pass-through")
if enable_frame > 0:
axes[1].axvline(x=enable_frame, color="yellow", linewidth=2,
linestyle="--", label="AGC ON")
axes[1].set_ylim(-8, 8)
axes[1].set_ylabel("Gain (signed)")
axes[1].set_title("AGC Internal Gain (-7=max atten, +7=max amp)")
axes[1].legend(fontsize=7, loc="upper right")
axes[1].grid(True, alpha=0.3)
# Peak magnitude (PRE-gain, 8-bit)
axes[2].plot(xs, agc["peak_mag"], color="#ffaa00", linewidth=1.0)
axes[2].axhline(y=AGC_TARGET, color="cyan", linestyle="--",
alpha=0.7, label=f"Target ({AGC_TARGET})")
axes[2].axhspan(240, 255, color="red", alpha=0.15, label="Clip zone")
if enable_frame > 0:
axes[2].axvline(x=enable_frame, color="yellow", linewidth=2,
linestyle="--", alpha=0.8)
axes[2].set_ylim(0, 260)
axes[2].set_ylabel("Peak (8-bit)")
axes[2].set_title("Peak Magnitude (pre-gain, raw input)")
axes[2].legend(fontsize=7, loc="upper right")
axes[2].grid(True, alpha=0.3)
# Saturation count (POST-gain overflow)
axes[3].fill_between(xs, agc["sat_count"], color="red", alpha=0.4)
axes[3].plot(xs, agc["sat_count"], color="red", linewidth=0.8)
if enable_frame > 0:
axes[3].axvline(x=enable_frame, color="yellow", linewidth=2,
linestyle="--", alpha=0.8)
axes[3].set_ylabel("Overflow Count")
total = int(agc["sat_count"].sum())
axes[3].set_title(f"Post-Gain Overflow (total={total})")
axes[3].grid(True, alpha=0.3)
# RMS signal level (post-gain)
axes[4].plot(xs, agc["rms_post"], color="#44aaff", linewidth=1.0)
if enable_frame > 0:
axes[4].axvline(x=enable_frame, color="yellow", linewidth=2,
linestyle="--", alpha=0.8)
axes[4].set_ylabel("RMS")
axes[4].set_xlabel("Frame")
axes[4].set_title("Post-Gain RMS Level")
axes[4].grid(True, alpha=0.3)
def analyze_dataset(data: np.ndarray, label: str):
"""Run 3-scenario analysis for one dataset."""
n_frames = data.shape[0]
mid = n_frames // 2
print(f"\n{'='*60}")
print(f" {label} — shape {data.shape}")
print(f"{'='*60}")
# Raw ADC stats
raw_sat = np.sum((np.abs(data.real) >= ADC_RAIL) |
(np.abs(data.imag) >= ADC_RAIL))
print(f" Raw ADC saturation: {raw_sat} samples "
f"({100*raw_sat/(2*data.size):.2f}%)")
# Scenario 1: AGC OFF — pass-through (gain_shift=0x00)
print(" [1/3] AGC OFF (gain=0, pass-through) ...")
agc_off = simulate_agc(data, agc_enabled=False, initial_gain_enc=0x00)
print(f" Post-gain overflow: {agc_off['sat_count'].sum()} "
f"(should be 0 — no amplification)")
# Scenario 2: AGC ON from frame 0
print(" [2/3] AGC ON (from start) ...")
agc_on = simulate_agc(data, agc_enabled=True, enable_at_frame=0,
initial_gain_enc=0x00)
print(f" Final gain: {agc_on['gain_signed'][-1]} "
f"(enc=0x{agc_on['gain_enc'][-1]:X})")
print(f" Post-gain overflow: {agc_on['sat_count'].sum()}")
# Scenario 3: AGC delayed
print(f" [3/3] AGC delayed (ON at frame {mid}) ...")
agc_delayed = simulate_agc(data, agc_enabled=True,
enable_at_frame=mid,
initial_gain_enc=0x00)
pre_sat = int(agc_delayed["sat_count"][:mid].sum())
post_sat = int(agc_delayed["sat_count"][mid:].sum())
print(f" Pre-AGC overflow: {pre_sat} "
f"Post-AGC overflow: {post_sat}")
# Plot
fig, axes = plt.subplots(3, 5, figsize=(28, 14))
fig.suptitle(f"AERIS-10 AGC Analysis — {label}\n"
f"({n_frames} frames, {data.shape[1]} chirps, "
f"{data.shape[2]} samples/chirp, "
f"raw ADC sat={100*raw_sat/(2*data.size):.2f}%)",
fontsize=13, fontweight="bold", y=0.99)
plot_scenario(axes[0], data, agc_off, "AGC OFF (pass-through)")
plot_scenario(axes[1], data, agc_on, "AGC ON (from start)")
plot_scenario(axes[2], data, agc_delayed,
f"AGC delayed (ON at frame {mid})", enable_frame=mid)
for ax, lbl in zip(axes[:, 0],
["AGC OFF", "AGC ON", "AGC DELAYED"],
strict=True):
ax.annotate(lbl, xy=(-0.35, 0.5), xycoords="axes fraction",
fontsize=13, fontweight="bold", color="white",
ha="center", va="center", rotation=90)
plt.tight_layout(rect=[0.03, 0, 1, 0.95])
return fig
def main():
parser = argparse.ArgumentParser(
description="AGC analysis for ADI raw IQ captures "
"(bit-accurate rx_gain_control.v simulation)")
parser.add_argument("--amp", type=str,
default=str(Path.home() / "Downloads/adi_radar_data"
"/amp_radar"
"/phaser_amp_4MSPS_500M_300u_256_m3dB.npy"),
help="Path to amplified radar .npy")
parser.add_argument("--noamp", type=str,
default=str(Path.home() / "Downloads/adi_radar_data"
"/no_amp_radar"
"/phaser_NOamp_4MSPS_500M_300u_256.npy"),
help="Path to non-amplified radar .npy")
parser.add_argument("--data", type=str, default=None,
help="Single dataset mode")
parser.add_argument("--label", type=str, default="Custom Data")
args = parser.parse_args()
plt.style.use("dark_background")
if args.data:
data = np.load(args.data)
analyze_dataset(data, args.label)
plt.show()
return
figs = []
for path, label in [(args.amp, "With Amplifier (-3 dB)"),
(args.noamp, "No Amplifier")]:
if not Path(path).exists():
print(f"WARNING: {path} not found, skipping")
continue
data = np.load(path)
fig = analyze_dataset(data, label)
figs.append(fig)
if not figs:
print("No data found. Use --amp/--noamp or --data.")
sys.exit(1)
plt.show()
if __name__ == "__main__":
main()
9_Firmware/9_3_GUI/radar_protocol.py
+6 -200
View File
@@ -6,7 +6,6 @@ Pure-logic module for USB packet parsing and command building.
No GUI dependencies — safe to import from tests and headless scripts.
USB Interface: FT2232H USB 2.0 (8-bit, 50T production board) via pyftdi
FT601 USB 3.0 (32-bit, 200T premium board) via ftd3xx
USB Packet Protocol (11-byte):
TX (FPGA→Host):
@@ -23,7 +22,7 @@ import queue
import logging
import contextlib
from dataclasses import dataclass, field
from typing import Any, ClassVar
from typing import Any
from enum import IntEnum
@@ -201,9 +200,7 @@ class RadarProtocol:
range_i = _to_signed16(struct.unpack_from(">H", raw, 3)[0])
doppler_i = _to_signed16(struct.unpack_from(">H", raw, 5)[0])
doppler_q = _to_signed16(struct.unpack_from(">H", raw, 7)[0])
det_byte = raw[9]
detection = det_byte & 0x01
frame_start = (det_byte >> 7) & 0x01
detection = raw[9] & 0x01
return {
"range_i": range_i,
@@ -211,7 +208,6 @@ class RadarProtocol:
"doppler_i": doppler_i,
"doppler_q": doppler_q,
"detection": detection,
"frame_start": frame_start,
}
@staticmethod
@@ -437,191 +433,7 @@ class FT2232HConnection:
pkt += struct.pack(">h", np.clip(range_i, -32768, 32767))
pkt += struct.pack(">h", np.clip(dop_i, -32768, 32767))
pkt += struct.pack(">h", np.clip(dop_q, -32768, 32767))
# Bit 7 = frame_start (sample_counter == 0), bit 0 = detection
det_byte = (detection & 0x01) | (0x80 if idx == 0 else 0x00)
pkt.append(det_byte)
pkt.append(FOOTER_BYTE)
buf += pkt
self._mock_seq_idx = (start_idx + num_packets) % NUM_CELLS
return bytes(buf)
# ============================================================================
# FT601 USB 3.0 Connection (premium board only)
# ============================================================================
# Optional ftd3xx import (FTDI's proprietary driver for FT60x USB 3.0 chips).
# pyftdi does NOT support FT601 — it only handles USB 2.0 chips (FT232H, etc.)
try:
import ftd3xx # type: ignore[import-untyped]
FTD3XX_AVAILABLE = True
_Ftd3xxError: type = ftd3xx.FTD3XXError # type: ignore[attr-defined]
except ImportError:
FTD3XX_AVAILABLE = False
_Ftd3xxError = OSError # fallback for type-checking; never raised
class FT601Connection:
"""
FT601 USB 3.0 SuperSpeed FIFO bridge — premium board only.
The FT601 has a 32-bit data bus and runs at 100 MHz.
VID:PID = 0x0403:0x6030 or 0x6031 (FTDI FT60x).
Requires the ``ftd3xx`` library (``pip install ftd3xx`` on Windows,
or ``libft60x`` on Linux). This is FTDI's proprietary USB 3.0 driver;
``pyftdi`` only supports USB 2.0 and will NOT work with FT601.
Public contract matches FT2232HConnection so callers can swap freely.
"""
VID = 0x0403
PID_LIST: ClassVar[list[int]] = [0x6030, 0x6031]
def __init__(self, mock: bool = True):
self._mock = mock
self._dev = None
self._lock = threading.Lock()
self.is_open = False
# Mock state (reuses same synthetic data pattern)
self._mock_frame_num = 0
self._mock_rng = np.random.RandomState(42)
def open(self, device_index: int = 0) -> bool:
if self._mock:
self.is_open = True
log.info("FT601 mock device opened (no hardware)")
return True
if not FTD3XX_AVAILABLE:
log.error(
"ftd3xx library required for FT601 hardware — "
"install with: pip install ftd3xx"
)
return False
try:
self._dev = ftd3xx.create(device_index, ftd3xx.OPEN_BY_INDEX)
if self._dev is None:
log.error("No FT601 device found at index %d", device_index)
return False
# Verify chip configuration — only reconfigure if needed.
# setChipConfiguration triggers USB re-enumeration, which
# invalidates the device handle and requires a re-open cycle.
cfg = self._dev.getChipConfiguration()
needs_reconfig = (
cfg.FIFOMode != 0 # 245 FIFO mode
or cfg.ChannelConfig != 0 # 1 channel, 32-bit
or cfg.OptionalFeatureSupport != 0
)
if needs_reconfig:
cfg.FIFOMode = 0
cfg.ChannelConfig = 0
cfg.OptionalFeatureSupport = 0
self._dev.setChipConfiguration(cfg)
# Device re-enumerates — close stale handle, wait, re-open
self._dev.close()
self._dev = None
import time
time.sleep(2.0) # wait for USB re-enumeration
self._dev = ftd3xx.create(device_index, ftd3xx.OPEN_BY_INDEX)
if self._dev is None:
log.error("FT601 not found after reconfiguration")
return False
log.info("FT601 reconfigured and re-opened (index %d)", device_index)
self.is_open = True
log.info("FT601 device opened (index %d)", device_index)
return True
except (OSError, _Ftd3xxError) as e:
log.error("FT601 open failed: %s", e)
self._dev = None
return False
def close(self):
if self._dev is not None:
with contextlib.suppress(Exception):
self._dev.close()
self._dev = None
self.is_open = False
def read(self, size: int = 4096) -> bytes | None:
"""Read raw bytes from FT601. Returns None on error/timeout."""
if not self.is_open:
return None
if self._mock:
return self._mock_read(size)
with self._lock:
try:
data = self._dev.readPipe(0x82, size, raw=True)
return bytes(data) if data else None
except (OSError, _Ftd3xxError) as e:
log.error("FT601 read error: %s", e)
return None
def write(self, data: bytes) -> bool:
"""Write raw bytes to FT601. Data must be 4-byte aligned for 32-bit bus."""
if not self.is_open:
return False
if self._mock:
log.info(f"FT601 mock write: {data.hex()}")
return True
# Pad to 4-byte alignment (FT601 32-bit bus requirement).
# NOTE: Radar commands are already 4 bytes, so this should be a no-op.
remainder = len(data) % 4
if remainder:
data = data + b"\x00" * (4 - remainder)
with self._lock:
try:
written = self._dev.writePipe(0x02, data, raw=True)
return written == len(data)
except (OSError, _Ftd3xxError) as e:
log.error("FT601 write error: %s", e)
return False
def _mock_read(self, size: int) -> bytes:
"""Generate synthetic radar packets (same pattern as FT2232H mock)."""
time.sleep(0.05)
self._mock_frame_num += 1
buf = bytearray()
num_packets = min(NUM_CELLS, size // DATA_PACKET_SIZE)
start_idx = getattr(self, "_mock_seq_idx", 0)
for n in range(num_packets):
idx = (start_idx + n) % NUM_CELLS
rbin = idx // NUM_DOPPLER_BINS
dbin = idx % NUM_DOPPLER_BINS
range_i = int(self._mock_rng.normal(0, 100))
range_q = int(self._mock_rng.normal(0, 100))
if abs(rbin - 20) < 3:
range_i += 5000
range_q += 3000
dop_i = int(self._mock_rng.normal(0, 50))
dop_q = int(self._mock_rng.normal(0, 50))
if abs(rbin - 20) < 3 and abs(dbin - 8) < 2:
dop_i += 8000
dop_q += 4000
detection = 1 if (abs(rbin - 20) < 2 and abs(dbin - 8) < 2) else 0
pkt = bytearray()
pkt.append(HEADER_BYTE)
pkt += struct.pack(">h", np.clip(range_q, -32768, 32767))
pkt += struct.pack(">h", np.clip(range_i, -32768, 32767))
pkt += struct.pack(">h", np.clip(dop_i, -32768, 32767))
pkt += struct.pack(">h", np.clip(dop_q, -32768, 32767))
# Bit 7 = frame_start (sample_counter == 0), bit 0 = detection
det_byte = (detection & 0x01) | (0x80 if idx == 0 else 0x00)
pkt.append(det_byte)
pkt.append(detection & 0x01)
pkt.append(FOOTER_BYTE)
buf += pkt
@@ -788,12 +600,6 @@ class RadarAcquisition(threading.Thread):
if sample.get("detection", 0):
self._frame.detections[rbin, dbin] = 1
self._frame.detection_count += 1
# Accumulate FPGA range profile data (matched-filter output)
# Each sample carries the range_i/range_q for this range bin.
# Accumulate magnitude across Doppler bins for the range profile.
ri = int(sample.get("range_i", 0))
rq = int(sample.get("range_q", 0))
self._frame.range_profile[rbin] += abs(ri) + abs(rq)
self._sample_idx += 1
@@ -801,11 +607,11 @@ class RadarAcquisition(threading.Thread):
self._finalize_frame()
def _finalize_frame(self):
"""Complete frame: push to queue, record."""
"""Complete frame: compute range profile, push to queue, record."""
self._frame.timestamp = time.time()
self._frame.frame_number = self._frame_num
# range_profile is already accumulated from FPGA range_i/range_q
# data in _ingest_sample(). No need to synthesize from doppler magnitude.
# Range profile = sum of magnitude across Doppler bins
self._frame.range_profile = np.sum(self._frame.magnitude, axis=1)
# Push to display queue (drop old if backed up)
try:
9_Firmware/9_3_GUI/test_GUI_V65_Tk.py
+1 -56
View File
@@ -16,7 +16,7 @@ import unittest
import numpy as np
from radar_protocol import (
RadarProtocol, FT2232HConnection, FT601Connection, DataRecorder, RadarAcquisition,
RadarProtocol, FT2232HConnection, DataRecorder, RadarAcquisition,
RadarFrame, StatusResponse, Opcode,
HEADER_BYTE, FOOTER_BYTE, STATUS_HEADER_BYTE,
NUM_RANGE_BINS, NUM_DOPPLER_BINS,
@@ -312,61 +312,6 @@ class TestFT2232HConnection(unittest.TestCase):
self.assertFalse(conn.write(b"\x00\x00\x00\x00"))
class TestFT601Connection(unittest.TestCase):
"""Test mock FT601 connection (mirrors FT2232H tests)."""
def test_mock_open_close(self):
conn = FT601Connection(mock=True)
self.assertTrue(conn.open())
self.assertTrue(conn.is_open)
conn.close()
self.assertFalse(conn.is_open)
def test_mock_read_returns_data(self):
conn = FT601Connection(mock=True)
conn.open()
data = conn.read(4096)
self.assertIsNotNone(data)
self.assertGreater(len(data), 0)
conn.close()
def test_mock_read_contains_valid_packets(self):
"""Mock data should contain parseable data packets."""
conn = FT601Connection(mock=True)
conn.open()
raw = conn.read(4096)
packets = RadarProtocol.find_packet_boundaries(raw)
self.assertGreater(len(packets), 0)
for start, end, ptype in packets:
if ptype == "data":
result = RadarProtocol.parse_data_packet(raw[start:end])
self.assertIsNotNone(result)
conn.close()
def test_mock_write(self):
conn = FT601Connection(mock=True)
conn.open()
cmd = RadarProtocol.build_command(0x01, 1)
self.assertTrue(conn.write(cmd))
conn.close()
def test_write_pads_to_4_bytes(self):
"""FT601 write() should pad data to 4-byte alignment."""
conn = FT601Connection(mock=True)
conn.open()
# 3-byte payload should be padded internally (no error)
self.assertTrue(conn.write(b"\x01\x02\x03"))
conn.close()
def test_read_when_closed(self):
conn = FT601Connection(mock=True)
self.assertIsNone(conn.read())
def test_write_when_closed(self):
conn = FT601Connection(mock=True)
self.assertFalse(conn.write(b"\x00\x00\x00\x00"))
class TestDataRecorder(unittest.TestCase):
"""Test HDF5 recording (skipped if h5py not available)."""
9_Firmware/9_3_GUI/test_v7.py
+26 -17
View File
@@ -58,9 +58,9 @@ class TestRadarSettings(unittest.TestCase):
def test_has_physical_conversion_fields(self):
s = _models().RadarSettings()
self.assertIsInstance(s.range_resolution, float)
self.assertIsInstance(s.range_bin_spacing, float)
self.assertIsInstance(s.velocity_resolution, float)
self.assertGreater(s.range_resolution, 0)
self.assertGreater(s.range_bin_spacing, 0)
self.assertGreater(s.velocity_resolution, 0)
def test_defaults(self):
@@ -432,27 +432,35 @@ class TestWaveformConfig(unittest.TestCase):
self.assertEqual(wc.center_freq_hz, 10.5e9)
self.assertEqual(wc.n_range_bins, 64)
self.assertEqual(wc.n_doppler_bins, 32)
self.assertEqual(wc.chirps_per_subframe, 16)
self.assertEqual(wc.fft_size, 1024)
self.assertEqual(wc.decimation_factor, 16)
def test_range_resolution(self):
"""range_resolution_m should be ~23.98 m/bin (matched filter, 100 MSPS)."""
"""bin_spacing_m should be ~24.0 m/bin with PLFM defaults."""
from v7.models import WaveformConfig
wc = WaveformConfig()
self.assertAlmostEqual(wc.range_resolution_m, 23.983, places=1)
self.assertAlmostEqual(wc.bin_spacing_m, 23.98, places=1)
def test_range_resolution_physical(self):
"""range_resolution_m = c/(2*BW), ~7.5 m at 20 MHz BW."""
from v7.models import WaveformConfig
wc = WaveformConfig()
self.assertAlmostEqual(wc.range_resolution_m, 7.49, places=1)
# 30 MHz BW → 5.0 m resolution
wc30 = WaveformConfig(bandwidth_hz=30e6)
self.assertAlmostEqual(wc30.range_resolution_m, 4.996, places=1)
def test_velocity_resolution(self):
"""velocity_resolution_mps should be ~5.34 m/s/bin (PRI=167us, 16 chirps)."""
"""velocity_resolution_mps should be ~2.67 m/s/bin."""
from v7.models import WaveformConfig
wc = WaveformConfig()
self.assertAlmostEqual(wc.velocity_resolution_mps, 5.343, places=1)
self.assertAlmostEqual(wc.velocity_resolution_mps, 2.67, places=1)
def test_max_range(self):
"""max_range_m = range_resolution * n_range_bins."""
"""max_range_m = bin_spacing * n_range_bins."""
from v7.models import WaveformConfig
wc = WaveformConfig()
self.assertAlmostEqual(wc.max_range_m, wc.range_resolution_m * 64, places=1)
self.assertAlmostEqual(wc.max_range_m, wc.bin_spacing_m * 64, places=1)
def test_max_velocity(self):
"""max_velocity_mps = velocity_resolution * n_doppler_bins / 2."""
@@ -468,8 +476,9 @@ class TestWaveformConfig(unittest.TestCase):
"""Non-default parameters correctly change derived values."""
from v7.models import WaveformConfig
wc1 = WaveformConfig()
wc2 = WaveformConfig(sample_rate_hz=200e6) # double Fs → halve range bin
self.assertAlmostEqual(wc2.range_resolution_m, wc1.range_resolution_m / 2, places=2)
# Matched-filter: bin_spacing = c/(2*fs)*dec — proportional to 1/fs
wc2 = WaveformConfig(sample_rate_hz=200e6) # double fs → halve bin spacing
self.assertAlmostEqual(wc2.bin_spacing_m, wc1.bin_spacing_m / 2, places=2)
def test_zero_center_freq_velocity(self):
"""Zero center freq should cause ZeroDivisionError in velocity calc."""
@@ -927,18 +936,18 @@ class TestExtractTargetsFromFrame(unittest.TestCase):
"""Detection at range bin 10 → range = 10 * range_resolution."""
from v7.processing import extract_targets_from_frame
frame = self._make_frame(det_cells=[(10, 16)]) # dbin=16 = center → vel=0
targets = extract_targets_from_frame(frame, range_resolution=23.983)
targets = extract_targets_from_frame(frame, bin_spacing=23.98)
self.assertEqual(len(targets), 1)
self.assertAlmostEqual(targets[0].range, 10 * 23.983, places=1)
self.assertAlmostEqual(targets[0].range, 10 * 23.98, places=1)
self.assertAlmostEqual(targets[0].velocity, 0.0, places=2)
def test_velocity_sign(self):
"""Doppler bin < center → negative velocity, > center → positive."""
from v7.processing import extract_targets_from_frame
frame = self._make_frame(det_cells=[(5, 10), (5, 20)])
targets = extract_targets_from_frame(frame, velocity_resolution=1.484)
# dbin=10: vel = (10-16)*1.484 = -8.904 (approaching)
# dbin=20: vel = (20-16)*1.484 = +5.936 (receding)
targets = extract_targets_from_frame(frame, velocity_resolution=2.67)
# dbin=10: vel = (10-16)*2.67 = -16.02 (approaching)
# dbin=20: vel = (20-16)*2.67 = +10.68 (receding)
self.assertLess(targets[0].velocity, 0)
self.assertGreater(targets[1].velocity, 0)
@@ -956,7 +965,7 @@ class TestExtractTargetsFromFrame(unittest.TestCase):
pitch=0.0, heading=90.0)
frame = self._make_frame(det_cells=[(10, 16)])
targets = extract_targets_from_frame(
frame, range_resolution=100.0, gps=gps)
frame, bin_spacing=100.0, gps=gps)
# Should be roughly east of radar position
self.assertAlmostEqual(targets[0].latitude, 41.9, places=2)
self.assertGreater(targets[0].longitude, 12.5)
9_Firmware/9_3_GUI/v7/__init__.py
+1 -2
View File
@@ -26,7 +26,6 @@ from .models import (
# Hardware interfaces — production protocol via radar_protocol.py
from .hardware import (
FT2232HConnection,
FT601Connection,
RadarProtocol,
Opcode,
RadarAcquisition,
@@ -90,7 +89,7 @@ __all__ = [ # noqa: RUF022
"USB_AVAILABLE", "FTDI_AVAILABLE", "SCIPY_AVAILABLE",
"SKLEARN_AVAILABLE", "FILTERPY_AVAILABLE",
# hardware — production FPGA protocol
"FT2232HConnection", "FT601Connection", "RadarProtocol", "Opcode",
"FT2232HConnection", "RadarProtocol", "Opcode",
"RadarAcquisition", "RadarFrame", "StatusResponse", "DataRecorder",
"STM32USBInterface",
# processing
9_Firmware/9_3_GUI/v7/dashboard.py
+10 -39
View File
@@ -13,14 +13,13 @@ RadarDashboard is a QMainWindow with six tabs:
6. Settings — Host-side DSP parameters + About section
Uses production radar_protocol.py for all FPGA communication:
- FT2232HConnection for production board (FT2232H USB 2.0)
- FT601Connection for premium board (FT601 USB 3.0) — selectable from GUI
- FT2232HConnection for real hardware
- Unified replay via SoftwareFPGA + ReplayEngine + ReplayWorker
- Mock mode (FT2232HConnection(mock=True)) for development
The old STM32 magic-packet start flow has been removed. FPGA registers
are controlled directly via 4-byte {opcode, addr, value_hi, value_lo}
commands sent over FT2232H or FT601.
commands sent over FT2232H.
"""
from __future__ import annotations
@@ -56,7 +55,6 @@ from .models import (
)
from .hardware import (
FT2232HConnection,
FT601Connection,
RadarProtocol,
RadarFrame,
StatusResponse,
@@ -144,7 +142,7 @@ class RadarDashboard(QMainWindow):
)
# Hardware interfaces — production protocol
self._connection: FT2232HConnection | FT601Connection | None = None
self._connection: FT2232HConnection | None = None
self._stm32 = STM32USBInterface()
self._recorder = DataRecorder()
@@ -366,7 +364,7 @@ class RadarDashboard(QMainWindow):
# Row 0: connection mode + device combos + buttons
ctrl_layout.addWidget(QLabel("Mode:"), 0, 0)
self._mode_combo = QComboBox()
self._mode_combo.addItems(["Mock", "Live", "Replay"])
self._mode_combo.addItems(["Mock", "Live FT2232H", "Replay"])
self._mode_combo.setCurrentIndex(0)
ctrl_layout.addWidget(self._mode_combo, 0, 1)
@@ -379,13 +377,6 @@ class RadarDashboard(QMainWindow):
refresh_btn.clicked.connect(self._refresh_devices)
ctrl_layout.addWidget(refresh_btn, 0, 4)
# USB Interface selector (production FT2232H / premium FT601)
ctrl_layout.addWidget(QLabel("USB Interface:"), 0, 5)
self._usb_iface_combo = QComboBox()
self._usb_iface_combo.addItems(["FT2232H (Production)", "FT601 (Premium)"])
self._usb_iface_combo.setCurrentIndex(0)
ctrl_layout.addWidget(self._usb_iface_combo, 0, 6)
self._start_btn = QPushButton("Start Radar")
self._start_btn.setStyleSheet(
f"QPushButton {{ background-color: {DARK_SUCCESS}; color: white; font-weight: bold; }}"
@@ -1010,8 +1001,7 @@ class RadarDashboard(QMainWindow):
self._conn_ft2232h = self._make_status_label("FT2232H")
self._conn_stm32 = self._make_status_label("STM32 USB")
self._conn_usb_label = QLabel("USB Data:")
conn_layout.addWidget(self._conn_usb_label, 0, 0)
conn_layout.addWidget(QLabel("FT2232H:"), 0, 0)
conn_layout.addWidget(self._conn_ft2232h, 0, 1)
conn_layout.addWidget(QLabel("STM32 USB:"), 1, 0)
conn_layout.addWidget(self._conn_stm32, 1, 1)
@@ -1177,7 +1167,7 @@ class RadarDashboard(QMainWindow):
about_lbl = QLabel(
"<b>AERIS-10 Radar System V7</b><br>"
"PyQt6 Edition with Embedded Leaflet Map<br><br>"
"<b>Data Interface:</b> FT2232H USB 2.0 (production) / FT601 USB 3.0 (premium)<br>"
"<b>Data Interface:</b> FT2232H USB 2.0 (production protocol)<br>"
"<b>FPGA Protocol:</b> 4-byte register commands, 0xAA/0xBB packets<br>"
"<b>Map:</b> OpenStreetMap + Leaflet.js<br>"
"<b>Framework:</b> PyQt6 + QWebEngine<br>"
@@ -1234,7 +1224,7 @@ class RadarDashboard(QMainWindow):
# =====================================================================
def _send_fpga_cmd(self, opcode: int, value: int):
"""Send a 4-byte register command to the FPGA via USB (FT2232H or FT601)."""
"""Send a 4-byte register command to the FPGA via FT2232H."""
if self._connection is None or not self._connection.is_open:
logger.warning(f"Cannot send 0x{opcode:02X}={value}: no connection")
return
@@ -1297,26 +1287,16 @@ class RadarDashboard(QMainWindow):
if "Mock" in mode:
self._replay_mode = False
iface = self._usb_iface_combo.currentText()
if "FT601" in iface:
self._connection = FT601Connection(mock=True)
else:
self._connection = FT2232HConnection(mock=True)
self._connection = FT2232HConnection(mock=True)
if not self._connection.open():
QMessageBox.critical(self, "Error", "Failed to open mock connection.")
return
elif "Live" in mode:
self._replay_mode = False
iface = self._usb_iface_combo.currentText()
if "FT601" in iface:
self._connection = FT601Connection(mock=False)
iface_name = "FT601"
else:
self._connection = FT2232HConnection(mock=False)
iface_name = "FT2232H"
self._connection = FT2232HConnection(mock=False)
if not self._connection.open():
QMessageBox.critical(self, "Error",
f"Failed to open {iface_name}. Check USB connection.")
"Failed to open FT2232H. Check USB connection.")
return
elif "Replay" in mode:
self._replay_mode = True
@@ -1388,7 +1368,6 @@ class RadarDashboard(QMainWindow):
self._start_btn.setEnabled(False)
self._stop_btn.setEnabled(True)
self._mode_combo.setEnabled(False)
self._usb_iface_combo.setEnabled(False)
self._demo_btn_main.setEnabled(False)
self._demo_btn_map.setEnabled(False)
n_frames = self._replay_engine.total_frames
@@ -1438,7 +1417,6 @@ class RadarDashboard(QMainWindow):
self._start_btn.setEnabled(False)
self._stop_btn.setEnabled(True)
self._mode_combo.setEnabled(False)
self._usb_iface_combo.setEnabled(False)
self._demo_btn_main.setEnabled(False)
self._demo_btn_map.setEnabled(False)
self._status_label_main.setText(f"Status: Running ({mode})")
@@ -1484,7 +1462,6 @@ class RadarDashboard(QMainWindow):
self._start_btn.setEnabled(True)
self._stop_btn.setEnabled(False)
self._mode_combo.setEnabled(True)
self._usb_iface_combo.setEnabled(True)
self._demo_btn_main.setEnabled(True)
self._demo_btn_map.setEnabled(True)
self._status_label_main.setText("Status: Radar stopped")
@@ -1977,12 +1954,6 @@ class RadarDashboard(QMainWindow):
self._set_conn_indicator(self._conn_ft2232h, conn_open)
self._set_conn_indicator(self._conn_stm32, self._stm32.is_open)
# Update USB label to reflect which interface is active
if isinstance(self._connection, FT601Connection):
self._conn_usb_label.setText("FT601:")
else:
self._conn_usb_label.setText("FT2232H:")
gps_count = self._gps_packet_count
if self._gps_worker:
gps_count = self._gps_worker.gps_count
9_Firmware/9_3_GUI/v7/hardware.py
+2 -4
View File
@@ -25,7 +25,6 @@ if USB_AVAILABLE:
sys.path.insert(0, os.path.join(os.path.dirname(__file__), ".."))
from radar_protocol import ( # noqa: F401 — re-exported for v7 package
FT2232HConnection,
FT601Connection,
RadarProtocol,
Opcode,
RadarAcquisition,
@@ -47,9 +46,8 @@ class STM32USBInterface:
Used ONLY for receiving GPS data from the MCU.
FPGA register commands are sent via the USB data interface — either
FT2232HConnection (production) or FT601Connection (premium), both
from radar_protocol.py. The old send_start_flag() / send_settings()
FPGA register commands are sent via FT2232H (see FT2232HConnection
from radar_protocol.py). The old send_start_flag() / send_settings()
methods have been removed — they used an incompatible magic-packet
protocol that the FPGA does not understand.
"""
9_Firmware/9_3_GUI/v7/map_widget.py
+1 -1
View File
@@ -98,7 +98,7 @@ class RadarMapWidget(QWidget):
)
self._targets: list[RadarTarget] = []
self._pending_targets: list[RadarTarget] | None = None
self._coverage_radius = 1_536 # metres (64 bins x ~24 m/bin)
self._coverage_radius = 1_536 # metres (64 bins x 24 m, 3 km mode)
self._tile_server = TileServer.OPENSTREETMAP
self._show_coverage = True
self._show_trails = False
9_Firmware/9_3_GUI/v7/models.py
+38 -31
View File
@@ -105,15 +105,15 @@ class RadarSettings:
tab and Opcode enum in radar_protocol.py. This dataclass holds only
host-side display/map settings and physical-unit conversion factors.
range_resolution and velocity_resolution should be calibrated to
range_bin_spacing and velocity_resolution should be calibrated to
the actual waveform parameters.
"""
system_frequency: float = 10.5e9 # Hz (carrier, used for velocity calc)
range_resolution: float = 24.0 # Meters per range bin (c/(2*Fs)*decim)
velocity_resolution: float = 1.0 # m/s per Doppler bin (calibrate to waveform)
max_distance: float = 1536 # Max detection range (m)
map_size: float = 2000 # Map display size (m)
coverage_radius: float = 1536 # Map coverage radius (m)
system_frequency: float = 10.5e9 # Hz (PLFM TX LO, verified from ADF4382 config)
range_bin_spacing: float = 24.0 # Meters per decimated range bin (c/(2*100MSPS)*16)
velocity_resolution: float = 2.67 # m/s per Doppler bin (lam/(2*32*167us))
max_distance: float = 1536 # Max detection range (m) -- 64 bins x 24 m (3 km mode)
map_size: float = 1536 # Map display size (m)
coverage_radius: float = 1536 # Map coverage radius (m)
@dataclass
@@ -196,54 +196,61 @@ class TileServer(Enum):
class WaveformConfig:
"""Physical waveform parameters for converting bins to SI units.
Encapsulates the radar waveform so that range/velocity resolution
Encapsulates the PLFM radar waveform so that range/velocity resolution
can be derived automatically instead of hardcoded in RadarSettings.
Defaults match the AERIS-10 production system parameters from
radar_scene.py / plfm_chirp_controller.v:
100 MSPS DDC output, 20 MHz chirp BW, 30 us long chirp,
167 us long-chirp PRI, X-band 10.5 GHz carrier.
Defaults match the PLFM hardware: 100 MSPS post-DDC processing rate,
20 MHz chirp bandwidth, 30 us long chirp, 167 us PRI, 10.5 GHz carrier.
The receiver uses matched-filter pulse compression (NOT deramped FMCW),
so range-per-bin = c / (2 * fs_processing) * decimation_factor.
"""
sample_rate_hz: float = 100e6 # DDC output I/Q rate (matched filter input)
bandwidth_hz: float = 20e6 # Chirp bandwidth (not used in range calc;
# retained for time-bandwidth product / display)
chirp_duration_s: float = 30e-6 # Long chirp ramp time
sample_rate_hz: float = 100e6 # Post-DDC processing rate (400 MSPS / 4)
bandwidth_hz: float = 20e6 # Chirp bandwidth (Phase 1 target: 30 MHz)
chirp_duration_s: float = 30e-6 # Long chirp ramp (informational only)
pri_s: float = 167e-6 # Pulse repetition interval (chirp + listen)
center_freq_hz: float = 10.5e9 # Carrier frequency (radar_scene.py: F_CARRIER)
n_range_bins: int = 64 # After decimation
n_doppler_bins: int = 32 # Total Doppler bins (2 sub-frames x 16)
chirps_per_subframe: int = 16 # Chirps in one Doppler sub-frame
center_freq_hz: float = 10.5e9 # TX LO carrier (verified: ADF4382 config)
n_range_bins: int = 64 # After decimation (3 km mode)
n_doppler_bins: int = 32 # After Doppler FFT
fft_size: int = 1024 # Pre-decimation FFT length
decimation_factor: int = 16 # 1024 → 64
@property
def range_resolution_m(self) -> float:
"""Meters per decimated range bin (matched-filter pulse compression).
def bin_spacing_m(self) -> float:
"""Meters per decimated range bin (matched-filter receiver).
For FFT-based matched filtering, each IFFT output bin spans
c / (2 * Fs) in range, where Fs is the I/Q sample rate at the
matched-filter input (DDC output). After decimation the bin
spacing grows by *decimation_factor*.
For matched-filter pulse compression: bin spacing = c / (2 * fs).
After decimation the bin spacing grows by *decimation_factor*.
This is independent of chirp bandwidth (BW affects physical
resolution, not bin spacing).
"""
c = 299_792_458.0
raw_bin = c / (2.0 * self.sample_rate_hz)
return raw_bin * self.decimation_factor
@property
def velocity_resolution_mps(self) -> float:
"""m/s per Doppler bin.
def range_resolution_m(self) -> float:
"""Physical range resolution in meters, set by chirp bandwidth.
lambda / (2 * chirps_per_subframe * PRI), matching radar_scene.py.
range_resolution = c / (2 * BW).
At 20 MHz BW → 7.5 m; at 30 MHz BW → 5.0 m.
This is distinct from bin_spacing_m (which depends on sample rate
and decimation factor, not bandwidth).
"""
c = 299_792_458.0
return c / (2.0 * self.bandwidth_hz)
@property
def velocity_resolution_mps(self) -> float:
"""m/s per Doppler bin. lambda / (2 * n_doppler * PRI)."""
c = 299_792_458.0
wavelength = c / self.center_freq_hz
return wavelength / (2.0 * self.chirps_per_subframe * self.pri_s)
return wavelength / (2.0 * self.n_doppler_bins * self.pri_s)
@property
def max_range_m(self) -> float:
"""Maximum unambiguous range in meters."""
return self.range_resolution_m * self.n_range_bins
return self.bin_spacing_m * self.n_range_bins
@property
def max_velocity_mps(self) -> float:
9_Firmware/9_3_GUI/v7/processing.py
+4 -4
View File
@@ -490,7 +490,7 @@ def polar_to_geographic(
def extract_targets_from_frame(
frame,
range_resolution: float = 1.0,
bin_spacing: float = 1.0,
velocity_resolution: float = 1.0,
gps: GPSData | None = None,
) -> list[RadarTarget]:
@@ -503,8 +503,8 @@ def extract_targets_from_frame(
----------
frame : RadarFrame
Frame with populated ``detections``, ``magnitude``, ``range_doppler_i/q``.
range_resolution : float
Meters per range bin.
bin_spacing : float
Meters per range bin (bin spacing, NOT bandwidth-limited resolution).
velocity_resolution : float
m/s per Doppler bin.
gps : GPSData | None
@@ -525,7 +525,7 @@ def extract_targets_from_frame(
mag = float(frame.magnitude[rbin, dbin])
snr = 10.0 * math.log10(max(mag, 1.0)) if mag > 0 else 0.0
range_m = float(rbin) * range_resolution
range_m = float(rbin) * bin_spacing
velocity_ms = float(dbin - doppler_center) * velocity_resolution
lat, lon, azimuth, elevation = 0.0, 0.0, 0.0, 0.0
9_Firmware/9_3_GUI/v7/workers.py
+5 -5
View File
@@ -169,7 +169,7 @@ class RadarDataWorker(QThread):
The FPGA already does: FFT, MTI, CFAR, DC notch.
Host-side DSP adds: clustering, tracking, geo-coordinate mapping.
Bin-to-physical conversion uses RadarSettings.range_resolution
Bin-to-physical conversion uses RadarSettings.range_bin_spacing
and velocity_resolution (should be calibrated to actual waveform).
"""
targets: list[RadarTarget] = []
@@ -180,7 +180,7 @@ class RadarDataWorker(QThread):
# Extract detections from FPGA CFAR flags
det_indices = np.argwhere(frame.detections > 0)
r_res = self._settings.range_resolution
r_res = self._settings.range_bin_spacing
v_res = self._settings.velocity_resolution
for idx in det_indices:
@@ -334,7 +334,7 @@ class TargetSimulator(QObject):
self._add_random_target()
def _add_random_target(self):
range_m = random.uniform(50, 1400)
range_m = random.uniform(5000, 40000)
azimuth = random.uniform(0, 360)
velocity = random.uniform(-100, 100)
elevation = random.uniform(-5, 45)
@@ -368,7 +368,7 @@ class TargetSimulator(QObject):
for t in self._targets:
new_range = t.range - t.velocity * 0.5
if new_range < 10 or new_range > 1536:
if new_range < 50 or new_range > 1536:
continue # target exits coverage — drop it
new_vel = max(-150, min(150, t.velocity + random.uniform(-2, 2)))
@@ -559,7 +559,7 @@ class ReplayWorker(QThread):
# Target extraction
targets = self._extract_targets(
frame,
range_resolution=self._waveform.range_resolution_m,
bin_spacing=self._waveform.bin_spacing_m,
velocity_resolution=self._waveform.velocity_resolution_mps,
gps=self._gps,
)
9_Firmware/tests/cross_layer/adar1000_vm_reference.py
-216
View File
@@ -1,216 +0,0 @@
"""ADAR1000 vector-modulator ground-truth table and firmware parser.
This module is a pure data + helpers library imported by the cross-layer
test suite (`9_Firmware/tests/cross_layer/test_cross_layer_contract.py`,
class `TestTier2Adar1000VmTableGroundTruth`). It has no CLI entry point
and no side effects on import beyond the structural assertion on the
table length.
Ground-truth source
-------------------
The 128-entry `(I, Q)` byte pairs below are transcribed from the ADAR1000
datasheet Rev. B, Tables 13-16, page 34 ("Phase Shifter Programming"),
which is the primary normative reference. The same values appear in the
Analog Devices Linux beamformer driver
(`drivers/iio/beamformer/adar1000.c`, `adar1000_phase_values[]`) and were
cross-checked against that driver as a secondary, independent
transcription. The byte values are factual data (5-bit unsigned magnitude
in bits[4:0], polarity bit at bit[5], bits[7:6] reserved zero); no
copyrightable creative expression. Only the datasheet is the
licensing-relevant source.
PLFM_RADAR firmware indexing convention
---------------------------------------
`adarSetRxPhase` / `adarSetTxPhase` in
`9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/ADAR1000_Manager.cpp`
write `VM_I[phase % 128]` and `VM_Q[phase % 128]` to the chip. Each index
N corresponds to commanded beam phase `N * 360/128 = N * 2.8125 deg`. The
ADI table is also on a uniform 2.8125 deg grid (verified by
`check_uniform_2p8125_deg_step` below), so a 1:1 mapping is correct:
PLFM index N == ADI table row N.
"""
from __future__ import annotations
import re
# ----------------------------------------------------------------------------
# Ground truth: ADAR1000 datasheet Rev. B Tables 13-16 p.34
# Each entry: (angle_int_deg, angle_frac_x10000, vm_byte_I, vm_byte_Q)
# ----------------------------------------------------------------------------
GROUND_TRUTH: list[tuple[int, int, int, int]] = [
(0, 0, 0x3F, 0x20), (2, 8125, 0x3F, 0x21), (5, 6250, 0x3F, 0x23),
(8, 4375, 0x3F, 0x24), (11, 2500, 0x3F, 0x26), (14, 625, 0x3E, 0x27),
(16, 8750, 0x3E, 0x28), (19, 6875, 0x3D, 0x2A), (22, 5000, 0x3D, 0x2B),
(25, 3125, 0x3C, 0x2D), (28, 1250, 0x3C, 0x2E), (30, 9375, 0x3B, 0x2F),
(33, 7500, 0x3A, 0x30), (36, 5625, 0x39, 0x31), (39, 3750, 0x38, 0x33),
(42, 1875, 0x37, 0x34), (45, 0, 0x36, 0x35), (47, 8125, 0x35, 0x36),
(50, 6250, 0x34, 0x37), (53, 4375, 0x33, 0x38), (56, 2500, 0x32, 0x38),
(59, 625, 0x30, 0x39), (61, 8750, 0x2F, 0x3A), (64, 6875, 0x2E, 0x3A),
(67, 5000, 0x2C, 0x3B), (70, 3125, 0x2B, 0x3C), (73, 1250, 0x2A, 0x3C),
(75, 9375, 0x28, 0x3C), (78, 7500, 0x27, 0x3D), (81, 5625, 0x25, 0x3D),
(84, 3750, 0x24, 0x3D), (87, 1875, 0x22, 0x3D), (90, 0, 0x21, 0x3D),
(92, 8125, 0x01, 0x3D), (95, 6250, 0x03, 0x3D), (98, 4375, 0x04, 0x3D),
(101, 2500, 0x06, 0x3D), (104, 625, 0x07, 0x3C), (106, 8750, 0x08, 0x3C),
(109, 6875, 0x0A, 0x3C), (112, 5000, 0x0B, 0x3B), (115, 3125, 0x0D, 0x3A),
(118, 1250, 0x0E, 0x3A), (120, 9375, 0x0F, 0x39), (123, 7500, 0x11, 0x38),
(126, 5625, 0x12, 0x38), (129, 3750, 0x13, 0x37), (132, 1875, 0x14, 0x36),
(135, 0, 0x16, 0x35), (137, 8125, 0x17, 0x34), (140, 6250, 0x18, 0x33),
(143, 4375, 0x19, 0x31), (146, 2500, 0x19, 0x30), (149, 625, 0x1A, 0x2F),
(151, 8750, 0x1B, 0x2E), (154, 6875, 0x1C, 0x2D), (157, 5000, 0x1C, 0x2B),
(160, 3125, 0x1D, 0x2A), (163, 1250, 0x1E, 0x28), (165, 9375, 0x1E, 0x27),
(168, 7500, 0x1E, 0x26), (171, 5625, 0x1F, 0x24), (174, 3750, 0x1F, 0x23),
(177, 1875, 0x1F, 0x21), (180, 0, 0x1F, 0x20), (182, 8125, 0x1F, 0x01),
(185, 6250, 0x1F, 0x03), (188, 4375, 0x1F, 0x04), (191, 2500, 0x1F, 0x06),
(194, 625, 0x1E, 0x07), (196, 8750, 0x1E, 0x08), (199, 6875, 0x1D, 0x0A),
(202, 5000, 0x1D, 0x0B), (205, 3125, 0x1C, 0x0D), (208, 1250, 0x1C, 0x0E),
(210, 9375, 0x1B, 0x0F), (213, 7500, 0x1A, 0x10), (216, 5625, 0x19, 0x11),
(219, 3750, 0x18, 0x13), (222, 1875, 0x17, 0x14), (225, 0, 0x16, 0x15),
(227, 8125, 0x15, 0x16), (230, 6250, 0x14, 0x17), (233, 4375, 0x13, 0x18),
(236, 2500, 0x12, 0x18), (239, 625, 0x10, 0x19), (241, 8750, 0x0F, 0x1A),
(244, 6875, 0x0E, 0x1A), (247, 5000, 0x0C, 0x1B), (250, 3125, 0x0B, 0x1C),
(253, 1250, 0x0A, 0x1C), (255, 9375, 0x08, 0x1C), (258, 7500, 0x07, 0x1D),
(261, 5625, 0x05, 0x1D), (264, 3750, 0x04, 0x1D), (267, 1875, 0x02, 0x1D),
(270, 0, 0x01, 0x1D), (272, 8125, 0x21, 0x1D), (275, 6250, 0x23, 0x1D),
(278, 4375, 0x24, 0x1D), (281, 2500, 0x26, 0x1D), (284, 625, 0x27, 0x1C),
(286, 8750, 0x28, 0x1C), (289, 6875, 0x2A, 0x1C), (292, 5000, 0x2B, 0x1B),
(295, 3125, 0x2D, 0x1A), (298, 1250, 0x2E, 0x1A), (300, 9375, 0x2F, 0x19),
(303, 7500, 0x31, 0x18), (306, 5625, 0x32, 0x18), (309, 3750, 0x33, 0x17),
(312, 1875, 0x34, 0x16), (315, 0, 0x36, 0x15), (317, 8125, 0x37, 0x14),
(320, 6250, 0x38, 0x13), (323, 4375, 0x39, 0x11), (326, 2500, 0x39, 0x10),
(329, 625, 0x3A, 0x0F), (331, 8750, 0x3B, 0x0E), (334, 6875, 0x3C, 0x0D),
(337, 5000, 0x3C, 0x0B), (340, 3125, 0x3D, 0x0A), (343, 1250, 0x3E, 0x08),
(345, 9375, 0x3E, 0x07), (348, 7500, 0x3E, 0x06), (351, 5625, 0x3F, 0x04),
(354, 3750, 0x3F, 0x03), (357, 1875, 0x3F, 0x01),
]
assert len(GROUND_TRUTH) == 128, f"GROUND_TRUTH must have 128 entries, has {len(GROUND_TRUTH)}"
VM_I_REF: list[int] = [row[2] for row in GROUND_TRUTH]
VM_Q_REF: list[int] = [row[3] for row in GROUND_TRUTH]
# ----------------------------------------------------------------------------
# Structural-invariant checks on the embedded ground-truth transcription.
# These defend against typos during the copy-paste from the datasheet / ADI
# driver. Each function returns a list of error strings (empty == pass) so
# callers (the pytest class) can assert-on-empty with a useful message.
# ----------------------------------------------------------------------------
def check_byte_format(label: str, table: list[int]) -> list[str]:
"""Each byte must have bits[7:6] == 0 (reserved)."""
errors = []
for i, byte in enumerate(table):
if byte & 0xC0:
errors.append(f"{label}[{i}]=0x{byte:02X}: reserved bits[7:6] non-zero")
return errors
def check_uniform_2p8125_deg_step() -> list[str]:
"""Angles must form a uniform 2.8125 deg grid: angle[N] == N * 2.8125."""
errors = []
for i, (deg_int, deg_frac, _, _) in enumerate(GROUND_TRUTH):
# angle in units of 1/10000 degree; 2.8125 deg = 28125/10000 exactly
angle_e4 = deg_int * 10000 + deg_frac
expected_e4 = i * 28125
if angle_e4 != expected_e4:
errors.append(
f"GROUND_TRUTH[{i}]: angle {deg_int}.{deg_frac:04d} deg "
f"(={angle_e4}/10000) != expected {expected_e4}/10000 "
f"(=i*2.8125)"
)
return errors
def check_quadrant_symmetry() -> list[str]:
"""Angle and angle+180 deg must have inverted polarity bits but identical
magnitudes. Index offset 64 corresponds to 180 deg on the 128-step grid.
Exemption: when magnitude is zero the polarity bit is physically
meaningless (sign of zero is undefined for the IQ phasor projection).
The datasheet uses POL=1 for both 0 and 180 deg Q components (both
encode Q=0). Skip the polarity assertion for zero-magnitude entries.
"""
errors = []
POL = 0x20
MAG = 0x1F
for i in range(64):
j = i + 64
mag_i_a, mag_i_b = VM_I_REF[i] & MAG, VM_I_REF[j] & MAG
if mag_i_a != mag_i_b:
errors.append(
f"VM_I[{i}]=0x{VM_I_REF[i]:02X} vs VM_I[{j}]=0x{VM_I_REF[j]:02X}: "
f"180 deg pair has different magnitude"
)
if mag_i_a != 0 and (VM_I_REF[i] & POL) == (VM_I_REF[j] & POL):
errors.append(
f"VM_I[{i}]=0x{VM_I_REF[i]:02X} vs VM_I[{j}]=0x{VM_I_REF[j]:02X}: "
f"180 deg pair has same polarity (should be inverted, mag={mag_i_a})"
)
mag_q_a, mag_q_b = VM_Q_REF[i] & MAG, VM_Q_REF[j] & MAG
if mag_q_a != mag_q_b:
errors.append(
f"VM_Q[{i}]=0x{VM_Q_REF[i]:02X} vs VM_Q[{j}]=0x{VM_Q_REF[j]:02X}: "
f"180 deg pair has different magnitude"
)
if mag_q_a != 0 and (VM_Q_REF[i] & POL) == (VM_Q_REF[j] & POL):
errors.append(
f"VM_Q[{i}]=0x{VM_Q_REF[i]:02X} vs VM_Q[{j}]=0x{VM_Q_REF[j]:02X}: "
f"180 deg pair has same polarity (should be inverted, mag={mag_q_a})"
)
return errors
def check_cardinal_points() -> list[str]:
"""Spot-check cardinal phase points against datasheet expectations."""
errors = []
expectations = [
(0, 0x3F, 0x20, "0 deg: max +I, ~zero Q"),
(32, 0x21, 0x3D, "90 deg: ~zero I, max +Q"),
(64, 0x1F, 0x20, "180 deg: max -I, ~zero Q"),
(96, 0x01, 0x1D, "270 deg: ~zero I, max -Q"),
]
for idx, exp_i, exp_q, desc in expectations:
if VM_I_REF[idx] != exp_i or VM_Q_REF[idx] != exp_q:
errors.append(
f"index {idx} ({desc}): expected (0x{exp_i:02X}, 0x{exp_q:02X}), "
f"got (0x{VM_I_REF[idx]:02X}, 0x{VM_Q_REF[idx]:02X})"
)
return errors
# ----------------------------------------------------------------------------
# Parse VM_I[] / VM_Q[] from firmware C++ source.
# ----------------------------------------------------------------------------
ARRAY_RE = re.compile(
r"const\s+uint8_t\s+ADAR1000Manager::(?P<name>VM_I|VM_Q|VM_GAIN)\s*"
r"\[\s*128\s*\]\s*=\s*\{(?P<body>[^}]*)\}\s*;",
re.DOTALL,
)
HEX_RE = re.compile(r"0[xX][0-9a-fA-F]{1,2}")
def parse_array(source: str, name: str) -> list[int] | None:
"""Extract a 128-entry uint8_t array from C++ source by name.
Returns None if the array is not found. Returns a list (possibly shorter
than 128) of the parsed bytes if found; caller is responsible for length
validation.
LIMITATION (intentional, see PR fix/adar1000-vm-tables review finding #2):
ARRAY_RE uses `[^}]*` for the body, which terminates at the first `}`.
This is sufficient for the *flat* `const uint8_t NAME[128] = { ... };`
declarations VM_I/VM_Q use today, but it would mis-parse if the array
body ever contained nested braces (e.g. designated initialisers, struct
aggregates, or macro-expansions producing braces). If the firmware ever
needs such a form for the VM tables, replace ARRAY_RE with a balanced
brace-counting parser. Until then, the current regex is preferred for
its simplicity and the round-trip tests will catch any silent breakage.
"""
for m in ARRAY_RE.finditer(source):
if m.group("name") != name:
continue
body = m.group("body")
body = re.sub(r"//[^\n]*", "", body)
body = re.sub(r"/\*.*?\*/", "", body, flags=re.DOTALL)
return [int(tok, 16) for tok in HEX_RE.findall(body)]
return None
9_Firmware/tests/cross_layer/contract_parser.py
+57 -43
View File
@@ -188,7 +188,7 @@ def parse_python_data_packet_fields(filepath: Path | None = None) -> list[DataPa
width_bits=size * 8
))
# Match detection = raw[9] & 0x01 (direct access)
# Match detection = raw[9] & 0x01
for m in re.finditer(r'(\w+)\s*=\s*raw\[(\d+)\]\s*&\s*(0x[0-9a-fA-F]+|\d+)', body):
name = m.group(1)
offset = int(m.group(2))
@@ -196,24 +196,6 @@ def parse_python_data_packet_fields(filepath: Path | None = None) -> list[DataPa
name=name, byte_start=offset, byte_end=offset, width_bits=1
))
# Match intermediate variable pattern: var = raw[N], then field = var & MASK
for m in re.finditer(r'(\w+)\s*=\s*raw\[(\d+)\]', body):
var_name = m.group(1)
offset = int(m.group(2))
# Find fields derived from this intermediate variable
for m2 in re.finditer(
rf'(\w+)\s*=\s*(?:\({var_name}\s*>>\s*\d+\)\s*&|{var_name}\s*&)\s*'
r'(0x[0-9a-fA-F]+|\d+)',
body,
):
name = m2.group(1)
# Skip if already captured by direct raw[] access pattern
if not any(f.name == name for f in fields):
fields.append(DataPacketField(
name=name, byte_start=offset, byte_end=offset,
width_bits=1
))
fields.sort(key=lambda f: f.byte_start)
return fields
@@ -515,7 +497,6 @@ def count_concat_bits(concat_expr: str, port_widths: dict[str, int]) -> ConcatWi
# Unknown width — flag it
fragments.append((part, -1))
total = -1 # Can't compute
break
return ConcatWidth(
total_bits=total,
@@ -602,28 +583,12 @@ def parse_verilog_data_mux(
for m in re.finditer(
r"5'd(\d+)\s*:\s*data_pkt_byte\s*=\s*(.+?);",
mux_body, re.DOTALL
mux_body
):
idx = int(m.group(1))
expr = m.group(2).strip()
entries.append((idx, expr))
# Helper: extract the dominant signal name from a mux expression.
# Handles direct refs like ``range_profile_cap[31:24]``, ternaries
# like ``stream_doppler_en ? doppler_real_cap[15:8] : 8'd0``, and
# concat-ternaries like ``stream_cfar_en ? {…, cfar_detection_cap} : …``.
def _extract_signal(expr: str) -> str | None:
# If it's a ternary, use the true-branch to find the data signal
tern = re.match(r'\w+\s*\?\s*(.+?)\s*:\s*.+', expr, re.DOTALL)
target = tern.group(1) if tern else expr
# Look for a known data signal (xxx_cap pattern or cfar_detection_cap)
cap_match = re.search(r'(\w+_cap)\b', target)
if cap_match:
return cap_match.group(1)
# Fall back to first identifier before a bit-select
sig_match = re.match(r'(\w+?)(?:\[|$)', target)
return sig_match.group(1) if sig_match else None
# Group consecutive bytes by signal root name
fields: list[DataPacketField] = []
i = 0
@@ -633,21 +598,22 @@ def parse_verilog_data_mux(
i += 1
continue
signal = _extract_signal(expr)
if not signal:
# Extract signal name (e.g., range_profile_cap from range_profile_cap[31:24])
sig_match = re.match(r'(\w+?)(?:\[|$)', expr)
if not sig_match:
i += 1
continue
signal = sig_match.group(1)
start_byte = idx
end_byte = idx
# Find consecutive bytes of the same signal
j = i + 1
while j < len(entries):
_next_idx, next_expr = entries[j]
next_sig = _extract_signal(next_expr)
if next_sig == signal:
end_byte = _next_idx
next_idx, next_expr = entries[j]
if next_expr.startswith(signal):
end_byte = next_idx
j += 1
else:
break
@@ -827,3 +793,51 @@ def parse_stm32_gpio_init(filepath: Path | None = None) -> list[GpioPin]:
))
return pins
# ===================================================================
# FPGA radar_params.vh parser
# ===================================================================
def parse_radar_params_vh() -> dict[str, int]:
"""
Parse `define values from radar_params.vh.
Returns dict like {"RP_FFT_SIZE": 1024, "RP_DECIMATION_FACTOR": 16, ...}.
Only parses defines with simple integer or Verilog literal values.
Skips bit-width prefixed literals (e.g. 2'b00) — returns the numeric value.
"""
path = FPGA_DIR / "radar_params.vh"
text = path.read_text()
params: dict[str, int] = {}
for m in re.finditer(
r'`define\s+(RP_\w+)\s+(\S+)', text
):
name = m.group(1)
val_str = m.group(2).rstrip()
# Skip non-numeric defines (like RADAR_PARAMS_VH guard)
if name == "RADAR_PARAMS_VH":
continue
# Handle Verilog bit-width literals: 2'b00, 8'h30, etc.
verilog_lit = re.match(r"\d+'([bhd])(\w+)", val_str)
if verilog_lit:
base_char = verilog_lit.group(1)
digits = verilog_lit.group(2)
base = {"b": 2, "h": 16, "d": 10}[base_char]
params[name] = int(digits, base)
continue
# Handle parenthesized expressions like (`RP_X * `RP_Y)
if "(" in val_str or "`" in val_str:
continue # Skip computed defines
# Plain integer
try:
params[name] = int(val_str)
except ValueError:
continue
return params
9_Firmware/tests/cross_layer/tb_cross_layer_ft2232h.v
+2 -4
View File
@@ -620,10 +620,8 @@ module tb_cross_layer_ft2232h;
"Data pkt: byte 7 = 0x56 (doppler_imag MSB)");
check(captured_bytes[8] === 8'h78,
"Data pkt: byte 8 = 0x78 (doppler_imag LSB)");
// Byte 9 = {frame_start, 6'b0, cfar_detection}
// After reset sample_counter==0, so frame_start=1 → 0x81
check(captured_bytes[9] === 8'h81,
"Data pkt: byte 9 = 0x81 (frame_start=1, cfar_detection=1)");
check(captured_bytes[9] === 8'h01,
"Data pkt: byte 9 = 0x01 (cfar_detection=1)");
check(captured_bytes[10] === 8'h55,
"Data pkt: byte 10 = 0x55 (footer)");
9_Firmware/tests/cross_layer/test_cross_layer_contract.py
+278 -888
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CONTRIBUTING.md
+100 -69
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@@ -5,109 +5,140 @@ for getting a change reviewed and merged.
## Getting started
1. Fork the repository and create a topic branch from `develop`. The `main` branch is for production releases only.
2. Keep generated outputs (Vivado projects, bitstreams, build logs) out of version control.
### Security Mandate: Package Installation
Due to supply chain attack risks, **ALL package installations MUST use the `sfw` (secure firewall) prefix**.
- Python: `sfw uv pip install <package>` (Do not use raw pip)
- Node/JS: `sfw npm install <package>`
- Rust/Cargo: `sfw cargo <command>`
Never run bare package installation commands without the `sfw` prefix.
1. Fork the repository and create a topic branch from `develop`.
2. Keep generated outputs (Vivado projects, bitstreams, build logs)
out of version control — the `.gitignore` already covers most of
these.
## Repository layout
| Path | Contents |
|------|----------|
| `4_Schematics and Boards Layout/` | KiCad schematics, Gerbers, BOM/CPL |
| `9_Firmware/9_1_Microcontroller/` | STM32 MCU C/C++ firmware and unit tests |
| `9_Firmware/9_2_FPGA/` | Verilog RTL, constraints, testbenches, build scripts |
| `9_Firmware/9_3_GUI/` | Python radar dashboard (Tkinter/PyQt6) and CLI tools |
| `9_Firmware/tests/cross_layer/` | Python-based system invariant/contract tests |
| `9_Firmware/9_2_FPGA/formal/` | SymbiYosys formal-verification wrappers |
| `9_Firmware/9_2_FPGA/scripts/` | Vivado TCL build & debug scripts |
| `9_Firmware/9_3_GUI/` | Python radar dashboard (Tkinter + matplotlib) |
| `docs/` | GitHub Pages documentation site |
## Code Standards & Tooling
## Before submitting a pull request
- **Python (GUI, Scripts, Tests)**:
- We use `uv` for dependency management.
- We strictly enforce linting with `ruff`. Run `uv run ruff check .` before committing.
- Test with `pytest`.
- **Verilog (FPGA)**:
- The RTL (`radar_system_top.v`) is the single source of truth for opcode values, bit widths, reset defaults, and valid ranges.
- Testbenches must include **adversarial validation**: actively test boundary conditions, race conditions, unexpected input sequences, and reset mid-operation.
- Use `iverilog` for simulation.
- **C/C++ (MCU)**:
- Use `make test` for host-side unit testing (cpputest).
- **System-Level Invariants**:
- Whenever adding code, verify that system-level invariants (across module, process, and chip boundaries) hold true.
- **Python** — verify syntax: `python3 -m py_compile <file>`
- **Verilog** — if you have Vivado, run the relevant `build*.tcl`;
if not, note which scripts your change affects
- **Whitespace** — `git diff --check` should be clean
- Keep PRs focused: one logical change per PR is easier to review
- **Run the regression tests** (see below)
## AI Usage Policy
## Running regression tests
The use of AI is permitted but we have to make sure that the quality and control of the codebase doesn't depend on the agents but the maintainer pushing the changes, meaning they are fully responsible for the code they commit.
After any change, run the relevant test suites to verify nothing is
broken. All commands assume you are at the repository root.
1. **Human Accountability** — The committing engineer is fully responsible for AI-generated code as if they wrote it. Every PR must be understood and defensible by a human.
2. **Mandatory Review** — No raw AI output may be committed unread. AI code must pass the same review bar as hand-written code.
3. **Full CI Before Commit** — All AI-assisted changes must pass the complete CI suite locally (lint, unit, regression, cross-layer) before commit.
### Prerequisites
## Running the Test Suites
| Tool | Used by | Install |
|------|---------|---------|
| [Icarus Verilog](http://iverilog.icarus.com/) (`iverilog`) | FPGA regression | `brew install icarus-verilog` / `apt install iverilog` |
| Python 3.8+ | GUI tests, co-sim | Usually pre-installed |
| GNU Make | MCU tests | Usually pre-installed |
| [SymbiYosys](https://symbiyosys.readthedocs.io/) (`sby`) | Formal verification | Optional — see SymbiYosys docs |
We use GitHub Actions for CI, which runs four main jobs on every PR. Run these locally before pushing.
### FPGA regression (RTL lint + unit/integration/signal-processing tests)
### 1. Python & Linting
```bash
uv run ruff check .
cd 9_Firmware/9_3_GUI
uv run pytest test_GUI_V65_Tk.py test_v7.py -v
```
### 2. FPGA Regression
```bash
cd 9_Firmware/9_2_FPGA
bash run_regression.sh
```
This runs five phases (Lint, Changed Modules, Integration, Signal Processing, Infrastructure, and **P0 Adversarial Tests**). All must pass.
### 3. MCU Unit Tests
This runs four phases:
| Phase | What it checks |
|-------|----------------|
| 0 — Lint | `iverilog -Wall` on all production RTL + static regex checks |
| 1 — Changed Modules | Unit tests for individual blocks (CIC, Doppler, CFAR, etc.) |
| 2 — Integration | DDC chain, receiver golden-compare, system-top, end-to-end |
| 3 — Signal Processing | FFT engine, NCO, FIR, matched filter chain |
| 4 — Infrastructure | CDC modules, edge detector, USB interface, range-bin decimator, mode controller |
All tests must pass (exit code 0). Advisory lint warnings (e.g., `case
without default`) are non-blocking.
### MCU unit tests
```bash
cd 9_Firmware/9_1_Microcontroller/tests
make clean && make
make clean && make all
```
### 4. Cross-Layer Contract Tests
Runs 20 C-based unit tests covering safety, bug-fix, and gap-3 tests.
Every test binary must exit 0.
### GUI / dashboard tests
```bash
uv run pytest 9_Firmware/tests/cross_layer/test_cross_layer_contract.py -v
cd 9_Firmware/9_3_GUI
python3 -m pytest test_GUI_V65_Tk.py -v
# or without pytest:
python3 -m unittest test_GUI_V65_Tk -v
```
## Before merging: CI checklist
57+ protocol and rendering tests. The `test_record_and_stop` test
requires `h5py` and will be skipped if it is not installed.
All PRs must pass CI:
### Co-simulation (Python vs RTL golden comparison)
| Job | What it checks |
|----|---------------|
| `python-tests` | ruff clean + pytest green |
| `mcu-tests` | make all exits 0 |
| `fpga-regression` | run_regression.sh exits 0 |
| `cross-layer-tests` | pytest exits 0 |
Run from the co-sim directory after a successful FPGA regression (the
regression generates the RTL CSV outputs that the co-sim scripts compare
against):
## Important Notes
```bash
cd 9_Firmware/9_2_FPGA/tb/cosim
- **NO LEGACY COMPATIBILITY** unless explicitly requested by the maintainer.
- **The FPGA RTL (`radar_system_top.v`) is the single source of truth** for opcode values, bit widths, reset defaults, and valid ranges. All other layers must align to it.
- **Adversarial testing is mandatory**: Every test must actively try to break the code.
- **Testbench timing**: Always add a `#1` delay after `@(posedge clk)` before driving DUT inputs with blocking assignments.
- **Pre-fetch FIFO**: Remember `wr_full` is asserted after DEPTH+1 writes, not just DEPTH.
# Validate all .mem files (twiddles, chirp ROMs, addressing)
python3 validate_mem_files.py
## Checklist Before Push
# DDC chain: RTL vs Python model (5 scenarios)
python3 compare.py dc
python3 compare.py single_target
python3 compare.py multi_target
python3 compare.py noise_only
python3 compare.py sine_1mhz
- [ ] `uv run ruff check .` — no lint errors
- [ ] `uv run pytest test_GUI_V65_Tk.py test_v7.py -v` — all pass
- [ ] `cd 9_Firmware/9_2_FPGA && bash run_regression.sh` — all 5 phases pass
- [ ] `cd 9_Firmware/9_1_Microcontroller/tests && make clean && make` — pass
- [ ] `uv run pytest 9_Firmware/tests/cross_layer/test_cross_layer_contract.py` — pass
- [ ] `git diff --check` — no whitespace issues
- [ ] PR targets `develop` branch
# Doppler processor: RTL vs golden reference
python3 compare_doppler.py stationary
# Matched filter: RTL vs Python model (4 scenarios)
python3 compare_mf.py all
```
Each script prints PASS/FAIL per scenario and exits non-zero on failure.
### Formal verification (optional)
Requires SymbiYosys (`sby`), Yosys, and a solver (z3 or boolector):
```bash
cd 9_Firmware/9_2_FPGA/formal
sby -f fv_doppler_processor.sby
sby -f fv_radar_mode_controller.sby
```
### Quick checklist
Before pushing, confirm:
1. `bash run_regression.sh` — all phases pass
2. `make all` (MCU tests) — 20/20 pass
3. `python3 -m unittest test_GUI_V65_Tk -v` — all pass
4. `python3 validate_mem_files.py` — all checks pass
5. `python3 compare.py dc && python3 compare_doppler.py stationary && python3 compare_mf.py all`
6. `git diff --check` — no whitespace issues
## Areas where help is especially welcome
See the list in [README.md](README.md#-contributing).
## Questions?
Open a GitHub issue — discussion is visible to everyone.
Open a GitHub issue — that way the discussion is visible to everyone.
README.md
+9 -9
View File
@@ -7,6 +7,7 @@
[![Frequency: 10.5GHz](https://img.shields.io/badge/Frequency-10.5GHz-blue)](https://github.com/NawfalMotii79/PLFM_RADAR)
[![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg)](https://github.com/NawfalMotii79/PLFM_RADAR/pulls)
![AERIS-10 Radar System](https://raw.githubusercontent.com/NawfalMotii79/PLFM_RADAR/main/8_Utils/3fb1dabf-2c6d-4b5d-b471-48bc461ce914.jpg)
AERIS-10 is an open-source, low-cost 10.5 GHz phased array radar system featuring Pulse Linear Frequency Modulated (LFM) modulation. Available in two versions (3km and 20km range), it's designed for researchers, drone developers, and serious SDR enthusiasts who want to explore and experiment with phased array radar technology.
@@ -46,13 +47,13 @@ The AERIS-10 main sub-systems are:
- **Main Board** containing:
- **DAC** - Generates the RADAR Chirps
- **2x Microwave Mixers (LTC5552)** - For up-conversion and IF-down-conversion
- **2x Microwave Mixers (LT5552)** - For up-conversion and IF-down-conversion
- **4x 4-Channel Phase Shifters (ADAR1000)** - For RX and TX chain beamforming
- **16x Front End Chips (ADTR1107)** - Used for both Low Noise Amplifying (RX) and Power Amplifying (TX) stages
- **XC7A50T FPGA** - Handles RADAR Signal Processing on the upstream FTG256 board:
- PLFM Chirps generation via the DAC
- Raw ADC data read
- Hybrid Automatic Gain Control (AGC) — cross-layer FPGA/STM32/GUI loop
- Digital Gain Control (host-configurable gain shift)
- I/Q Baseband Down-Conversion
- Decimation
- Filtering
@@ -67,13 +68,13 @@ The AERIS-10 main sub-systems are:
- Clock Generator (AD9523-1)
- 2x Frequency Synthesizers (ADF4382)
- 4x 4-Channel Phase Shifters (ADAR1000) for RADAR pulse sequencing
- 2x ADS7830 8-channel I²C ADCs (Main Board, U88 @ 0x48 / U89 @ 0x4A) for 16x Idq measurement, one per PA channel, each sensed through a 5 mΩ shunt on the PA board and an INA241A3 current-sense amplifier (x50) on the Main Board
- 2x DAC5578 8-channel I²C DACs (Main Board, U7 @ 0x48 / U69 @ 0x49) for 16x Vg control, one per PA channel; closed-loop calibrated at boot to the target Idq
- GPS module (UM982) for GUI map centering and per-detection position tagging
- 2x ADS7830 ADCs (on Power Amplifier Boards) for Idq measurement
- 2x DAC5578 (on Power Amplifier Boards) for Vg control
- GPS module for GUI map centering
- GY-85 IMU for pitch/roll correction of target coordinates
- BMP180 Barometer
- Stepper Motor
- 1x ADS7830 8-channel I²C ADC (Main Board, U10) reading 8 thermistors for thermal monitoring; a single GPIO (EN_DIS_COOLING) switches the cooling fans on when any channel exceeds the threshold
- 8x ADS7830 Temperature Sensors for cooling fan control
- RF switches
- **16x Power Amplifier Boards** - Used only for AERIS-10E version, featuring 10Watt QPA2962 GaN amplifier for extended range
@@ -91,7 +92,7 @@ The AERIS-10 main sub-systems are:
### Processing Pipeline
1. **Waveform Generation** - DAC creates LFM chirps
2. **Up/Down Conversion** - LTC5552 mixers handle frequency translation
2. **Up/Down Conversion** - LT5552 mixers handle frequency translation
3. **Beam Steering** - ADAR1000 phase shifters control 16 elements
4. **Signal Processing (FPGA)**:
- Raw ADC data capture
@@ -110,8 +111,7 @@ The AERIS-10 main sub-systems are:
- Map integration
- Radar control interface
![AERIS-10 Dashboard](https://raw.githubusercontent.com/NawfalMotii79/PLFM_RADAR/main/8_Utils/GUI_V6.gif)
<!-- V6 GIF removed — V6 is deprecated. V65 Tk and V7 PyQt6 are the active GUIs. -->
![AERIS-10 GUI Demo](https://raw.githubusercontent.com/NawfalMotii79/PLFM_RADAR/main/8_Utils/GUI_V6.gif)
## 📊 Technical Specifications
docs/index.html
-5
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@@ -32,11 +32,6 @@
</section>
<section class="stats-grid">
<article class="card stat notice">
<h2>Production Board USB</h2>
<p class="metric">FT2232H (USB 2.0)</p>
<p class="muted">50T production board uses FT2232H. FT601 USB 3.0 is available on 200T premium dev board only.</p>
</article>
<article class="card stat">
<h2>Tracked Timing Baseline</h2>
<p class="metric">WNS +0.058 ns</p>