 Jason
|
76183e2e95
|
Fix 6 RTL bugs in FPGA signal processing chain
- nco_400m_enhanced.v: Correct sine LUT values (3.7x quadrature error)
- ddc_400m.v: Fix wire forward-declaration (Verilog-2001 compliance)
- plfm_chirp_controller.v: Remove multi-driven chirp_counter (critical)
- radar_system_top.v: Fix CFAR wire-as-reg, connect chirp_counter to receiver
- radar_receiver_final.v: Promote chirp_counter to input port
All fixes verified with Icarus Verilog 13.0 testbenches (144/144 tests pass).
|
2026-03-15 06:14:04 +02:00 |
|
 NawfalMotii79
|
19bcbba835
|
Add files via upload
|
2026-03-11 02:02:03 +00:00 |
|
|
NawfalMotii79
|
7b6f93955f
|
Create cntrt.xdc
|
2026-03-10 02:42:15 +00:00 |
|
|
NawfalMotii79
|
11089dfacd
|
Update GUI_V6_Demo.py
|
2026-03-10 01:55:47 +00:00 |
|
|
NawfalMotii79
|
90bab6bd64
|
Create GUI_V6_Demo.py
|
2026-03-10 01:43:19 +00:00 |
|
|
NawfalMotii79
|
a7e55c752f
|
Create usb_packet_analyzer.v
|
2026-03-10 01:36:04 +00:00 |
|
|
NawfalMotii79
|
220f2e0d0b
|
Create radar_system_tb.v
|
2026-03-10 01:35:26 +00:00 |
|
|
NawfalMotii79
|
45ad19184c
|
Add files via upload
|
2026-03-10 01:31:50 +00:00 |
|
|
NawfalMotii79
|
0eb2d9726d
|
Update GUI_versions.txt
|
2026-03-10 01:27:05 +00:00 |
|
|
NawfalMotii79
|
43ff85e331
|
Update and rename GUI_V6 to GUI_V6.py
|
2026-03-10 01:26:00 +00:00 |
|
|
NawfalMotii79
|
0c1cb7a57d
|
Add files via upload
|
2026-03-10 01:24:45 +00:00 |
|
|
NawfalMotii79
|
9d99a8e976
|
Add files via upload
|
2026-03-10 01:23:26 +00:00 |
|
|
NawfalMotii79
|
da0b87bee9
|
Add files via upload
|
2026-03-09 00:18:58 +00:00 |
|
|
NawfalMotii79
|
5fbe97fa5f
|
Add files via upload
|
2026-03-09 00:17:39 +00:00 |
|