Create radar_system_tb.v
This commit is contained in:
NawfalMotii79
GitHub
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`timescale 1ns / 1ps
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/**
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* radar_system_tb.v
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*
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* Comprehensive Testbench for Radar System Top Module
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* Tests:
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* - Transmitter chirp generation
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* - Receiver signal processing
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* - USB data transfer via FT601
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* - STM32 control interface
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*/
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module radar_system_tb;
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// ============================================================================
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// PARAMETERS
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// ============================================================================
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// Clock periods
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parameter CLK_100M_PERIOD = 10.0; // 100MHz = 10ns
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parameter CLK_120M_PERIOD = 8.333; // 120MHz = 8.333ns
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parameter FT601_CLK_PERIOD = 10.0; // 100MHz = 10ns
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parameter ADC_DCO_PERIOD = 2.5; // 400MHz = 2.5ns
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// Simulation time
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parameter SIM_TIME = 500_000; // 500us simulation
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// Test parameters
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parameter NUM_CHIRPS = 64; // Number of chirps to simulate
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parameter ENABLE_DOPPLER = 1; // Enable Doppler processing
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parameter ENABLE_CFAR = 1; // Enable CFAR detection
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parameter ENABLE_USB = 1; // Enable USB interface
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// ============================================================================
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// CLOCK AND RESET SIGNALS
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// ============================================================================
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reg clk_100m;
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reg clk_120m_dac;
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reg ft601_clk_in;
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reg reset_n;
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// ADC clocks
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reg adc_dco_p;
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reg adc_dco_n;
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// ADC data
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reg [7:0] adc_data_pattern;
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reg [7:0] adc_d_p;
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reg [7:0] adc_d_n;
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// FT601 interface
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wire [31:0] ft601_data;
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wire [1:0] ft601_be;
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wire ft601_txe_n;
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wire ft601_rxf_n;
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reg ft601_txe;
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reg ft601_rxf;
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wire ft601_wr_n;
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wire ft601_rd_n;
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wire ft601_oe_n;
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wire ft601_siwu_n;
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reg [1:0] ft601_srb;
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reg [1:0] ft601_swb;
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wire ft601_clk_out;
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// STM32 control signals
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reg stm32_new_chirp;
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reg stm32_new_elevation;
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reg stm32_new_azimuth;
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reg stm32_mixers_enable;
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// ADAR1000 SPI signals
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reg stm32_sclk_3v3;
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reg stm32_mosi_3v3;
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wire stm32_miso_3v3;
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reg stm32_cs_adar1_3v3;
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reg stm32_cs_adar2_3v3;
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reg stm32_cs_adar3_3v3;
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reg stm32_cs_adar4_3v3;
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wire stm32_sclk_1v8;
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wire stm32_mosi_1v8;
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reg stm32_miso_1v8;
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wire stm32_cs_adar1_1v8;
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wire stm32_cs_adar2_1v8;
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wire stm32_cs_adar3_1v8;
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wire stm32_cs_adar4_1v8;
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// DAC outputs
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wire [7:0] dac_data;
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wire dac_clk;
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wire dac_sleep;
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// RF control
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wire fpga_rf_switch;
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wire rx_mixer_en;
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wire tx_mixer_en;
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// ADAR1000 control
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wire adar_tx_load_1, adar_rx_load_1;
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wire adar_tx_load_2, adar_rx_load_2;
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wire adar_tx_load_3, adar_rx_load_3;
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wire adar_tx_load_4, adar_rx_load_4;
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wire adar_tr_1, adar_tr_2, adar_tr_3, adar_tr_4;
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// Status outputs
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wire [5:0] current_elevation;
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wire [5:0] current_azimuth;
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wire [5:0] current_chirp;
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wire new_chirp_frame;
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wire [31:0] dbg_doppler_data;
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wire dbg_doppler_valid;
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wire [4:0] dbg_doppler_bin;
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wire [5:0] dbg_range_bin;
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wire [3:0] system_status;
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// ============================================================================
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// CLOCK GENERATION
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// ============================================================================
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// 100MHz system clock
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initial begin
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clk_100m = 0;
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forever #(CLK_100M_PERIOD/2) clk_100m = ~clk_100m;
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end
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// 120MHz DAC clock
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initial begin
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clk_120m_dac = 0;
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forever #(CLK_120M_PERIOD/2) clk_120m_dac = ~clk_120m_dac;
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end
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// FT601 clock (100MHz)
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initial begin
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ft601_clk_in = 0;
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forever #(FT601_CLK_PERIOD/2) ft601_clk_in = ~ft601_clk_in;
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end
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// ADC DCO clock (400MHz)
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initial begin
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adc_dco_p = 0;
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adc_dco_n = 1;
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forever begin
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#(ADC_DCO_PERIOD/2) begin
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adc_dco_p = ~adc_dco_p;
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adc_dco_n = ~adc_dco_n;
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end
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end
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end
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// ============================================================================
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// RESET GENERATION
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// ============================================================================
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initial begin
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reset_n = 0;
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#100;
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reset_n = 1;
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#10;
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end
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// ============================================================================
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// FT601 INTERFACE SIMULATION
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// ============================================================================
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// FT601 FIFO status
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initial begin
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ft601_txe = 1'b0; // TX FIFO not empty (ready to write)
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ft601_rxf = 1'b1; // RX FIFO full (not ready to read)
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ft601_srb = 2'b00;
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ft601_swb = 2'b00;
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// Simulate occasional FIFO full conditions
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forever begin
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#1000;
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ft601_txe = $random % 2;
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ft601_rxf = $random % 2;
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end
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end
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// FT601 data bus monitoring
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reg [31:0] ft601_captured_data;
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reg [31:0] usb_packet_buffer [0:1023];
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integer usb_packet_count = 0;
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integer usb_byte_count = 0;
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always @(negedge ft601_wr_n) begin
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if (!ft601_wr_n) begin
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ft601_captured_data = ft601_data;
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usb_packet_buffer[usb_packet_count] = ft601_captured_data;
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usb_byte_count = usb_byte_count + 4;
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if (usb_packet_count < 100) begin
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$display("[USB @%0t] WRITE: data=0x%08h, be=%b, count=%0d",
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$time, ft601_captured_data, ft601_be, usb_packet_count);
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end
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usb_packet_count = usb_packet_count + 1;
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end
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end
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// ============================================================================
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// STM32 CONTROL SIGNAL GENERATION
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// ============================================================================
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integer chirp_num = 0;
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integer elevation_num = 0;
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integer azimuth_num = 0;
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initial begin
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// Initialize
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stm32_new_chirp = 0;
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stm32_new_elevation = 0;
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stm32_new_azimuth = 0;
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stm32_mixers_enable = 1;
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stm32_sclk_3v3 = 0;
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stm32_mosi_3v3 = 0;
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stm32_cs_adar1_3v3 = 1;
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stm32_cs_adar2_3v3 = 1;
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stm32_cs_adar3_3v3 = 1;
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stm32_cs_adar4_3v3 = 1;
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stm32_miso_1v8 = 0;
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#200;
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// Generate chirp sequence
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for (chirp_num = 0; chirp_num < NUM_CHIRPS; chirp_num = chirp_num + 1) begin
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// New chirp toggle
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stm32_new_chirp = 1;
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#20;
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stm32_new_chirp = 0;
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// Every 8 chirps, change elevation
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if ((chirp_num % 8) == 0) begin
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stm32_new_elevation = 1;
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#20;
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stm32_new_elevation = 0;
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elevation_num = elevation_num + 1;
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end
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// Every 16 chirps, change azimuth
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if ((chirp_num % 16) == 0) begin
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stm32_new_azimuth = 1;
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#20;
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stm32_new_azimuth = 0;
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azimuth_num = azimuth_num + 1;
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end
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// Wait for chirp duration
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#3000; // ~30us between chirps
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end
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// Disable mixers at the end
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#5000;
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stm32_mixers_enable = 0;
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end
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// ============================================================================
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// ADC DATA GENERATION (Simulated Radar Echo)
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// ============================================================================
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integer sample_count = 0;
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integer target_count = 0;
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reg [31:0] echo_delay [0:9];
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reg [7:0] echo_amplitude [0:9];
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reg [7:0] echo_phase [0:9];
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integer target_idx;
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initial begin
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// Initialize targets (simulated objects)
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// Format: {delay_samples, amplitude, phase_index}
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echo_delay[0] = 500; echo_amplitude[0] = 100; echo_phase[0] = 0;
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echo_delay[1] = 1200; echo_amplitude[1] = 80; echo_phase[1] = 45;
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echo_delay[2] = 2500; echo_amplitude[2] = 60; echo_phase[2] = 90;
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echo_delay[3] = 4000; echo_amplitude[3] = 40; echo_phase[3] = 135;
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echo_delay[4] = 6000; echo_amplitude[4] = 20; echo_phase[4] = 180;
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for (target_idx = 5; target_idx < 10; target_idx = target_idx + 1) begin
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echo_delay[target_idx] = 0;
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echo_amplitude[target_idx] = 0;
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echo_phase[target_idx] = 0;
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end
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adc_d_p = 8'h00;
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adc_d_n = ~8'h00;
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// Wait for reset and chirp start
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#500;
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// Generate ADC data synchronized with chirps
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forever begin
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@(posedge adc_dco_p);
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sample_count = sample_count + 1;
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// Generate echo signal when transmitter is active
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if (tx_mixer_en && fpga_rf_switch) begin
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adc_data_pattern = generate_radar_echo(sample_count);
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end else begin
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adc_data_pattern = 8'h80; // Mid-scale noise floor
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end
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// Add noise
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adc_data_pattern = adc_data_pattern + ($random % 16) - 8;
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// LVDS output
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adc_d_p = adc_data_pattern;
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adc_d_n = ~adc_data_pattern;
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end
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end
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// Function to generate radar echo based on multiple targets
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function [7:0] generate_radar_echo;
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input integer sample;
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integer t;
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integer echo_sum;
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integer chirp_phase;
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reg [7:0] result;
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begin
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echo_sum = 128; // DC offset
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for (t = 0; t < 5; t = t + 1) begin
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if (echo_delay[t] > 0 && sample > echo_delay[t]) begin
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// Simple Doppler modulation
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chirp_phase = ((sample - echo_delay[t]) * 10) % 256;
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echo_sum = echo_sum + $signed({1'b0, echo_amplitude[t]}) *
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$signed({1'b0, sin_lut[chirp_phase + echo_phase[t]]}) / 128;
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end
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end
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// Clamp to 8-bit range
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if (echo_sum > 255) echo_sum = 255;
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if (echo_sum < 0) echo_sum = 0;
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result = echo_sum[7:0];
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generate_radar_echo = result;
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end
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endfunction
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// Sine LUT for echo modulation
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reg [7:0] sin_lut [0:255];
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integer lut_i;
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initial begin
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for (lut_i = 0; lut_i < 256; lut_i = lut_i + 1) begin
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sin_lut[lut_i] = 128 + 127 * $sin(2 * 3.14159 * lut_i / 256);
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end
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end
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// ============================================================================
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// SPI COMMUNICATION MONITORING
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// ============================================================================
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always @(posedge stm32_sclk_1v8) begin
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if (!stm32_cs_adar1_1v8) begin
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$display("[SPI @%0t] ADAR1: MOSI=%b, MISO=%b",
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$time, stm32_mosi_1v8, stm32_miso_1v8);
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end
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if (!stm32_cs_adar2_1v8) begin
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$display("[SPI @%0t] ADAR2: MOSI=%b, MISO=%b",
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$time, stm32_mosi_1v8, stm32_miso_1v8);
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end
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end
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// ============================================================================
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// DUT INSTANTIATION
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// ============================================================================
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radar_system_top dut (
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// System Clocks
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.clk_100m(clk_100m),
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.clk_120m_dac(clk_120m_dac),
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.ft601_clk_in(ft601_clk_in),
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.reset_n(reset_n),
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// Transmitter Interfaces
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.dac_data(dac_data),
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.dac_clk(dac_clk),
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.dac_sleep(dac_sleep),
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.fpga_rf_switch(fpga_rf_switch),
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.rx_mixer_en(rx_mixer_en),
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.tx_mixer_en(tx_mixer_en),
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// ADAR1000 Control
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.adar_tx_load_1(adar_tx_load_1),
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.adar_rx_load_1(adar_rx_load_1),
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.adar_tx_load_2(adar_tx_load_2),
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.adar_rx_load_2(adar_rx_load_2),
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.adar_tx_load_3(adar_tx_load_3),
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.adar_rx_load_3(adar_rx_load_3),
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.adar_tx_load_4(adar_tx_load_4),
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.adar_rx_load_4(adar_rx_load_4),
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.adar_tr_1(adar_tr_1),
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.adar_tr_2(adar_tr_2),
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.adar_tr_3(adar_tr_3),
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.adar_tr_4(adar_tr_4),
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// Level Shifter SPI
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.stm32_sclk_3v3(stm32_sclk_3v3),
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.stm32_mosi_3v3(stm32_mosi_3v3),
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.stm32_miso_3v3(stm32_miso_3v3),
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.stm32_cs_adar1_3v3(stm32_cs_adar1_3v3),
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.stm32_cs_adar2_3v3(stm32_cs_adar2_3v3),
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.stm32_cs_adar3_3v3(stm32_cs_adar3_3v3),
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.stm32_cs_adar4_3v3(stm32_cs_adar4_3v3),
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.stm32_sclk_1v8(stm32_sclk_1v8),
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.stm32_mosi_1v8(stm32_mosi_1v8),
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.stm32_miso_1v8(stm32_miso_1v8),
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.stm32_cs_adar1_1v8(stm32_cs_adar1_1v8),
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.stm32_cs_adar2_1v8(stm32_cs_adar2_1v8),
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.stm32_cs_adar3_1v8(stm32_cs_adar3_1v8),
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.stm32_cs_adar4_1v8(stm32_cs_adar4_1v8),
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// Receiver Interfaces
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.adc_d_p(adc_d_p),
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.adc_d_n(adc_d_n),
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.adc_dco_p(adc_dco_p),
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.adc_dco_n(adc_dco_n),
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.adc_pwdn(adc_pwdn),
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// STM32 Control
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.stm32_new_chirp(stm32_new_chirp),
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.stm32_new_elevation(stm32_new_elevation),
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.stm32_new_azimuth(stm32_new_azimuth),
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.stm32_mixers_enable(stm32_mixers_enable),
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// FT601 Interface
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.ft601_data(ft601_data),
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.ft601_be(ft601_be),
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.ft601_txe_n(ft601_txe_n),
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.ft601_rxf_n(ft601_rxf_n),
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.ft601_txe(ft601_txe),
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.ft601_rxf(ft601_rxf),
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.ft601_wr_n(ft601_wr_n),
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.ft601_rd_n(ft601_rd_n),
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.ft601_oe_n(ft601_oe_n),
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.ft601_siwu_n(ft601_siwu_n),
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.ft601_srb(ft601_srb),
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.ft601_swb(ft601_swb),
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.ft601_clk_out(ft601_clk_out),
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// Status Outputs
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.current_elevation(current_elevation),
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.current_azimuth(current_azimuth),
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.current_chirp(current_chirp),
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.new_chirp_frame(new_chirp_frame),
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.dbg_doppler_data(dbg_doppler_data),
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.dbg_doppler_valid(dbg_doppler_valid),
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.dbg_doppler_bin(dbg_doppler_bin),
|
||||
.dbg_range_bin(dbg_range_bin),
|
||||
.system_status(system_status)
|
||||
);
|
||||
|
||||
// ============================================================================
|
||||
// MONITORING AND CHECKING
|
||||
// ============================================================================
|
||||
|
||||
// Transmitter monitoring
|
||||
always @(posedge clk_100m) begin
|
||||
if (new_chirp_frame) begin
|
||||
$display("[MON @%0t] New chirp frame: chirp=%0d, elev=%0d, az=%0d",
|
||||
$time, current_chirp, current_elevation, current_azimuth);
|
||||
end
|
||||
end
|
||||
|
||||
// DAC output monitoring
|
||||
integer dac_sample_count = 0;
|
||||
always @(posedge dac_clk) begin
|
||||
if (dac_data != 8'h80) begin
|
||||
dac_sample_count = dac_sample_count + 1;
|
||||
if (dac_sample_count < 50) begin
|
||||
$display("[DAC @%0t] data=0x%02h", $time, dac_data);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Doppler output monitoring
|
||||
integer doppler_count = 0;
|
||||
always @(posedge clk_100m) begin
|
||||
if (dbg_doppler_valid) begin
|
||||
doppler_count = doppler_count + 1;
|
||||
if (doppler_count < 100) begin
|
||||
$display("[DOPPLER @%0t] bin=%0d, range=%0d, data=0x%08h",
|
||||
$time, dbg_doppler_bin, dbg_range_bin, dbg_doppler_data);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// TEST COMPLETION
|
||||
// ============================================================================
|
||||
|
||||
initial begin
|
||||
#SIM_TIME;
|
||||
|
||||
$display("");
|
||||
$display("========================================");
|
||||
$display("SIMULATION COMPLETE");
|
||||
$display("========================================");
|
||||
$display("Total simulation time: %0t ns", $time);
|
||||
$display("Chirps generated: %0d", chirp_num);
|
||||
$display("USB packets sent: %0d", usb_packet_count);
|
||||
$display("USB bytes sent: %0d", usb_byte_count);
|
||||
$display("Doppler outputs: %0d", doppler_count);
|
||||
$display("DAC samples: %0d", dac_sample_count);
|
||||
$display("========================================");
|
||||
|
||||
// Verify USB data format
|
||||
if (usb_packet_count > 0) begin
|
||||
$display("");
|
||||
$display("USB Packet Analysis:");
|
||||
$display("First 10 packets:");
|
||||
for (integer p = 0; p < 10 && p < usb_packet_count; p = p + 1) begin
|
||||
$display(" Packet[%0d]: 0x%08h", p, usb_packet_buffer[p]);
|
||||
end
|
||||
end
|
||||
|
||||
$finish;
|
||||
end
|
||||
|
||||
// ============================================================================
|
||||
// ASSERTIONS AND CHECKS
|
||||
// ============================================================================
|
||||
|
||||
// Check that chirp counter increments properly
|
||||
property chirp_counter_check;
|
||||
@(posedge clk_100m) $rose(new_chirp_frame) |-> ##[1:10] (current_chirp != $past(current_chirp));
|
||||
endproperty
|
||||
assert property (chirp_counter_check) else $error("Chirp counter not incrementing");
|
||||
|
||||
// Check that USB writes occur when data is valid
|
||||
property usb_write_check;
|
||||
@(posedge ft601_clk_in) (dbg_doppler_valid) |-> ##[1:100] (!$stable(ft601_wr_n));
|
||||
endproperty
|
||||
assert property (usb_write_check) else $warning("USB not writing when data valid");
|
||||
|
||||
// Check that system reset works
|
||||
property reset_check;
|
||||
@(negedge reset_n) (1'b1) |-> ##1 (system_status == 4'b0000);
|
||||
endproperty
|
||||
assert property (reset_check) else $error("Reset failed to clear status");
|
||||
|
||||
// ============================================================================
|
||||
// WAVEFORM DUMPING
|
||||
// ============================================================================
|
||||
|
||||
initial begin
|
||||
$dumpfile("radar_system_tb.vcd");
|
||||
$dumpvars(0, radar_system_tb);
|
||||
|
||||
// Optional: dump specific signals for debugging
|
||||
$dumpvars(1, dut.tx_inst);
|
||||
$dumpvars(1, dut.rx_inst);
|
||||
$dumpvars(1, dut.usb_inst);
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user