Jason 76183e2e95 Fix 6 RTL bugs in FPGA signal processing chain ...

- nco_400m_enhanced.v: Correct sine LUT values (3.7x quadrature error)
- ddc_400m.v: Fix wire forward-declaration (Verilog-2001 compliance)
- plfm_chirp_controller.v: Remove multi-driven chirp_counter (critical)
- radar_system_top.v: Fix CFAR wire-as-reg, connect chirp_counter to receiver
- radar_receiver_final.v: Promote chirp_counter to input port

All fixes verified with Icarus Verilog 13.0 testbenches (144/144 tests pass).

2026-03-15 06:14:04 +02:00

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9_1_Microcontroller

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2026-03-09 00:18:58 +00:00

9_2_FPGA

Fix 6 RTL bugs in FPGA signal processing chain

2026-03-15 06:14:04 +02:00

9_3_GUI

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2026-03-11 02:02:03 +00:00