73d6d9b80a
Add files via upload
2026-04-05 11:44:10 +01:00
0f5a04f8a7
Delete 4_Schematics and Boards Layout/4_7_Production Files directory
2026-04-05 11:39:13 +01:00
8e0a90fcf5
Add files via upload
2026-04-05 05:05:10 +01:00
10e0914d60
Delete docs/assets/img/Nawfal.png
2026-04-04 21:04:42 +01:00
168b9b2ae0
Revise index.html for AERIS-10 documentation site
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Updated the HTML structure and content for the AERIS-10 documentation site, including new sections for engineering documentation and navigation links.
2026-04-02 01:42:50 +01:00
a343c856e3
Update image links to use raw GitHub URLs
2026-04-02 01:35:17 +01:00
7ffd1f6b10
Revise README for clarity and image updates
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Updated images and text for clarity and consistency in the README.
2026-04-02 01:31:23 +01:00
f12405e90e
Add files via upload
2026-04-02 01:24:58 +01:00
72411006ab
Add files via upload
2026-04-02 01:23:36 +01:00
1beb7dc1ad
Revise index.html with new images and metadata
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Updated metadata and added new images for the AERIS-10 project. Adjusted GitHub links and footer information.
2026-04-02 01:14:06 +01:00
49e22b8bc9
Add files via upload
2026-04-02 01:12:19 +01:00
c7fa099293
Add files via upload
2026-04-02 01:04:55 +01:00
81bf4cabbb
Delete 8_Utils directory
2026-04-02 01:03:40 +01:00
cfbe6d2bd4
Fix image paths in README.md
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Updated image paths in README.md to use absolute paths.
2026-04-02 00:58:22 +01:00
e4fa118b50
Refactor index.html for improved layout and SEO
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Updated the HTML structure and styles for the AERIS-10 documentation page, enhancing the layout and adding meta tags for better SEO.
2026-04-02 00:57:10 +01:00
c91e4b4252
Delete index.html
2026-04-02 00:56:29 +01:00
b7f40445a4
Add files via upload
2026-04-02 00:40:14 +01:00
2ec636ef58
Update index.html for absolute paths and styles
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Updated links to use absolute paths and added fallback inline styles for the documentation site.
2026-04-02 00:32:41 +01:00
a6205bd768
Add initial HTML structure for AERIS-10 project
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Initial commit of the AERIS-10 project website, including HTML structure, styling, and content for radar system overview, specifications, architecture, and documentation.
2026-04-02 00:01:44 +01:00
bbd0556200
Delete index.html
2026-04-01 23:53:26 +01:00
86681127b0
Add index.html for AERIS-10 documentation
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Initial commit of the AERIS-10 Engineering Documentation site.
2026-04-01 22:38:42 +01:00
d8d1d34a35
Add files via upload
2026-03-31 03:21:54 +01:00
484bf0907c
Delete 4_Schematics and Boards Layout/4_6_Schematics/PowerBoard/PowerBoard.brd
2026-03-31 03:21:09 +01:00
f5d89fd710
Fix badge syntax in README.md
2026-03-29 10:50:46 +01:00
a3d0d3fb0c
Fix image formatting in README.md
2026-03-29 08:47:06 +01:00
46c37e17d4
Merge pull request #33 from JJassonn69/fix/staggered-prf-dual16-doppler
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Fix staggered-PRF Doppler path using dual 16-point FFT sub-frames
2026-03-27 22:09:08 +01:00
a577b7628b
Fix staggered-PRF Doppler processing with dual 16-point FFTs
2026-03-27 23:05:28 +02:00
2a89713c21
Add sponsors section to README
2026-03-27 03:40:34 +01:00
f5765f6c2c
Add files via upload
2026-03-27 03:36:05 +01:00
02eb0b99cf
Delete 14_RADAR_Old_version directory
2026-03-22 01:32:49 +00:00
93c75d19df
Merge pull request #30 from JJassonn69/main
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FPGA file on Original Repository
2026-03-21 20:02:05 +00:00
5499827ab7
add TE0713+UMFT601X-B FT601 integration dev bitstream (timing clean)
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FMC LPC dev build for TE0713/TE0701 + UMFT601X-B stack. Fixed timing
closure: replaced set_output_delay with set_max_delay -datapath_only
to eliminate false IBUF+BUFG clock skew penalty on source-synchronous
outputs. Removed erroneous set_input_delay on output-only ft601_be[*].
Added IOB packing for siwu_n, false paths for async GPIO/reset/wakeup.
Strategy: Performance_ExplorePostRoutePhysOpt.
Results: WNS +0.059 ns, WHS +0.121 ns, DRC 0 errors, 0 failing endpoints.
Bitstream: docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit
2026-03-21 20:43:52 +02:00
9dee28ab52
add TE0713 heartbeat bring-up artifact
2026-03-21 20:16:45 +02:00
f9ad30e737
GUI: add self-test UI, fix opcode mismatches (0x16->0x06, 0x04->0x05), update status parsing to 6-word/26-byte format
2026-03-20 20:54:42 +02:00
4985eccbae
Wire self-test results (0x31) to USB status readback path, add fpga_self_test to regression
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- usb_data_interface.v: Add 3 self-test status inputs, expand status packet
from 7 words (header + 5 data + footer) to 8 words (header + 6 data + footer).
New status_words[5] carries {busy, detail[7:0], flags[4:0]}.
- radar_system_top.v: Wire self_test_flags_latched, self_test_detail_latched,
self_test_busy to usb_data_interface ports. Add opcode 0x31 as status
readback alias so host can read self-test results.
- tb_usb_data_interface.v: Add self-test port connections, verify word 5 in
Group 16, add Group 18 (busy flag + partial failure variant). 81 checks pass.
- run_regression.sh: Add fpga_self_test.v to PROD_RTL lint list and system-
level compile lists. Add tb_fpga_self_test as Phase 1 unit test.
- 24/24 regression tests pass, lint clean (0 errors, 4 advisory warnings).
2026-03-20 20:03:11 +02:00
eb907de3d1
Fix 5 GUI bugs: threaded connect, button toggle, live CFAR/MTI/DC replay, stable heatmap, physical axis labels
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- Bug 1: Move conn.open() to background thread to prevent GUI hang
- Bug 2: Save btn_connect as instance var, toggle Connect/Disconnect text
- Bug 3: Split opcodes into hardware-only (silent) and replay-adjustable
(CFAR/MTI/DC-notch params trigger bit-accurate pipeline re-processing)
- Bug 4: EMA-smoothed vmax (alpha=0.15), fftshift on Doppler axis
- Bug 5: Physical axis labels (range in meters, velocity in m/s)
- Add _replay_mti(), _replay_dc_notch(), _replay_cfar() standalone functions
- Expand TestReplayConnection from 6 to 11 tests (42/42 pass)
2026-03-20 19:36:21 +02:00
f8d80cc96e
Add radar dashboard GUI with replay mode for real ADI CN0566 data visualization, FPGA self-test module, and co-sim npy arrays
2026-03-20 19:02:06 +02:00
7a44f19432
Full-chain MTI+CFAR real-data co-simulation: bit-exact match across all 10247 checkpoints (decim->MTI->Doppler->DC notch->CFAR) using ADI CN0566 data
2026-03-20 17:16:12 +02:00
d5d28e9f1c
Build 25 engineering report: MTI canceller + DC notch timing PASS
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Build 25 results (MTI + DC notch integration):
- WNS +0.132 ns, WHS +0.058 ns (all domains PASS)
- 9,252 LUTs, 12,488 FFs, 17 BRAM, 142 DSP, 0.753 W
- MTI cost: +694 LUTs, +2,104 FFs, 0 BRAM, 0 DSP
- Bitstream: radar_system_top_build25.bit (production-safe)
- 23/23 FPGA regression, 29/29 MTI checks, 3/3 real-data co-sim
Updated reports.html (15-point Build 25 report), implementation-log.html
(timeline entries for production fixes, CFAR, MTI), and release-notes.html
(new tagged releases, gap status update).
2026-03-20 16:59:30 +02:00
ed629e7559
Integrate MTI canceller and DC notch filter for ground clutter removal
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MTI canceller (2-pulse, H(z)=1-z^{-1}) between range decimator and
Doppler processor. Subtracts previous chirp from current, nulling DC
Doppler (stationary clutter). Pass-through when host_mti_enable=0.
DC notch filter (post-Doppler, pre-CFAR) zeros bins within
+/-host_dc_notch_width of DC. Complements MTI for residual clutter.
New host registers: 0x26 (mti_enable), 0x27 (dc_notch_width).
Both default to 0 (disabled) - fully backward-compatible.
Verification: 23/23 regression, 29/29 MTI standalone, 3/3 real-data
co-sim (5137/5137 exact match) all PASS.
2026-03-20 16:39:17 +02:00
eb8e063f37
Change radar system image format to PNG
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Updated image format from JPG to PNG for better quality.
2026-03-20 05:49:13 +00:00
4801cb81d2
Replace radar system image with updated version
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Updated the image for the AERIS-10 Radar System in the README.
2026-03-20 05:48:20 +00:00
075ae1e77a
Add Build 24 15-point engineering report: timing, utilization, DSP/BRAM breakdown, power, DRC, methodology, congestion, routing, logic levels, build comparison, CFAR cost, verification summary
2026-03-20 05:47:20 +02:00
0b170f7c61
Added Full Diagram
2026-03-20 05:32:15 +02:00
d7fc8c6771
Complete Diagram
2026-03-20 05:32:11 +02:00
0745cc4f48
Pipeline CFAR noise computation: break critical path for timing closure
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Split ST_CFAR_THR into two pipeline stages (THR + MUL) to fix Build 23
timing violation (WNS = -0.309 ns). The combinational path from
leading_sum through GO/SO cross-multiply into alpha*noise DSP was too
long for 10 ns.
New pipeline:
ST_CFAR_THR: register noise_sum_comb (mode select + cross-multiply)
ST_CFAR_MUL: compute alpha * noise_sum_reg in DSP
ST_CFAR_CMP: compare + update window (unchanged)
3 cycles per CUT instead of 2 (~85 us vs 70 us per frame, negligible).
All detection results identical: 23/23 CFAR standalone, 22/22 full
regression, 3/3 real-data co-sim (5137/5137 exact match) PASS.
2026-03-20 05:24:08 +02:00
f71923b67d
Integrate CA-CFAR detector: replace fixed-threshold comparator with adaptive sliding-window CFAR engine (22/22 regression PASS)
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- Add cfar_ca.v: CA/GO/SO-CFAR with BRAM magnitude buffer, host-configurable
guard cells, training cells, alpha multiplier, and mode selection
- Replace old threshold detector block in radar_system_top.v with cfar_ca
instantiation; backward-compatible (cfar_enable defaults to 0)
- Add 5 new host registers: guard (0x21), train (0x22), alpha (0x23),
mode (0x24), enable (0x25)
- Expose doppler_frame_done_out from radar_receiver_final for CFAR frame sync
- Add tb_cfar_ca.v standalone testbench (14 tests, 24 checks)
- Add Group 14 E2E tests: 13 checks covering range-mode (0x20) and all
CFAR config registers (0x21-0x25) through full USB command path
- Update run_regression.sh with CFAR in lint, Phase 1, and integration compiles
2026-03-20 04:57:34 +02:00
e93bc33c6c
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
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Fix 1: Combinational magnitude + non-sticky detection flag (tb: 23/23)
Fix 2: Rename all cfar_* signals to detect_*/threshold_* (honest naming)
Fix 3: New rx_gain_control.v between DDC and FFT, opcode 0x16 (tb: 33/33)
Fix 4: Clamp host_chirps_per_elev to DOPPLER_FFT_SIZE, error flag (E2E: 54/54)
Fix 5: Decimator watchdog timeout, 256-cycle limit (tb: 63/63)
Fix 6: Remove bypass_mode dead code from ddc_400m.v (DDC tb: 21/21)
Fix 7: Range-mode register 0x20 with status readback (USB tb: 77/77)
2026-03-20 04:38:35 +02:00
0b0643619c
Real-data co-simulation: range FFT, Doppler, full-chain all 2048/2048 exact match
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ADI CN0566 Phaser 10.525 GHz X-band radar data validation:
- golden_reference.py: bit-accurate Python model with range_bin_decimator
- tb_range_fft_realdata.v: 1024/1024 exact match
- tb_doppler_realdata.v: 2048/2048 exact match
- tb_fullchain_realdata.v: decimator+Doppler 2048/2048 exact match
- 19/19 FPGA regression unaffected
2026-03-20 03:19:22 +02:00
b01c507de8
Added Full Diagram
2026-03-20 00:22:45 +00:00
NawfalMotii79
Jason