fix(fpga): audit F-2026-04-20-A/B — CIC reset fan-out + BUFIO→BUFG max_delay

A: cic_decimator_4x_enhanced.v reset_h max_fanout 50→25. More replicas
mean each drives fewer DSP48 RSTB loads, letting Vivado place each
closer to its consumers. Targets the rep__24 → comb_reg[4]/RSTB path
that failed clk_mmcm_out0 intra by -10 ps (1.4 ns of pure routing).

B: adc_clk_mmcm.xdc BUFIO↔BUFG max_delay 2.500→2.700 ns. The 2.5 ns
target was tighter than achievable for the IDDR (ILOGIC) → FDRE (fabric
SLICE) re-registration. The effective window is the BUFIO↔BUFG phase
relationship (not the clock period), so 2.7 ns remains safe. Fixes the
adc_dco_p→clk_mmcm_out0 inter path -113 ps failure on lane 7.

9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v

@@ -74,7 +74,7 @@ localparam COMB_WIDTH = 28;
 //                           DSP output) = 4 cycles at 400 MHz = 10 ns.
 //                           Negligible vs system reset assertion duration.
 // ----------------------------------------------------------------------------
-(* max_fanout = 50 *) reg reset_h = 1'b1;  // INIT=1'b1: registers start in reset state on power-up
+(* max_fanout = 25 *) reg reset_h = 1'b1;  // INIT=1'b1: registers start in reset state on power-up
 always @(posedge clk) reset_h <= ~reset_n;
 
 // Sign-extended input for integrator_0 C port (48-bit)

9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc

@@ -33,10 +33,10 @@
 # (one period) to ensure the tools verify the transfer fits within one cycle
 # without over-constraining with full inter-clock setup/hold analysis.
 set_max_delay -datapath_only -from [get_clocks adc_dco_p] \
-    -to [get_clocks clk_mmcm_out0] 2.500
+    -to [get_clocks clk_mmcm_out0] 2.700
 
 set_max_delay -datapath_only -from [get_clocks clk_mmcm_out0] \
-    -to [get_clocks adc_dco_p] 2.500
+    -to [get_clocks adc_dco_p] 2.700
 
 # --------------------------------------------------------------------------
 # CDC: MMCM output domain ↔ other clock domains