diff --git a/9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v b/9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v
index 3b3547a..adb5a3d 100644
--- a/9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v
+++ b/9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v
@@ -74,7 +74,7 @@ localparam COMB_WIDTH = 28;
 //                           DSP output) = 4 cycles at 400 MHz = 10 ns.
 //                           Negligible vs system reset assertion duration.
 // ----------------------------------------------------------------------------
-(* max_fanout = 50 *) reg reset_h = 1'b1;  // INIT=1'b1: registers start in reset state on power-up
+(* max_fanout = 25 *) reg reset_h = 1'b1;  // INIT=1'b1: registers start in reset state on power-up
 always @(posedge clk) reset_h <= ~reset_n;
 
 // Sign-extended input for integrator_0 C port (48-bit)
diff --git a/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc b/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc
index cd30508..518f4da 100644
--- a/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc
+++ b/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc
@@ -33,10 +33,10 @@
 # (one period) to ensure the tools verify the transfer fits within one cycle
 # without over-constraining with full inter-clock setup/hold analysis.
 set_max_delay -datapath_only -from [get_clocks adc_dco_p] \
-    -to [get_clocks clk_mmcm_out0] 2.500
+    -to [get_clocks clk_mmcm_out0] 2.700
 
 set_max_delay -datapath_only -from [get_clocks clk_mmcm_out0] \
-    -to [get_clocks adc_dco_p] 2.500
+    -to [get_clocks adc_dco_p] 2.700
 
 # --------------------------------------------------------------------------
 # CDC: MMCM output domain ↔ other clock domains