From d36a4c93e24aa99115a43251ec4f1cb3715c1131 Mon Sep 17 00:00:00 2001
From: Jason <83615043+JJassonn69@users.noreply.github.com>
Date: Mon, 20 Apr 2026 20:20:43 +0545
Subject: [PATCH] =?UTF-8?q?fix(fpga):=20audit=20F-2026-04-20-A/B=20?=
 =?UTF-8?q?=E2=80=94=20CIC=20reset=20fan-out=20+=20BUFIO=E2=86=92BUFG=20ma?=
 =?UTF-8?q?x=5Fdelay?=
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A: cic_decimator_4x_enhanced.v reset_h max_fanout 50→25. More replicas
mean each drives fewer DSP48 RSTB loads, letting Vivado place each
closer to its consumers. Targets the rep__24 → comb_reg[4]/RSTB path
that failed clk_mmcm_out0 intra by -10 ps (1.4 ns of pure routing).

B: adc_clk_mmcm.xdc BUFIO↔BUFG max_delay 2.500→2.700 ns. The 2.5 ns
target was tighter than achievable for the IDDR (ILOGIC) → FDRE (fabric
SLICE) re-registration. The effective window is the BUFIO↔BUFG phase
relationship (not the clock period), so 2.7 ns remains safe. Fixes the
adc_dco_p→clk_mmcm_out0 inter path -113 ps failure on lane 7.
---
 9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v  | 2 +-
 9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v b/9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v
index 3b3547a..adb5a3d 100644
--- a/9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v
+++ b/9_Firmware/9_2_FPGA/cic_decimator_4x_enhanced.v
@@ -74,7 +74,7 @@ localparam COMB_WIDTH = 28;
 //                           DSP output) = 4 cycles at 400 MHz = 10 ns.
 //                           Negligible vs system reset assertion duration.
 // ----------------------------------------------------------------------------
-(* max_fanout = 50 *) reg reset_h = 1'b1;  // INIT=1'b1: registers start in reset state on power-up
+(* max_fanout = 25 *) reg reset_h = 1'b1;  // INIT=1'b1: registers start in reset state on power-up
 always @(posedge clk) reset_h <= ~reset_n;
 
 // Sign-extended input for integrator_0 C port (48-bit)
diff --git a/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc b/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc
index cd30508..518f4da 100644
--- a/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc
+++ b/9_Firmware/9_2_FPGA/constraints/adc_clk_mmcm.xdc
@@ -33,10 +33,10 @@
 # (one period) to ensure the tools verify the transfer fits within one cycle
 # without over-constraining with full inter-clock setup/hold analysis.
 set_max_delay -datapath_only -from [get_clocks adc_dco_p] \
-    -to [get_clocks clk_mmcm_out0] 2.500
+    -to [get_clocks clk_mmcm_out0] 2.700
 
 set_max_delay -datapath_only -from [get_clocks clk_mmcm_out0] \
-    -to [get_clocks adc_dco_p] 2.500
+    -to [get_clocks adc_dco_p] 2.700
 
 # --------------------------------------------------------------------------
 # CDC: MMCM output domain ↔ other clock domains