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// file: Clock_120MHz.v
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//
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// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
|
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//
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||||
// This file contains confidential and proprietary information
|
||||
// of Xilinx, Inc. and is protected under U.S. and
|
||||
// international copyright and other intellectual property
|
||||
// laws.
|
||||
//
|
||||
// DISCLAIMER
|
||||
// This disclaimer is not a license and does not grant any
|
||||
// rights to the materials distributed herewith. Except as
|
||||
// otherwise provided in a valid license issued to you by
|
||||
// Xilinx, and to the maximum extent permitted by applicable
|
||||
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
// (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
// including negligence, or under any other theory of
|
||||
// liability) for any loss or damage of any kind or nature
|
||||
// related to, arising under or in connection with these
|
||||
// materials, including for any direct, or any indirect,
|
||||
// special, incidental, or consequential loss or damage
|
||||
// (including loss of data, profits, goodwill, or any type of
|
||||
// loss or damage suffered as a result of any action brought
|
||||
// by a third party) even if such damage or loss was
|
||||
// reasonably foreseeable or Xilinx had been advised of the
|
||||
// possibility of the same.
|
||||
//
|
||||
// CRITICAL APPLICATIONS
|
||||
// Xilinx products are not designed or intended to be fail-
|
||||
// safe, or for use in any application requiring fail-safe
|
||||
// performance, such as life-support or safety devices or
|
||||
// systems, Class III medical devices, nuclear facilities,
|
||||
// applications related to the deployment of airbags, or any
|
||||
// other applications that could lead to death, personal
|
||||
// injury, or severe property or environmental damage
|
||||
// (individually and collectively, "Critical
|
||||
// Applications"). Customer assumes the sole risk and
|
||||
// liability of any use of Xilinx products in Critical
|
||||
// Applications, subject only to applicable laws and
|
||||
// regulations governing limitations on product liability.
|
||||
//
|
||||
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
// PART OF THIS FILE AT ALL TIMES.
|
||||
//
|
||||
//----------------------------------------------------------------------------
|
||||
// User entered comments
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||||
//----------------------------------------------------------------------------
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// None
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||||
//
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//----------------------------------------------------------------------------
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// "Output Output Phase Duty Pk-to-Pk Phase"
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// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
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//----------------------------------------------------------------------------
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// CLK_OUT1___120.000______0.000______50.0______230.987____300.046
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// CLK_OUT2____60.000______0.000______50.0______254.384____300.046
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//
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//----------------------------------------------------------------------------
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// "Input Clock Freq (MHz) Input Jitter (UI)"
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//----------------------------------------------------------------------------
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// __primary_________100.000____________0.010
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`timescale 1ps/1ps
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(* CORE_GENERATION_INFO = "Clock_120MHz,clk_wiz_v3_6,{component_name=Clock_120MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.000,clkin2_period=8.333,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
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module Clock_120MHz
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(// Clock in ports
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input CLK_IN,
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// Clock out ports
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output CLK_OUT_120MHz,
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output CLK_OUT_60MHz
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);
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// Input buffering
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//------------------------------------
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IBUFG clkin1_buf
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(.O (clkin1),
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.I (CLK_IN));
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// Clocking primitive
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//------------------------------------
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// Instantiation of the MMCM primitive
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// * Unused inputs are tied off
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// * Unused outputs are labeled unused
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wire [15:0] do_unused;
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wire drdy_unused;
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wire psdone_unused;
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wire locked_unused;
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wire clkfbout;
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wire clkfbout_buf;
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wire clkfboutb_unused;
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wire clkout0b_unused;
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wire clkout1b_unused;
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wire clkout2_unused;
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wire clkout2b_unused;
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wire clkout3_unused;
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wire clkout3b_unused;
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wire clkout4_unused;
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wire clkout5_unused;
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wire clkout6_unused;
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wire clkfbstopped_unused;
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wire clkinstopped_unused;
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MMCME2_ADV
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#(.BANDWIDTH ("OPTIMIZED"),
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.CLKOUT4_CASCADE ("FALSE"),
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.COMPENSATION ("ZHOLD"),
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.STARTUP_WAIT ("FALSE"),
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.DIVCLK_DIVIDE (5),
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.CLKFBOUT_MULT_F (51.000),
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.CLKFBOUT_PHASE (0.000),
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.CLKFBOUT_USE_FINE_PS ("FALSE"),
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.CLKOUT0_DIVIDE_F (8.500),
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.CLKOUT0_PHASE (0.000),
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.CLKOUT0_DUTY_CYCLE (0.500),
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.CLKOUT0_USE_FINE_PS ("FALSE"),
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.CLKOUT1_DIVIDE (17),
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.CLKOUT1_PHASE (0.000),
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.CLKOUT1_DUTY_CYCLE (0.500),
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.CLKOUT1_USE_FINE_PS ("FALSE"),
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.CLKIN1_PERIOD (10.000),
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.REF_JITTER1 (0.010))
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mmcm_adv_inst
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// Output clocks
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(.CLKFBOUT (clkfbout),
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.CLKFBOUTB (clkfboutb_unused),
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.CLKOUT0 (clkout0),
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.CLKOUT0B (clkout0b_unused),
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.CLKOUT1 (clkout1),
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.CLKOUT1B (clkout1b_unused),
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.CLKOUT2 (clkout2_unused),
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.CLKOUT2B (clkout2b_unused),
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.CLKOUT3 (clkout3_unused),
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.CLKOUT3B (clkout3b_unused),
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.CLKOUT4 (clkout4_unused),
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.CLKOUT5 (clkout5_unused),
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.CLKOUT6 (clkout6_unused),
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// Input clock control
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.CLKFBIN (clkfbout_buf),
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.CLKIN1 (clkin1),
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.CLKIN2 (1'b0),
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// Tied to always select the primary input clock
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.CLKINSEL (1'b1),
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// Ports for dynamic reconfiguration
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.DADDR (7'h0),
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.DCLK (1'b0),
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.DEN (1'b0),
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.DI (16'h0),
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.DO (do_unused),
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.DRDY (drdy_unused),
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.DWE (1'b0),
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// Ports for dynamic phase shift
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.PSCLK (1'b0),
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.PSEN (1'b0),
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.PSINCDEC (1'b0),
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.PSDONE (psdone_unused),
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// Other control and status signals
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.LOCKED (locked_unused),
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.CLKINSTOPPED (clkinstopped_unused),
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.CLKFBSTOPPED (clkfbstopped_unused),
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.PWRDWN (1'b0),
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.RST (1'b0));
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// Output buffering
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//-----------------------------------
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BUFG clkf_buf
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(.O (clkfbout_buf),
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.I (clkfbout));
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BUFG clkout1_buf
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(.O (CLK_OUT_120MHz),
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.I (clkout0));
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BUFG clkout2_buf
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(.O (CLK_OUT_60MHz),
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.I (clkout1));
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endmodule
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@@ -0,0 +1,109 @@
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############################ CLOCK INPUT SI5351 100MHz ########################
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NET "CLK_IN" CLOCK_DEDICATED_ROUTE = TRUE;
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NET "CLK_IN" LOC = N11 | IOSTANDARD = LVCMOS33;
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NET "CLK_IN" TNM_NET = "CLK_IN";
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TIMESPEC "TS_CLK_IN" = PERIOD "clk_in" 10 ns HIGH 50%;# 100 MHz clock
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############################### Microcontroller ###############################
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NET "STM32_SCLK" LOC = E12 | IOSTANDARD = LVCMOS33;
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NET "STM32_MOSI" LOC = H13 | IOSTANDARD = LVCMOS33;
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NET "STM32_MISO" LOC = G14 | IOSTANDARD = LVCMOS33;
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NET "STM32_CS_ADAR_1" LOC = F14 | IOSTANDARD = LVCMOS33;
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NET "STM32_CS_ADAR_2" LOC = H16 | IOSTANDARD = LVCMOS33;
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NET "STM32_CS_ADAR_3" LOC = G16 | IOSTANDARD = LVCMOS33;
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NET "STM32_CS_ADAR_4" LOC = J15 | IOSTANDARD = LVCMOS33;
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NET "DIG_0" LOC = F13 | IOSTANDARD = LVCMOS33;
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NET "DIG_1" LOC = E16 | IOSTANDARD = LVCMOS33;
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NET "DIG_2" LOC = D16 | IOSTANDARD = LVCMOS33;
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NET "DIG_3" LOC = F15 | IOSTANDARD = LVCMOS33;
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#NET "DIG_4" LOC = E15 | IOSTANDARD = LVCMOS33;
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#NET "DIG_5" LOC = H11 | IOSTANDARD = LVCMOS33;
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#NET "DIG_6" LOC = G12 | IOSTANDARD = LVCMOS33;
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#NET "DIG_7" LOC = H12 | IOSTANDARD = LVCMOS33;
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############################### DAC AD9708AR ##################################
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NET "DAC_DATA[0]" LOC = A14 | IOSTANDARD = LVCMOS33;
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NET "DAC_DATA[1]" LOC = A13 | IOSTANDARD = LVCMOS33;
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NET "DAC_DATA[2]" LOC = A12 | IOSTANDARD = LVCMOS33;
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NET "DAC_DATA[3]" LOC = B11 | IOSTANDARD = LVCMOS33;
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NET "DAC_DATA[4]" LOC = B10 | IOSTANDARD = LVCMOS33;
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NET "DAC_DATA[5]" LOC = A10 | IOSTANDARD = LVCMOS33;
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NET "DAC_DATA[6]" LOC = A9 | IOSTANDARD = LVCMOS33;
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NET "DAC_DATA[7]" LOC = A8 | IOSTANDARD = LVCMOS33;
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NET "DAC_SLEEP" LOC = A15 | IOSTANDARD = LVCMOS33;
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NET "DAC_CLOCK" LOC = C13 | IOSTANDARD = LVCMOS33 | DRIVE = 16 | SLEW = FAST;
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############################### MIXER LTC5552 ##################################
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NET "MIX_TX_EN" LOC = C11 | IOSTANDARD = LVCMOS33;
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NET "MIX_RX_EN" LOC = M6 | IOSTANDARD = LVCMOS33;
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############################### ADC MAX1449 ##################################
|
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NET "ADC_DATA[0]" LOC = T8 | IOSTANDARD = LVCMOS33;
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NET "ADC_DATA[1]" LOC = T9 | IOSTANDARD = LVCMOS33;
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NET "ADC_DATA[2]" LOC = T10 | IOSTANDARD = LVCMOS33;
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NET "ADC_DATA[3]" LOC = R11 | IOSTANDARD = LVCMOS33;
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NET "ADC_DATA[4]" LOC = T12 | IOSTANDARD = LVCMOS33;
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NET "ADC_DATA[5]" LOC = T13 | IOSTANDARD = LVCMOS33;
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NET "ADC_DATA[6]" LOC = T14 | IOSTANDARD = LVCMOS33;
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NET "ADC_DATA[7]" LOC = T15 | IOSTANDARD = LVCMOS33;
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||||
NET "ADC_DATA[8]" LOC = R15 | IOSTANDARD = LVCMOS33;
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NET "ADC_DATA[9]" LOC = R16 | IOSTANDARD = LVCMOS33;
|
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NET "ADC_PD" LOC = M16 | IOSTANDARD = LVCMOS33;
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NET "ADC_OE" LOC = N16 | IOSTANDARD = LVCMOS33;
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NET "ADC_CLOCK" LOC = P14 | IOSTANDARD = LVCMOS33 | DRIVE = 16 | SLEW = FAST;
|
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|
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############################# RF SWITCH M3SWA2-34DR+ ##############################
|
||||
NET "M3S_VCTRL" LOC = P8 | IOSTANDARD = LVCMOS33;
|
||||
|
||||
############################### ADAR1000_1_2_3_4 ##################################
|
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NET "SPI_SCLK_1V8" LOC = F5 | IOSTANDARD = LVCMOS18 | DRIVE = 16 | SLEW = FAST;
|
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NET "SPI_MOSI_1V8" LOC = B5 | IOSTANDARD = LVCMOS18;
|
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NET "SPI_MISO_1V8" LOC = A5 | IOSTANDARD = LVCMOS18;
|
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NET "CS_ADAR_1V8_1" LOC = E6 | IOSTANDARD = LVCMOS18;
|
||||
NET "CS_ADAR_1V8_2" LOC = B7 | IOSTANDARD = LVCMOS18;
|
||||
NET "CS_ADAR_1V8_3" LOC = A7 | IOSTANDARD = LVCMOS18;
|
||||
NET "CS_ADAR_1V8_4" LOC = B6 | IOSTANDARD = LVCMOS18;
|
||||
|
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NET "ADAR_TR1" LOC = A4 | IOSTANDARD = LVCMOS18;
|
||||
NET "ADAR_TR2" LOC = B4 | IOSTANDARD = LVCMOS18;
|
||||
NET "ADAR_TR3" LOC = A3 | IOSTANDARD = LVCMOS18;
|
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NET "ADAR_TR4" LOC = C7 | IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "ADAR_TX_LOAD_1" LOC = C6 | IOSTANDARD = LVCMOS18;
|
||||
NET "ADAR_TX_LOAD_2" LOC = G1 | IOSTANDARD = LVCMOS18;
|
||||
NET "ADAR_TX_LOAD_3" LOC = G4 | IOSTANDARD = LVCMOS18;
|
||||
NET "ADAR_TX_LOAD_4" LOC = E1 | IOSTANDARD = LVCMOS18;
|
||||
|
||||
NET "ADAR_RX_LOAD_1" LOC = D6 | IOSTANDARD = LVCMOS18;
|
||||
NET "ADAR_RX_LOAD_2" LOC = G2 | IOSTANDARD = LVCMOS18;
|
||||
NET "ADAR_RX_LOAD_3" LOC = G5 | IOSTANDARD = LVCMOS18;
|
||||
NET "ADAR_RX_LOAD_4" LOC = F2 | IOSTANDARD = LVCMOS18;
|
||||
|
||||
############################### FT2232HQ ##################################
|
||||
NET "AD_Bus[0]" LOC = N1 | IOSTANDARD = LVCMOS33;
|
||||
NET "AD_Bus[1]" LOC = P1 | IOSTANDARD = LVCMOS33;
|
||||
NET "AD_Bus[2]" LOC = R1 | IOSTANDARD = LVCMOS33;
|
||||
NET "AD_Bus[3]" LOC = N2 | IOSTANDARD = LVCMOS33;
|
||||
NET "AD_Bus[4]" LOC = R2 | IOSTANDARD = LVCMOS33;
|
||||
NET "AD_Bus[5]" LOC = T2 | IOSTANDARD = LVCMOS33;
|
||||
NET "AD_Bus[6]" LOC = N3 | IOSTANDARD = LVCMOS33;
|
||||
NET "AD_Bus[7]" LOC = P3 | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "FT_OE" LOC = L5 | IOSTANDARD = LVCMOS33;
|
||||
NET "FT_RD" LOC = L4 | IOSTANDARD = LVCMOS33;
|
||||
NET "FT_WR" LOC = P4 | IOSTANDARD = LVCMOS33;
|
||||
NET "FT_TXE" LOC = N4 | IOSTANDARD = LVCMOS33;
|
||||
#NET "FT_RXF" LOC = T3 | IOSTANDARD = LVCMOS33;
|
||||
#NET "FT_SIWA" LOC = P5 | IOSTANDARD = LVCMOS33;
|
||||
|
||||
|
||||
NET "FT_CLKOUT" CLOCK_DEDICATED_ROUTE = TRUE;
|
||||
NET "FT_CLKOUT" LOC = T4 | IOSTANDARD = LVCMOS33;
|
||||
|
||||
NET "FT_CLKOUT" TNM_NET = "FT_CLKOUT";
|
||||
TIMESPEC "TS_FT_CLKOUT" = PERIOD "FT_CLKOUT" 16.67 ns HIGH 50%;# 60 MHz clock
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,262 @@
|
||||
|
||||
|
||||
############################CLOCK INPUT SI5351 100MHz########################
|
||||
|
||||
set_property PACKAGE_PIN N11 [get_ports CLK_IN]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports CLK_IN]
|
||||
create_clock -period 10.0 [get_ports CLK_IN] #100 MHz clock
|
||||
|
||||
###############################Microcontroller###############################
|
||||
|
||||
set_property PACKAGE_PIN E12 [get_ports STM32_SCLK]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports STM32_SCLK]
|
||||
|
||||
set_property PACKAGE_PIN H13 [get_ports STM32_MOSI]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports STM32_MOSI]
|
||||
|
||||
set_property PACKAGE_PIN G14 [get_ports STM32_MISO]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports STM32_MISO]
|
||||
|
||||
set_property PACKAGE_PIN F14 [get_ports STM32_CS_ADAR_1]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports STM32_CS_ADAR_1]
|
||||
|
||||
set_property PACKAGE_PIN H16 [get_ports STM32_CS_ADAR_2]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports STM32_CS_ADAR_2]
|
||||
|
||||
set_property PACKAGE_PIN G16 [get_ports STM32_CS_ADAR_3]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports STM32_CS_ADAR_3]
|
||||
|
||||
set_property PACKAGE_PIN J15 [get_ports STM32_CS_ADAR_4]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports STM32_CS_ADAR_4]
|
||||
|
||||
set_property PACKAGE_PIN F13 [get_ports DIG_0]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DIG_0]
|
||||
|
||||
set_property PACKAGE_PIN E16 [get_ports DIG_1]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DIG_1]
|
||||
|
||||
set_property PACKAGE_PIN D16 [get_ports DIG_2]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DIG_2]
|
||||
|
||||
set_property PACKAGE_PIN F15 [get_ports DIG_3]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DIG_3
|
||||
|
||||
set_property PACKAGE_PIN E15 [get_ports DIG_4]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DIG_4]
|
||||
|
||||
set_property PACKAGE_PIN H11 [get_ports DIG_5]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DIG_5]
|
||||
|
||||
set_property PACKAGE_PIN G12 [get_ports DIG_6]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DIG_6]
|
||||
|
||||
set_property PACKAGE_PIN H12 [get_ports DIG_7]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DIG_7]
|
||||
|
||||
###############################DAC AD9708AR##################################
|
||||
|
||||
set_property PACKAGE_PIN A14 [get_ports DAC_0] #LSB
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DAC_0]
|
||||
|
||||
set_property PACKAGE_PIN A13 [get_ports DAC_1]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DAC_1]
|
||||
|
||||
set_property PACKAGE_PIN A12 [get_ports DAC_2]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DAC_2]
|
||||
|
||||
set_property PACKAGE_PIN B11 [get_ports DAC_3]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DAC_3]
|
||||
|
||||
set_property PACKAGE_PIN B10 [get_ports DAC_4]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DAC_4]
|
||||
|
||||
set_property PACKAGE_PIN A10 [get_ports DAC_5]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DAC_5]
|
||||
|
||||
set_property PACKAGE_PIN A9 [get_ports DAC_6]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DAC_6]
|
||||
|
||||
set_property PACKAGE_PIN A8 [get_ports DAC_7] #MSB
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DAC_7]
|
||||
|
||||
set_property PACKAGE_PIN A15 [get_ports DAC_SLEEP] #active high
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DAC_SLEEP]
|
||||
|
||||
set_property PACKAGE_PIN C13 [get_ports DAC_CLK] #data latched on pos. edge of clock # C13 should be an MRCC/SRCC pin
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports DAC_CLK]
|
||||
set_property DRIVE 16 [get_ports DAC_CLK] # Adjust drive strength if needed
|
||||
set_property SLEW FAST [get_ports DAC_CLK] # Ensure fast edge transition
|
||||
|
||||
###############################MIXER LTC5552##################################
|
||||
|
||||
set_property PACKAGE_PIN C11 [get_ports MIX_TX_EN]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports MIX_TX_EN]
|
||||
|
||||
set_property PACKAGE_PIN M6 [get_ports MIX_RX_EN]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports MIX_RX_EN]
|
||||
|
||||
###############################ADC MAX1449##################################
|
||||
|
||||
set_property PACKAGE_PIN T8 [get_ports ADC_0] #LSB
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ADC_0]
|
||||
|
||||
set_property PACKAGE_PIN T9 [get_ports ADC_1]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ADC_1]
|
||||
|
||||
set_property PACKAGE_PIN T10 [get_ports ADC_2]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ADC_2]
|
||||
|
||||
set_property PACKAGE_PIN R11 [get_ports ADC_3]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ADC_3]
|
||||
|
||||
set_property PACKAGE_PIN T12 [get_ports ADC_4]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ADC_4]
|
||||
|
||||
set_property PACKAGE_PIN T13 [get_ports ADC_5]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ADC_5]
|
||||
|
||||
set_property PACKAGE_PIN T14 [get_ports ADC_6]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ADC_6]
|
||||
|
||||
set_property PACKAGE_PIN T15 [get_ports ADC_7]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ADC_7]
|
||||
|
||||
set_property PACKAGE_PIN R14 [get_ports ADC_8]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ADC_8]
|
||||
|
||||
set_property PACKAGE_PIN R16 [get_ports ADC_9] #MSB
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ADC_9]
|
||||
|
||||
set_property PACKAGE_PIN M16 [get_ports ADC_PD]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ADC_PD]
|
||||
|
||||
set_property PACKAGE_PIN N16 [get_ports ADC_OE]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ADC_OE]
|
||||
|
||||
set_property PACKAGE_PIN P14 [get_ports ADC_CLK] # P14 should be an MRCC/SRCC pin
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports ADC_CLK]
|
||||
set_property DRIVE 16 [get_ports ADC_CLK] # Adjust drive strength if needed
|
||||
set_property SLEW FAST [get_ports ADC_CLK] # Ensure fast edge transition
|
||||
|
||||
#############################RF SWITCH M3SWA2-34DR+##############################
|
||||
|
||||
set_property PACKAGE_PIN P8 [get_ports M3S_VCTRL]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports M3S_VCTRL]
|
||||
|
||||
###############################ADAR1000_1_2_3_4##################################
|
||||
|
||||
set_property PACKAGE_PIN F5 [get_ports SPI_SCLK_1V8]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports SPI_SCLK_1V8]
|
||||
set_property DRIVE 16 [get_ports SPI_SCLK_1V8] # Adjust drive strength if needed
|
||||
set_property SLEW FAST [get_ports SPI_SCLK_1V8] # Ensure fast edge transition
|
||||
|
||||
set_property PACKAGE_PIN B5 [get_ports SPI_MOSI_1V8]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports SPI_MOSI_1V8]
|
||||
|
||||
set_property PACKAGE_PIN A5 [get_ports SPI_MISO_1V8]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports SPI_MISO_1V8]
|
||||
|
||||
set_property PACKAGE_PIN E6 [get_ports CS_ADAR_1V8_1]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports CS_ADAR_1V8_1]
|
||||
|
||||
set_property PACKAGE_PIN B7 [get_ports CS_ADAR_1V8_2]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports CS_ADAR_1V8_2]
|
||||
|
||||
set_property PACKAGE_PIN A7 [get_ports CS_ADAR_1V8_3]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports CS_ADAR_1V8_3]
|
||||
|
||||
set_property PACKAGE_PIN B6 [get_ports CS_ADAR_1V8_4]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports CS_ADAR_1V8_4]
|
||||
|
||||
set_property PACKAGE_PIN A4 [get_ports ADAR_TR_1]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADAR_TR_1]
|
||||
|
||||
set_property PACKAGE_PIN B4 [get_ports ADAR_TR_2]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADAR_TR_2]
|
||||
|
||||
set_property PACKAGE_PIN A3 [get_ports ADAR_TR_3]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADAR_TR_3]
|
||||
|
||||
set_property PACKAGE_PIN C7 [get_ports ADAR_TR_4]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADAR_TR_4]
|
||||
|
||||
set_property PACKAGE_PIN C6 [get_ports ADAR_TX_LOAD_1]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADAR_TX_LOAD_1]
|
||||
|
||||
set_property PACKAGE_PIN G1 [get_ports ADAR_TX_LOAD_2]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADAR_TX_LOAD_2]
|
||||
|
||||
set_property PACKAGE_PIN G4 [get_ports ADAR_TX_LOAD_3]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADAR_TX_LOAD_3]
|
||||
|
||||
set_property PACKAGE_PIN E1 [get_ports ADAR_TX_LOAD_4]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADAR_TX_LOAD_4]
|
||||
|
||||
set_property PACKAGE_PIN D6 [get_ports ADAR_RX_LOAD_1]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADAR_RX_LOAD_1]
|
||||
|
||||
set_property PACKAGE_PIN G2 [get_ports ADAR_RX_LOAD_2]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADAR_RX_LOAD_2]
|
||||
|
||||
set_property PACKAGE_PIN G5 [get_ports ADAR_RX_LOAD_3]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADAR_RX_LOAD_3]
|
||||
|
||||
set_property PACKAGE_PIN F2 [get_ports ADAR_RX_LOAD_4]
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports ADAR_RX_LOAD_4]
|
||||
|
||||
###############################FT2232HQ##################################
|
||||
|
||||
set_property PACKAGE_PIN N1 [get_ports FT_D0] #LSB
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_D0]
|
||||
|
||||
set_property PACKAGE_PIN P1 [get_ports FT_D1]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_D1]
|
||||
|
||||
set_property PACKAGE_PIN R1 [get_ports FT_D2]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_D2]
|
||||
|
||||
set_property PACKAGE_PIN N2 [get_ports FT_D3]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_D3]
|
||||
|
||||
set_property PACKAGE_PIN R2 [get_ports FT_D4]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_D4]
|
||||
|
||||
set_property PACKAGE_PIN T2 [get_ports FT_D5]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_D5]
|
||||
|
||||
set_property PACKAGE_PIN N3 [get_ports FT_D6]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_D6]
|
||||
|
||||
set_property PACKAGE_PIN P3 [get_ports FT_D7] #MSB
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_D7]
|
||||
|
||||
set_property PACKAGE_PIN L5 [get_ports FT_OE]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_OE]
|
||||
|
||||
set_property PACKAGE_PIN L4 [get_ports FT_RD]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_RD]
|
||||
|
||||
set_property PACKAGE_PIN P4 [get_ports FT_WR]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_WR]
|
||||
|
||||
set_property PACKAGE_PIN N4 [get_ports FT_TXE]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_TXE]
|
||||
|
||||
set_property PACKAGE_PIN T3 [get_ports FT_RXF]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_RXF]
|
||||
|
||||
set_property PACKAGE_PIN P5 [get_ports FT_SIWA]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_SIWA]
|
||||
|
||||
set_property PACKAGE_PIN T4 [get_ports FT_CLKOUT]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports FT_CLKOUT]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,40 @@
|
||||
module adc_interface (
|
||||
input wire CLK_IN, // 100 MHz clock input
|
||||
input wire rst, // Reset signal
|
||||
output wire ADC_CLK, // 60 MHz clock output to ADC
|
||||
output reg ADC_OE, // Output enable (0 = enable)
|
||||
output reg ADC_PD, // Power down (0 = normal operation)
|
||||
input wire [9:0] ADC_DATA, // 10-bit parallel ADC data input
|
||||
output reg [9:0] sampled_data // Captured ADC data
|
||||
);
|
||||
|
||||
// Clocking Wizard or PLL/MMCM should be instantiated here to generate 60MHz ADC_CLK
|
||||
wire clk_60MHz;
|
||||
|
||||
// Instantiate clock generator (example with MMCM/PLL instantiation needed)
|
||||
clk_wiz_0 clk_gen (
|
||||
.clk_in1(CLK_IN),
|
||||
.clk_out1(clk_60MHz), // 60 MHz clock output
|
||||
.reset(1'b0),
|
||||
.locked()
|
||||
);
|
||||
|
||||
assign ADC_CLK = clk_60MHz;
|
||||
|
||||
// ADC control signals initialization
|
||||
always @(posedge CLK_IN or posedge rst) begin
|
||||
if (rst) begin
|
||||
ADC_OE <= 1'b1; // Default disabled
|
||||
ADC_PD <= 1'b1; // Default power down
|
||||
end else begin
|
||||
ADC_OE <= 1'b0; // Enable ADC
|
||||
ADC_PD <= 1'b0; // Normal operation
|
||||
end
|
||||
end
|
||||
|
||||
// Capture ADC data on ADC_CLK rising edge
|
||||
always @(posedge clk_60MHz) begin
|
||||
sampled_data <= ADC_DATA;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,137 @@
|
||||
`timescale 1ns / 1ps
|
||||
module ft2232h_245_sync(input clk,//input 50_MHz
|
||||
input reset,
|
||||
input [7:0] DAC_DATA,
|
||||
input [7:0] AD_Bus,
|
||||
output reg oe,
|
||||
output reg rd,
|
||||
input txe,
|
||||
output reg wr,
|
||||
input clkout_ft2232);
|
||||
//output reg oe);
|
||||
|
||||
//wire CLK_OUT_PLL; //Output from PLL_IP_clock
|
||||
|
||||
|
||||
reg txe_n;
|
||||
reg wr_n;
|
||||
|
||||
reg oe_n = 1'b1;
|
||||
reg rd_n = 1'b1;
|
||||
|
||||
reg Flag_tx = 0;
|
||||
|
||||
reg data_en_1 = 0;
|
||||
reg data_en_2 = 0;
|
||||
|
||||
reg [7:0] data_o = 8'b00000000;
|
||||
|
||||
|
||||
parameter TX_RX_0 = 3'b000;
|
||||
parameter TX_1 = 3'b001;
|
||||
parameter TX_2 = 3'b010;
|
||||
parameter TX_3 = 3'b011;
|
||||
|
||||
reg [3:0] state;
|
||||
|
||||
reg [3:0] state_data;
|
||||
|
||||
reg counter = 1'b0;
|
||||
|
||||
begin
|
||||
|
||||
assign AD_Bus = (data_en_1 == 1'b1) ? DAC_DATA : 8'bz;
|
||||
|
||||
always @ (posedge clkout_ft2232)
|
||||
begin
|
||||
if ((txe_n == 0) && Flag_tx)
|
||||
begin
|
||||
data_en_1 = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
wr = wr_n;
|
||||
txe_n = txe;
|
||||
oe = oe_n;
|
||||
rd = rd_n;
|
||||
end
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset)
|
||||
begin
|
||||
state = TX_RX_0;
|
||||
state_data = 0;
|
||||
counter = 1'b0;
|
||||
wr_n = 1'b1;
|
||||
end
|
||||
else
|
||||
|
||||
begin
|
||||
|
||||
|
||||
case(state)
|
||||
|
||||
TX_RX_0: begin
|
||||
if (txe_n == 0)
|
||||
begin
|
||||
state = TX_1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
state = TX_RX_0;
|
||||
wr_n = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
TX_1 : begin
|
||||
if(txe_n == 0)
|
||||
begin
|
||||
counter = counter + 1;
|
||||
if(counter == 1'b1)
|
||||
begin
|
||||
counter = 1'b0;
|
||||
state = TX_2;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
wr_n = 1'b1;
|
||||
state = TX_RX_0;
|
||||
end
|
||||
end
|
||||
|
||||
TX_2 : begin
|
||||
wr_n = 1'b0;
|
||||
counter = counter + 1;
|
||||
if(counter == 1'b1)
|
||||
begin
|
||||
counter = 1'b0;
|
||||
state = TX_3;
|
||||
end
|
||||
end
|
||||
|
||||
TX_3 : begin
|
||||
if(txe_n == 0)
|
||||
begin
|
||||
Flag_tx = 1'b1;
|
||||
state = TX_3;
|
||||
end
|
||||
else
|
||||
begin
|
||||
state = TX_RX_0;
|
||||
wr_n = 1'b1;
|
||||
Flag_tx = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,253 @@
|
||||
module fpga_controller (
|
||||
input wire CLK_IN, // 100MHz input clock
|
||||
input wire DIG_0, // Control signal
|
||||
input wire DIG_1, //reset from µC
|
||||
input wire [7:0] ADC_DATA, // 8-bit data from ADC
|
||||
output wire DAC_CLOCK, // Clock for DAC
|
||||
output reg [7:0] DAC_DATA, // Data to DAC
|
||||
output reg [7:0] FT_DATA, // Data to FT2232H
|
||||
output reg FT_WR, // Write control for FT2232H
|
||||
input FT_TXE,
|
||||
input wire FT_CLKOUT,
|
||||
output reg FT_OE,
|
||||
output reg FT_RD
|
||||
);
|
||||
|
||||
// Clock generation (assumes DAC needs 120MHz, adjust if needed)
|
||||
reg [2:0] clk_div = 0;
|
||||
reg dac_clk_reg = 0;
|
||||
always @(posedge CLK_IN) begin
|
||||
clk_div <= clk_div + 1;
|
||||
if (clk_div == 2) begin
|
||||
dac_clk_reg <= ~dac_clk_reg;
|
||||
clk_div <= 0;
|
||||
end
|
||||
end
|
||||
assign DAC_CLOCK = dac_clk_reg;
|
||||
|
||||
// Instantiate waveform generator
|
||||
waveform_generator waveform_gen (
|
||||
.CLK_IN(CLK_IN),
|
||||
.DAC_CLOCK(DAC_CLOCK),
|
||||
.DAC_DATA(DAC_DATA)
|
||||
);
|
||||
|
||||
// Instantiate ADC interface
|
||||
wire [7:0] adc_output;
|
||||
adc_interface adc_intf (
|
||||
.CLK_IN(CLK_IN),
|
||||
.ADC_DATA(adc_output)
|
||||
);
|
||||
|
||||
// Instantiate FIFO for FT2232H data buffering
|
||||
ft2232h_245_sync ft2232h_245_sync (
|
||||
.clk,//input 50_MHz
|
||||
.reset,
|
||||
.DAC_DATA,
|
||||
.AD_Bus,
|
||||
.oe,
|
||||
.rd,
|
||||
.txe,
|
||||
.wr,
|
||||
.clkout_ft2232
|
||||
);
|
||||
|
||||
// Data handling logic
|
||||
always @(posedge CLK_IN) begin
|
||||
if (!DIG_0) begin
|
||||
FT_DATA <= fifo_out; // Send ADC data to FT2232H
|
||||
FT_WR <= ~fifo_empty; // Write when FIFO is not empty
|
||||
end else begin
|
||||
FT_WR <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// Waveform Generator Module
|
||||
module waveform_generator (
|
||||
input wire CLK_IN,
|
||||
output reg DAC_CLOCK,
|
||||
output reg [7:0] DAC_DATA
|
||||
);
|
||||
reg [2:0] clk_div = 0;
|
||||
always @(posedge CLK_IN) begin
|
||||
clk_div <= clk_div + 1;
|
||||
if (clk_div == 2) begin
|
||||
DAC_CLOCK <= ~DAC_CLOCK;
|
||||
clk_div <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
parameter integer n = 31;
|
||||
reg [7:0] waveform_LUT [0:n-1];
|
||||
initial begin
|
||||
waveform_LUT[0] = 8'h80; waveform_LUT[1] = 8'h89;
|
||||
waveform_LUT[2] = 8'h99; waveform_LUT[3] = 8'hAE;
|
||||
waveform_LUT[4] = 8'hC7; waveform_LUT[5] = 8'hE1;
|
||||
waveform_LUT[6] = 8'hF6; waveform_LUT[7] = 8'hFF;
|
||||
waveform_LUT[8] = 8'hF4; waveform_LUT[9] = 8'hCF;
|
||||
waveform_LUT[10] = 8'h92; waveform_LUT[11] = 8'h4B;
|
||||
waveform_LUT[12] = 8'h11; waveform_LUT[13] = 8'h02;
|
||||
waveform_LUT[14] = 8'h2E; waveform_LUT[15] = 8'h8A;
|
||||
waveform_LUT[16] = 8'hE4; waveform_LUT[17] = 8'hFC;
|
||||
waveform_LUT[18] = 8'hB6; waveform_LUT[19] = 8'h3F;
|
||||
waveform_LUT[20] = 8'h00; waveform_LUT[21] = 8'h41;
|
||||
waveform_LUT[22] = 8'hC8; waveform_LUT[23] = 8'hFC;
|
||||
waveform_LUT[24] = 8'h91; waveform_LUT[25] = 8'h0C;
|
||||
waveform_LUT[26] = 8'h2E; waveform_LUT[27] = 8'hD0;
|
||||
waveform_LUT[28] = 8'hED; waveform_LUT[29] = 8'h4A;
|
||||
waveform_LUT[30] = 8'h09;
|
||||
end
|
||||
|
||||
reg [9:0] index = 0;
|
||||
always @(posedge DAC_CLOCK) begin
|
||||
DAC_DATA <= waveform_LUT[index];
|
||||
index <= (index >= n - 1) ? 0 : index + 1;
|
||||
end
|
||||
endmodule
|
||||
|
||||
// ADC Interface Module
|
||||
module adc_interface (
|
||||
input wire CLK_IN,
|
||||
output reg [7:0] ADC_DATA
|
||||
);
|
||||
always @(posedge CLK_IN) begin
|
||||
ADC_DATA <= $random; // Simulate ADC data
|
||||
end
|
||||
endmodule
|
||||
|
||||
// FIFO Transmitter Module
|
||||
module ft2232h_245_sync(input clk,//input 50_MHz
|
||||
input reset,
|
||||
input [7:0] DAC_DATA,
|
||||
input [7:0] AD_Bus,
|
||||
output reg oe,
|
||||
output reg rd,
|
||||
input txe,
|
||||
output reg wr,
|
||||
input clkout_ft2232);
|
||||
//output reg oe);
|
||||
|
||||
//wire CLK_OUT_PLL; //Output from PLL_IP_clock
|
||||
|
||||
|
||||
reg txe_n;
|
||||
reg wr_n;
|
||||
|
||||
reg oe_n = 1'b1;
|
||||
reg rd_n = 1'b1;
|
||||
|
||||
reg Flag_tx = 0;
|
||||
|
||||
reg data_en_1 = 0;
|
||||
reg data_en_2 = 0;
|
||||
|
||||
reg [7:0] data_o = 8'b00000000;
|
||||
|
||||
|
||||
parameter TX_RX_0 = 3'b000;
|
||||
parameter TX_1 = 3'b001;
|
||||
parameter TX_2 = 3'b010;
|
||||
parameter TX_3 = 3'b011;
|
||||
|
||||
reg [3:0] state;
|
||||
|
||||
reg [3:0] state_data;
|
||||
|
||||
reg counter = 1'b0;
|
||||
|
||||
begin
|
||||
|
||||
assign AD_Bus = (data_en_1 == 1'b1) ? DAC_DATA : 8'bz;
|
||||
|
||||
always @ (posedge clkout_ft2232)
|
||||
begin
|
||||
if ((txe_n == 0) && Flag_tx)
|
||||
begin
|
||||
data_en_1 = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @ (posedge clk)
|
||||
begin
|
||||
wr = wr_n;
|
||||
txe_n = txe;
|
||||
oe = oe_n;
|
||||
rd = rd_n;
|
||||
end
|
||||
|
||||
always @ (posedge clk)
|
||||
if (reset)
|
||||
begin
|
||||
state = TX_RX_0;
|
||||
state_data = 0;
|
||||
counter = 1'b0;
|
||||
wr_n = 1'b1;
|
||||
end
|
||||
else
|
||||
|
||||
begin
|
||||
|
||||
|
||||
case(state)
|
||||
|
||||
TX_RX_0: begin
|
||||
if (txe_n == 0)
|
||||
begin
|
||||
state = TX_1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
state = TX_RX_0;
|
||||
wr_n = 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
TX_1 : begin
|
||||
if(txe_n == 0)
|
||||
begin
|
||||
counter = counter + 1;
|
||||
if(counter == 1'b1)
|
||||
begin
|
||||
counter = 1'b0;
|
||||
state = TX_2;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
wr_n = 1'b1;
|
||||
state = TX_RX_0;
|
||||
end
|
||||
end
|
||||
|
||||
TX_2 : begin
|
||||
wr_n = 1'b0;
|
||||
counter = counter + 1;
|
||||
if(counter == 1'b1)
|
||||
begin
|
||||
counter = 1'b0;
|
||||
state = TX_3;
|
||||
end
|
||||
end
|
||||
|
||||
TX_3 : begin
|
||||
if(txe_n == 0)
|
||||
begin
|
||||
Flag_tx = 1'b1;
|
||||
state = TX_3;
|
||||
end
|
||||
else
|
||||
begin
|
||||
state = TX_RX_0;
|
||||
wr_n = 1'b1;
|
||||
Flag_tx = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
||||
@@ -0,0 +1,56 @@
|
||||
module spi_level_shifter (
|
||||
input wire STM32_SCLK,
|
||||
input wire STM32_MOSI,
|
||||
output wire STM32_MISO,
|
||||
input wire STM32_CS_ADAR1,
|
||||
input wire STM32_CS_ADAR2,
|
||||
input wire STM32_CS_ADAR3,
|
||||
input wire STM32_CS_ADAR4,
|
||||
input wire DIG_0,
|
||||
input wire DIG_1,
|
||||
input wire DIG_2,
|
||||
output wire SPI_SCLK_1V8,
|
||||
output wire SPI_MOSI_1V8,
|
||||
input wire SPI_MISO_1V8,
|
||||
output wire CS_ADAR_1V8_1,
|
||||
output wire CS_ADAR_1V8_2,
|
||||
output wire CS_ADAR_1V8_3,
|
||||
output wire CS_ADAR_1V8_4,
|
||||
output reg ADAR_TR1,
|
||||
output reg ADAR_TR2,
|
||||
output reg ADAR_TR3,
|
||||
output reg ADAR_TR4,
|
||||
output reg M3S_VCTRL,
|
||||
output wire MIX_TX_EN,
|
||||
output wire MIX_RX_EN
|
||||
);
|
||||
|
||||
assign SPI_SCLK_1V8 = STM32_SCLK;
|
||||
assign SPI_MOSI_1V8 = STM32_MOSI;
|
||||
assign STM32_MISO = SPI_MISO_1V8;
|
||||
|
||||
assign CS_ADAR_1V8_1 = STM32_CS_ADAR1;
|
||||
assign CS_ADAR_1V8_2 = STM32_CS_ADAR2;
|
||||
assign CS_ADAR_1V8_3 = STM32_CS_ADAR3;
|
||||
assign CS_ADAR_1V8_4 = STM32_CS_ADAR4;
|
||||
|
||||
assign MIX_TX_EN = DIG_1;
|
||||
assign MIX_RX_EN = DIG_2;
|
||||
|
||||
always @(*) begin
|
||||
if (DIG_0) begin
|
||||
ADAR_TR1 = 1;
|
||||
ADAR_TR2 = 1;
|
||||
ADAR_TR3 = 1;
|
||||
ADAR_TR4 = 1;
|
||||
M3S_VCTRL = 0;
|
||||
end else begin
|
||||
ADAR_TR1 = 0;
|
||||
ADAR_TR2 = 0;
|
||||
ADAR_TR3 = 0;
|
||||
ADAR_TR4 = 0;
|
||||
M3S_VCTRL = 1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,66 @@
|
||||
module waveform_generator (
|
||||
input wire CLK_IN, // 100MHz input clock
|
||||
output reg DAC_CLOCK, // 120MHz clock to DAC
|
||||
output reg DAC_SLEEP, // DAC sleep control (0 = normal operation)
|
||||
output reg [7:0] DAC_DATA // 8-bit output to DAC
|
||||
);
|
||||
|
||||
// Clock divider for generating 120MHz DAC clock from 100MHz input
|
||||
reg [2:0] clk_div = 0;
|
||||
always @(posedge CLK_IN) begin
|
||||
clk_div <= clk_div + 1;
|
||||
if (clk_div == 2) begin
|
||||
DAC_CLOCK <= ~DAC_CLOCK;
|
||||
clk_div <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
// Look-Up Table (LUT) to store precomputed waveform samples
|
||||
parameter integer n = 31; // Number of samples per ramp (Tb/Ts)
|
||||
reg [7:0] waveform_LUT [0:n-1];
|
||||
|
||||
initial begin
|
||||
// Precomputed LUT values based on Python script
|
||||
waveform_LUT[0] = 8'h80;
|
||||
waveform_LUT[1] = 8'h89;
|
||||
waveform_LUT[2] = 8'h99;
|
||||
waveform_LUT[3] = 8'hAE;
|
||||
waveform_LUT[4] = 8'hC7;
|
||||
waveform_LUT[5] = 8'hE1;
|
||||
waveform_LUT[6] = 8'hF6;
|
||||
waveform_LUT[7] = 8'hFF;
|
||||
waveform_LUT[8] = 8'hF4;
|
||||
waveform_LUT[9] = 8'hCF;
|
||||
waveform_LUT[10] = 8'h92;
|
||||
waveform_LUT[11] = 8'h4B;
|
||||
waveform_LUT[12] = 8'h11;
|
||||
waveform_LUT[13] = 8'h02;
|
||||
waveform_LUT[14] = 8'h2E;
|
||||
waveform_LUT[15] = 8'h8A;
|
||||
waveform_LUT[16] = 8'hE4;
|
||||
waveform_LUT[17] = 8'hFC;
|
||||
waveform_LUT[18] = 8'hB6;
|
||||
waveform_LUT[19] = 8'h3F;
|
||||
waveform_LUT[20] = 8'h00;
|
||||
waveform_LUT[21] = 8'h41;
|
||||
waveform_LUT[22] = 8'hC8;
|
||||
waveform_LUT[23] = 8'hFC;
|
||||
waveform_LUT[24] = 8'h91;
|
||||
waveform_LUT[25] = 8'h0C;
|
||||
waveform_LUT[26] = 8'h2E;
|
||||
waveform_LUT[27] = 8'hD0;
|
||||
waveform_LUT[28] = 8'hED;
|
||||
waveform_LUT[29] = 8'h4A;
|
||||
waveform_LUT[30] = 8'h09;
|
||||
DAC_SLEEP = 0; // Enable DAC operation
|
||||
end
|
||||
|
||||
// Counter to step through the LUT
|
||||
reg [9:0] index = 0;
|
||||
always @(posedge DAC_CLOCK) begin
|
||||
DAC_DATA <= waveform_LUT[index];
|
||||
index <= index + 1;
|
||||
if (index >= n) index <= 0; // Repeat the waveform
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user