NawfalMotii79
138 lines
1.9 KiB
Verilog
138 lines
1.9 KiB
Verilog
`timescale 1ns / 1ps
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module ft2232h_245_sync(input clk,//input 50_MHz
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input reset,
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input [7:0] DAC_DATA,
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input [7:0] AD_Bus,
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output reg oe,
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output reg rd,
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input txe,
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output reg wr,
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input clkout_ft2232);
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//output reg oe);
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//wire CLK_OUT_PLL; //Output from PLL_IP_clock
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reg txe_n;
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reg wr_n;
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reg oe_n = 1'b1;
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reg rd_n = 1'b1;
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reg Flag_tx = 0;
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reg data_en_1 = 0;
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reg data_en_2 = 0;
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reg [7:0] data_o = 8'b00000000;
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parameter TX_RX_0 = 3'b000;
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parameter TX_1 = 3'b001;
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parameter TX_2 = 3'b010;
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parameter TX_3 = 3'b011;
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reg [3:0] state;
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reg [3:0] state_data;
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reg counter = 1'b0;
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begin
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assign AD_Bus = (data_en_1 == 1'b1) ? DAC_DATA : 8'bz;
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always @ (posedge clkout_ft2232)
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begin
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if ((txe_n == 0) && Flag_tx)
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begin
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data_en_1 = 1'b1;
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end
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end
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always @ (posedge clk)
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begin
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wr = wr_n;
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txe_n = txe;
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oe = oe_n;
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rd = rd_n;
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end
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always @ (posedge clk)
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if (reset)
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begin
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state = TX_RX_0;
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state_data = 0;
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counter = 1'b0;
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wr_n = 1'b1;
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end
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else
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begin
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case(state)
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TX_RX_0: begin
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if (txe_n == 0)
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begin
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state = TX_1;
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end
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else
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begin
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state = TX_RX_0;
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wr_n = 1'b1;
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end
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end
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TX_1 : begin
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if(txe_n == 0)
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begin
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counter = counter + 1;
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if(counter == 1'b1)
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begin
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counter = 1'b0;
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state = TX_2;
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end
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end
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else
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begin
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wr_n = 1'b1;
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state = TX_RX_0;
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end
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end
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TX_2 : begin
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wr_n = 1'b0;
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counter = counter + 1;
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if(counter == 1'b1)
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begin
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counter = 1'b0;
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state = TX_3;
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end
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end
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TX_3 : begin
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if(txe_n == 0)
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begin
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Flag_tx = 1'b1;
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state = TX_3;
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end
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else
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begin
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state = TX_RX_0;
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wr_n = 1'b1;
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Flag_tx = 1'b0;
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end
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end
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endcase
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end
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end
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endmodule
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