NawfalMotii79
40 lines
1.3 KiB
Verilog
40 lines
1.3 KiB
Verilog
module adc_interface (
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input wire CLK_IN, // 100 MHz clock input
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input wire rst, // Reset signal
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output wire ADC_CLK, // 60 MHz clock output to ADC
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output reg ADC_OE, // Output enable (0 = enable)
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output reg ADC_PD, // Power down (0 = normal operation)
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input wire [9:0] ADC_DATA, // 10-bit parallel ADC data input
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output reg [9:0] sampled_data // Captured ADC data
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);
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// Clocking Wizard or PLL/MMCM should be instantiated here to generate 60MHz ADC_CLK
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wire clk_60MHz;
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// Instantiate clock generator (example with MMCM/PLL instantiation needed)
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clk_wiz_0 clk_gen (
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.clk_in1(CLK_IN),
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.clk_out1(clk_60MHz), // 60 MHz clock output
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.reset(1'b0),
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.locked()
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);
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assign ADC_CLK = clk_60MHz;
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// ADC control signals initialization
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always @(posedge CLK_IN or posedge rst) begin
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if (rst) begin
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ADC_OE <= 1'b1; // Default disabled
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ADC_PD <= 1'b1; // Default power down
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end else begin
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ADC_OE <= 1'b0; // Enable ADC
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ADC_PD <= 1'b0; // Normal operation
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end
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end
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// Capture ADC data on ADC_CLK rising edge
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always @(posedge clk_60MHz) begin
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sampled_data <= ADC_DATA;
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end
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endmodule |