Jason
131 lines
8.0 KiB
HTML
131 lines
8.0 KiB
HTML
<!doctype html>
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<html lang="en">
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<head>
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<meta charset="utf-8">
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<meta name="viewport" content="width=device-width, initial-scale=1">
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<title>AERIS-10 Docs | Reports</title>
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<link rel="stylesheet" href="assets/style.css">
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</head>
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<body>
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<header class="topbar">
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<div class="container nav">
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<a class="brand" href="index.html">AERIS-10 Docs</a>
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<nav>
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<a href="architecture.html">Architecture</a>
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<a href="implementation-log.html">Implementation Log</a>
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<a href="bring-up.html">Bring-Up</a>
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<a href="reports.html">Reports</a>
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<a href="release-notes.html">Release Notes</a>
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</nav>
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</div>
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</header>
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<main class="container page">
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<section class="hero">
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<p class="eyebrow">Artifacts</p>
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<h1>Published Reports and Visuals</h1>
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<p>Central access point for antenna simulations, implementation summaries, timing baselines, and board-day artifact references.</p>
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<div class="cta-row">
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<a class="button" href="board-day-worksheet.html">Open Board-Day Worksheet</a>
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<a class="button ghost" href="bring-up.html">Open Bring-Up Plan</a>
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</div>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Current FPGA implementation status</h2>
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<ul>
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<li>Build 15 is the current detailed analysis baseline for the production XC7A200T target and completed with all timing constraints met.</li>
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<li>Build 16 was validated in the remote Vivado workspace as a constraint-cleanup pass: XDCB-5 warnings were removed, the large TIMING-18 bucket collapsed to a single <code>ft601_txe</code> methodology residue, and routed timing remained clean at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.</li>
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<li>The remaining <code>ft601_txe</code> methodology item currently behaves like an async-status-observation residue rather than a proven unconstrained functional FT601 path.</li>
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</ul>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Board-day artifact inventory</h2>
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<div class="table-wrap">
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<table>
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<thead>
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<tr>
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<th>Artifact</th>
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<th>Source path</th>
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<th>Day-0 use</th>
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<th>Status / note</th>
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</tr>
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</thead>
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<tbody>
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<tr><td>Production-target XDC</td><td><code>9_Firmware/9_2_FPGA/constraints/xc7a200t_fbg484.xdc</code></td><td>Constraint source of truth for the production FPGA target</td><td>Tracked and validated after Build 16 cleanup port</td></tr>
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<tr><td>FPGA programming flow</td><td><code>9_Firmware/9_2_FPGA/scripts/program_fpga.tcl</code></td><td>Programs the device and reports DONE / INIT_COMPLETE / probes presence</td><td>Primary operator-facing programming script</td></tr>
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<tr><td>Debug probe insertion flow</td><td><code>9_Firmware/9_2_FPGA/scripts/insert_ila_probes.tcl</code></td><td>Used when generating or refreshing debug-capable images</td><td>Keep matched with the selected debug bitstream</td></tr>
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<tr><td>FPGA regression runner</td><td><code>9_Firmware/9_2_FPGA/run_regression.sh</code></td><td>Pre-arrival regression evidence for the tracked FPGA baseline</td><td>18 / 18 passing on the current tracked branch</td></tr>
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<tr><td>MCU regression harness</td><td><code>9_Firmware/9_1_Microcontroller/tests/Makefile</code></td><td>Pre-arrival firmware regression evidence before flashing hardware</td><td>15 / 15 passing on the current tracked branch</td></tr>
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<tr><td>Bring-up logging macros</td><td><code>9_Firmware/9_1_Microcontroller/9_1_1_C_Cpp_Libraries/diag_log.h</code></td><td>Defines the main first-power-on log vocabulary used over USART3</td><td>Observation-only instrumentation layer</td></tr>
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<tr><td>Board-day worksheet</td><td><code>docs/board-day-worksheet.html</code></td><td>Record pass/fail, measurements, and blockers during first sessions</td><td>Use with this page and the bring-up plan</td></tr>
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<tr><td>Bring-up execution plan</td><td><code>docs/bring-up.html</code></td><td>Operator checklist, abort criteria, observability targets, and open risks</td><td>Primary readiness document</td></tr>
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</tbody>
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</table>
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</div>
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</section>
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<section class="grid-2" style="margin-top:0.8rem;">
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<article class="card">
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<h2>Antenna Simulation Report</h2>
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<p><span class="chip">Status: Mostly current (historical Phase-0 context)</span></p>
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<p class="muted">File: <code>AERIS_Antenna_Report.pdf</code></p>
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<p class="muted">Notes: Valid for 10.5 GHz patch-element simulation and array projection context. Treat as element-level evidence, not full current hardware bring-up sign-off.</p>
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<p>
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<a class="button" href="AERIS_Antenna_Report.pdf" target="_blank" rel="noopener">Open PDF</a>
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<a class="button ghost" href="AERIS_Antenna_Report.pdf" download>Download</a>
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</p>
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</article>
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<article class="card">
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<h2>Python Simulation Report</h2>
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<p><span class="chip">Status: Legacy (needs refresh)</span></p>
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<p class="muted">File: <code>AERIS_Simulation_Report.pdf</code></p>
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<p class="muted">Notes: Contains older architecture assumptions (e.g., XC7A100T-centric narrative). Use as historical reference only until Simulation Report v2 is published.</p>
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<p>
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<a class="button" href="AERIS_Simulation_Report.pdf" target="_blank" rel="noopener">Open PDF</a>
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<a class="button ghost" href="AERIS_Simulation_Report.pdf" download>Download</a>
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</p>
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</article>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>FPGA implementation analysis</h2>
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<p><span class="chip">Status: Current engineering baseline</span></p>
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<p class="muted">Primary detailed write-up: internal Build 15 implementation analysis captured timing, power, route status, DRC, methodology, CDC, and utilization for the production-target design after USB range wiring and CFAR cleanup.</p>
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<p class="muted">Follow-on Build 16 remote validation focused on production XDC cleanup only and confirmed no timing regression while reducing methodology noise substantially.</p>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Latest Simulation Report (Recommended)</h2>
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<p><span class="chip">Status: Current baseline (v2)</span></p>
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<p class="muted">File: <code>AERIS_Simulation_Report_v2.pdf</code></p>
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<p class="muted">Aligned to the active project baseline: XC7A200T target, firmware regression closure, FPGA regression/timing gates, USB range-profile integration, and TE0712/TE0713 split-target flow.</p>
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<p>
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<a class="button" href="AERIS_Simulation_Report_v2.pdf" target="_blank" rel="noopener">Open PDF</a>
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<a class="button ghost" href="AERIS_Simulation_Report_v2.pdf" download>Download</a>
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</p>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Report Currency Notice</h2>
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<ul>
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<li>The current routed production-target baseline is Build 15, with Build 16 used as a remote-only XDC cleanup validation pass.</li>
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<li>The latest public simulation PDF should be interpreted alongside the implementation log and release notes for the most accurate state of firmware bug closure and FPGA integration readiness.</li>
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<li>Detailed Build 15 and Build 16 engineering notes currently live in internal working reports and remote Vivado artifacts rather than this public docs directory.</li>
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<li>The artifact inventory above is intended to stabilize day-0 execution even when the detailed internal engineering reports stay outside the public docs site.</li>
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</ul>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Antenna concept snapshot</h2>
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<img class="diagram" src="assets/img/Antenna_Array.jpg" alt="Antenna array concept">
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</section>
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</main>
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<footer class="footer">
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<div class="container"><p>Add future report artifacts here to keep public references stable.</p></div>
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</footer>
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</body>
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</html>
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