Jason
96 lines
3.4 KiB
HTML
96 lines
3.4 KiB
HTML
<!doctype html>
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<html lang="en">
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<head>
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<meta charset="utf-8">
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<meta name="viewport" content="width=device-width, initial-scale=1">
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<title>AERIS-10 Docs | Architecture</title>
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<link rel="stylesheet" href="assets/style.css">
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</head>
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<body>
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<header class="topbar">
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<div class="container nav">
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<a class="brand" href="index.html">AERIS-10 Docs</a>
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<nav>
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<a href="architecture.html">Architecture</a>
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<a href="implementation-log.html">Implementation Log</a>
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<a href="bring-up.html">Bring-Up</a>
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<a href="reports.html">Reports</a>
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<a href="release-notes.html">Release Notes</a>
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</nav>
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</div>
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</header>
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<main class="container page">
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<section class="hero">
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<p class="eyebrow">System View</p>
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<h1>Architecture and Data Path</h1>
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<p>Hardware and firmware structure for the current XC7A200T implementation and bring-up targets.</p>
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</section>
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<section class="grid-2">
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<article class="card">
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<h2>Top-level processing flow</h2>
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<div class="table-wrap">
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<table>
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<thead>
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<tr>
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<th>Stage</th>
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<th>Module Focus</th>
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<th>Notes</th>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td>ADC capture</td>
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<td>AD9484 interface + CDC edge</td>
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<td>400 MHz sampling domain, synchronized into processing pipeline.</td>
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</tr>
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<tr>
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<td>DDC</td>
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<td>NCO + CIC + FIR</td>
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<td>I/Q conversion and decimation for baseband-ready stream.</td>
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</tr>
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<tr>
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<td>Matched filter</td>
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<td>FFT-based chain</td>
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<td>Synthesis branch is golden for hardware-equivalent co-sim.</td>
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</tr>
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<tr>
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<td>Range/Doppler</td>
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<td>Range bin decimator + Doppler FFT</td>
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<td>32 chirps/frame, 64 range bins, deterministic frame outputs.</td>
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</tr>
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<tr>
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<td>Host path</td>
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<td>FT601 interface</td>
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<td>USB streaming with framing and soak validation in bring-up.</td>
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</tr>
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</tbody>
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</table>
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</div>
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</article>
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<article class="card">
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<h2>Current target split strategy</h2>
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<ul>
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<li>Production target remains <code>xc7a200t-2fbg484i</code> with full board constraints.</li>
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<li>TE0712/TE0701 and TE0713/TE0701 use dedicated top wrappers and dedicated XDC files.</li>
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<li>Board-specific pinouts are isolated from core DSP modules to avoid accidental cross-target regression.</li>
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<li>Bring-up sequence starts from minimal heartbeat top, then steps into full signal chain validation.</li>
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</ul>
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</article>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Reference block diagram</h2>
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<img class="diagram" src="assets/img/RADAR_V6.jpg" alt="AERIS-10 system architecture diagram">
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<p class="muted">Diagram snapshot from AERIS-10 project architecture.</p>
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</section>
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</main>
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<footer class="footer">
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<div class="container"><p>Architecture is updated as bring-up and integration milestones complete.</p></div>
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</footer>
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</body>
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</html>
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