Jason
87 lines
4.6 KiB
HTML
87 lines
4.6 KiB
HTML
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<title>AERIS-10 Docs | Implementation Log</title>
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<body>
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<a class="brand" href="index.html">AERIS-10 Docs</a>
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<a href="architecture.html">Architecture</a>
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<a href="implementation-log.html">Implementation Log</a>
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<a href="bring-up.html">Bring-Up</a>
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<a href="reports.html">Reports</a>
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<a href="release-notes.html">Release Notes</a>
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<main class="container page">
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<section class="hero">
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<p class="eyebrow">Engineering Journal</p>
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<h1>Implementation Timeline and Improvements</h1>
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<p>Consolidated record of key firmware, timing, debug and infrastructure changes.</p>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Recent milestone timeline</h2>
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<div class="timeline">
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<article>
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<h3>Build 16 XDC cleanup validated on production target</h3>
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<p class="muted">Remote production XDC pass eliminated XDCB-5 warnings, collapsed the large TIMING-18 bucket to a single ft601_txe residue, and preserved timing at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.</p>
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</article>
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<article>
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<h3>Build 15 timing-clean integration baseline established</h3>
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<p class="muted">Production-target implementation completed with all timing constraints met after USB range-profile wiring and the CFAR sequential-assignment fix.</p>
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</article>
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<article>
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<h3>USB range profile path wired to matched-filter output</h3>
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<p class="muted">The top-level Doppler placeholder was removed from the USB range-profile path and replaced with the real matched-filter range output propagated through the receiver chain.</p>
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</article>
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<article>
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<h3>Firmware bug sweep closed with regression coverage</h3>
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<p class="muted">All 17 audited MCU firmware bugs were fixed, regression-tested, and pushed, including LO init ordering, SPI chip-select handling, PA calibration logic, TIM3 PWM bring-up, and stale diagnostic mismatches.</p>
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</article>
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<article>
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<h3>FPGA timing/resource cleanup phase completed</h3>
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<p class="muted">Chirp BRAM migration, Doppler DSP48 pipelining, CIC pipeline staging, matched-filter regression repair, and full FPGA regression brought the active baseline to 18/18 passing tests.</p>
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</article>
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<article>
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<h3>Build 13 frozen as earlier hardware candidate</h3>
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<p class="muted">Historical milestone retained for traceability: WNS +0.311 ns, TNS 0.000, WHS +0.060, THS 0.000 on the production target before the later DSP and integration work.</p>
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</article>
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</div>
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</section>
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<section class="grid-2" style="margin-top:0.8rem;">
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<article class="card">
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<h2>Codebase quality and verification upgrades</h2>
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<ul>
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<li>Added comprehensive DIAG instrumentation across MCU bring-up, LO, PA, USB, and safety paths before executing the bug-fix phase.</li>
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<li>Built an STM32 HAL/mock regression harness and closed the audited firmware bug list with MCU regression passing.</li>
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<li>Ran full FPGA regression with 18/18 passing suites, including matched filter, Doppler, CIC, CDC, USB, and system-top coverage.</li>
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<li>Migrated the chirp LUT path toward BRAM, added DSP48 and CIC pipeline staging, and validated that the active FPGA baseline still meets timing.</li>
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</ul>
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</article>
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<article class="card">
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<h2>Debug and infrastructure improvements</h2>
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<ul>
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<li>Completed Build 15 production-target analysis with timing, power, route, DRC, methodology, and CDC evidence captured in the internal engineering reports.</li>
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<li>Validated a remote-only Build 16 XDC cleanup pass that removed XDCB-5, reduced TIMING-18 to a single ft601_txe methodology residue, and preserved post-route timing.</li>
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<li>Kept separate Trenz development targets while prioritizing the in-stock TE0713 path for practical hardware execution.</li>
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<li>Preserved remote Vivado baselines so timing-clean builds can be compared before and after constraint-only experiments.</li>
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</ul>
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</article>
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</section>
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</main>
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<footer class="footer">
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<div class="container"><p>Update this page at each major commit or bring-up gate.</p></div>
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