Jason
82 lines
3.3 KiB
HTML
82 lines
3.3 KiB
HTML
<!doctype html>
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<html lang="en">
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<head>
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<meta charset="utf-8">
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<meta name="viewport" content="width=device-width, initial-scale=1">
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<title>AERIS-10 Docs | Bring-Up</title>
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<link rel="stylesheet" href="assets/style.css">
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</head>
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<body>
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<header class="topbar">
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<div class="container nav">
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<a class="brand" href="index.html">AERIS-10 Docs</a>
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<nav>
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<a href="architecture.html">Architecture</a>
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<a href="implementation-log.html">Implementation Log</a>
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<a href="bring-up.html">Bring-Up</a>
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<a href="reports.html">Reports</a>
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<a href="release-notes.html">Release Notes</a>
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</nav>
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</div>
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</header>
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<main class="container page">
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<section class="hero">
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<p class="eyebrow">Execution Checklist</p>
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<h1>Hardware Bring-Up Plan</h1>
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<p>Operational sequence and pass/fail gates for Day-1 and post-Day-1 validation.</p>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Bring-up gates</h2>
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<div class="table-wrap">
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<table>
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<thead>
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<tr>
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<th>Step</th>
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<th>Objective</th>
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<th>Pass Criteria</th>
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</tr>
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</thead>
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<tbody>
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<tr><td>1</td><td>Program baseline bitstream</td><td>JTAG detect + successful configuration</td></tr>
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<tr><td>2</td><td>Clock/reset sanity</td><td>Stable clocks and deterministic reset release</td></tr>
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<tr><td>3</td><td>ADC front-end</td><td>Valid raw data visible in ILA on expected clock</td></tr>
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<tr><td>4</td><td>DDC verification</td><td>Expected valid strobe and non-zero I/Q outputs</td></tr>
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<tr><td>5</td><td>Matched filter stage</td><td>Range profile valid asserted and segment flow correct</td></tr>
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<tr><td>6</td><td>Range/Doppler pipeline</td><td>Deterministic frame outputs with full bin coverage</td></tr>
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<tr><td>7</td><td>USB host link</td><td>Sustained transfer and stable framing over soak window</td></tr>
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<tr><td>8</td><td>Thermal/power screen</td><td>No rail anomalies or thermal runaway under load</td></tr>
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</tbody>
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</table>
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</div>
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</section>
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<section class="grid-2" style="margin-top:0.8rem;">
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<article class="card">
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<h2>Day-1 quick sequence</h2>
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<ol>
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<li>Mount SoM on carrier and verify supply/jumper defaults.</li>
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<li>Program minimal heartbeat top for immediate hardware liveness check.</li>
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<li>Program debug bitstream and attach LTX for ILA sessions.</li>
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<li>Capture first ADC and DDC traces, compare with expected signatures.</li>
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</ol>
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</article>
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<article class="card">
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<h2>Risk controls</h2>
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<ul>
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<li>Keep production target untouched; use split dev targets for carrier-specific pinouts.</li>
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<li>Do not rely on RTL hierarchical net names in post-synth debug scripts.</li>
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<li>Run timing/CDC/exceptions checks after every target migration update.</li>
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<li>Use a repeatable program-capture checklist to detect intermittent reset/clock issues.</li>
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</ul>
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</article>
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</section>
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</main>
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<footer class="footer">
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<div class="container"><p>This checklist is the operational source of truth for hardware execution.</p></div>
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</footer>
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</body>
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</html>
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