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<p class="eyebrow">Traceability</p>
<h1>Release Notes by Key Commit</h1>
<p>Milestone notes keyed to major bring-up, debug, and documentation commits.</p>
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<h2>Commit timeline</h2>
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<th>Commit</th>
<th>Title</th>
<th>Impact</th>
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<td><code>2763b4b</code></td>
<td>CFAR sequential fix and Build 15 analysis capture</td>
<td>Replaced the clocked-block CFAR blocking assignment with sequential logic and published the Build 15 timing/DRC/methodology analysis baseline.</td>
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<td><code>3fa26c9</code></td>
<td>USB range profile wiring completed</td>
<td>Removed the Doppler placeholder from the USB range path and propagated real matched-filter range data through the receiver/top-level interfaces.</td>
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<td><code>f4ff271</code></td>
<td>Matched-filter regression repair</td>
<td>Corrected golden-case <code>$readmemh</code> paths so the matched-filter regression returned to 40/40 passing.</td>
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<td><code>463ebef</code></td>
<td>CIC pipeline staging and regression runner</td>
<td>Added CIC comb pipeline staging, simulation guards, and an FPGA regression runner to preserve timing while tightening verification.</td>
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<td><code>c466021</code></td>
<td>Firmware bug sweep closure (B12-B17)</td>
<td>Closed the PA calibration, ADC buffer, DIAG macro, TIM3 PWM, and stale-diagnostic issues with additional MCU regression coverage.</td>
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<td><code>49c9aa2</code></td>
<td>SPI platform fix plus FPGA B2/B3 timing work</td>
<td>Fixed the legacy platform SPI transmit-only path and landed chirp BRAM migration plus Doppler DSP48 pipelining work.</td>
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<td><code>3b32f67</code></td>
<td>ADF4382A SPI and chip-select correctness</td>
<td>Fixed platform SPI ops wiring, added software-managed CS behavior, and widened SPI chip-select storage to handle STM32 pin values correctly.</td>
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<td><code>3979693</code></td>
<td>Initial 8-firmware-bug closure with tests</td>
<td>Closed the LO init ordering, AD9523 sequencing, sync trigger, temperature timer, GPIO mapping, and related MCU issues with regression coverage.</td>
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<h2>Uncommitted validated work</h2>
<ul>
<li>Build 16 remote production-XDC cleanup has been validated in the remote Vivado workspace but is not yet represented by a git commit.</li>
<li>The remote-only pass removed XDCB-5 warnings, reduced the large TIMING-18 bucket to a single <code>ft601_txe</code> methodology residue, and preserved timing at WNS +0.058 ns, WHS +0.068 ns, WPWS +0.684 ns.</li>
<li>The surviving <code>ft601_txe</code> item currently behaves like a methodology residue on an async status-observation path rather than a proven unconstrained functional FT601 interface.</li>
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<h2>Open in GitHub</h2>
<ul>
<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/2763b4b" target="_blank" rel="noopener">2763b4b</a></li>
<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3fa26c9" target="_blank" rel="noopener">3fa26c9</a></li>
<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/f4ff271" target="_blank" rel="noopener">f4ff271</a></li>
<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/463ebef" target="_blank" rel="noopener">463ebef</a></li>
<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/c466021" target="_blank" rel="noopener">c466021</a></li>
<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/49c9aa2" target="_blank" rel="noopener">49c9aa2</a></li>
<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3b32f67" target="_blank" rel="noopener">3b32f67</a></li>
<li><a href="https://github.com/JJassonn69/PLFM_RADAR/commit/3979693" target="_blank" rel="noopener">3979693</a></li>
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