Jason
d2f20f5c15
- release-notes.html: Add commits for Gaps 3-5-7-4, tagged releases table, architectural gap status table, updated GitHub links - implementation-log.html: Add Build 20/19/18 timeline entries, Gap 3-4-5 milestones, updated quality/build history sections - reports.html: Update FPGA status to Build 20 baseline, MCU regression to 20/20, report currency notice with current gap status
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5.6 KiB
HTML
97 lines
5.6 KiB
HTML
<!doctype html>
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<html lang="en">
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<head>
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<meta charset="utf-8">
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<meta name="viewport" content="width=device-width, initial-scale=1">
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<title>AERIS-10 Docs | Implementation Log</title>
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<link rel="stylesheet" href="assets/style.css">
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</head>
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<body>
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<header class="topbar">
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<div class="container nav">
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<a class="brand" href="index.html">AERIS-10 Docs</a>
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<nav>
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<a href="architecture.html">Architecture</a>
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<a href="implementation-log.html">Implementation Log</a>
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<a href="bring-up.html">Bring-Up</a>
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<a href="reports.html">Reports</a>
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<a href="release-notes.html">Release Notes</a>
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</header>
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<main class="container page">
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<section class="hero">
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<p class="eyebrow">Engineering Journal</p>
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<h1>Implementation Timeline and Improvements</h1>
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<p>Consolidated record of key firmware, timing, debug and infrastructure changes.</p>
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</section>
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<section class="card" style="margin-top:0.8rem;">
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<h2>Recent milestone timeline</h2>
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<div class="timeline">
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<article>
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<h3>Gap 4: USB Read Path wired with toggle CDC (e5d1b3c)</h3>
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<p class="muted">FT601 read FSM cmd_* outputs connected through toggle CDC to clk_100m command decode registers in radar_system_top.v. Host can now set radar mode, trigger chirps, set CFAR threshold, and control data streaming via USB. 3 new testbench groups (55 total checks). 18/18 FPGA regression.</p>
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</article>
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<article>
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<h3>Build 20 tagged v0.1.3-build20 — new production baseline (c6103b3)</h3>
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<p class="muted">WNS improved 7x to +0.426 ns (from +0.062 ns in Build 18). Includes 400 MHz MMCM jitter cleaner, CIC comb DSP48E1 CREG pipeline, and XDC clock-name fix. All timing constraints met. 6,092 LUTs (4.5%), 9,024 FFs (3.4%), 16 BRAM (4.4%), 140 DSP48E1 (18.9%), 0.730 W.</p>
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</article>
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<article>
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<h3>Build 19 timing failure root-caused and fixed</h3>
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<p class="muted">Build 19 had WNS -0.011 ns due to conflicting XDC create_generated_clock preventing false-path application on CDC paths. Fixed by removing the conflicting constraint and using Vivado auto-generated clk_mmcm_out0.</p>
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</article>
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<article>
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<h3>Gap 3: Safety Architecture closed (f3bbf77)</h3>
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<p class="muted">Added IWDG watchdog configuration, Emergency_Stop PA rail cutoff, temperature max guard, periodic IDQ re-read, and emergency state ordering. 5 new MCU tests, 20/20 MCU regression pass.</p>
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</article>
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<article>
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<h3>Gap 5: BRAM async reset fixed (c87dce0)</h3>
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<p class="muted">Chirp memory loader BRAM async reset converted to synchronous reset pattern per Xilinx UG901 guidelines. Prevents BRAM inference failures on production target.</p>
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</article>
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<article>
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<h3>Build 18 tagged v0.1.2-build18 — prior production baseline</h3>
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<p class="muted">WNS +0.062 ns, WHS +0.059 ns. 6,088 LUTs, 8,946 FFs, 16 BRAM, 140 DSP48E1, 0.631 W. All timing met.</p>
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</article>
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<article>
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<h3>Firmware bug sweep closed with regression coverage</h3>
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<p class="muted">All 17 audited MCU firmware bugs were fixed, regression-tested, and pushed, including LO init ordering, SPI chip-select handling, PA calibration logic, TIM3 PWM bring-up, and stale diagnostic mismatches. 20/20 MCU tests pass.</p>
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</article>
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<article>
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<h3>FPGA timing/resource cleanup phase completed</h3>
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<p class="muted">Chirp BRAM migration, Doppler DSP48 pipelining, CIC pipeline staging, matched-filter regression repair, and full FPGA regression brought the active baseline to 18/18 passing tests.</p>
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</article>
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</div>
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</section>
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<section class="grid-2" style="margin-top:0.8rem;">
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<article class="card">
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<h2>Codebase quality and verification upgrades</h2>
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<ul>
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<li>FPGA regression: 18/18 passing suites covering matched filter, Doppler, CIC, CDC, USB (with read path), FFT, NCO, FIR, range decimator, mode controller, and system-top integration.</li>
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<li>MCU regression: 20/20 passing tests (15 bug-fix + 5 Gap-3 safety tests).</li>
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<li>Architectural gaps 3, 4, 5, 7 closed with full test coverage. Gaps 1, 2, 6 deferred to post-bring-up or pre-tuning.</li>
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<li>USB host-to-FPGA command path fully wired: read FSM, toggle CDC, command decode for mode/trigger/CFAR/stream control.</li>
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<li>Safety architecture: IWDG watchdog, emergency stop PA cutoff, temperature guard, IDQ re-read, state ordering.</li>
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</ul>
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</article>
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<article class="card">
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<h2>Build history and timing improvements</h2>
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<ul>
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<li><strong>Build 20 (v0.1.3-build20)</strong>: Current production baseline. WNS +0.426 ns, WHS +0.058 ns. 400 MHz MMCM + CIC CREG pipeline. 0.730 W.</li>
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<li><strong>Build 19</strong>: Failed (WNS -0.011 ns). Root cause: conflicting XDC generated clock prevented false-path application.</li>
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<li><strong>Build 18 (v0.1.2-build18)</strong>: Prior baseline. WNS +0.062 ns, WHS +0.059 ns. 0.631 W.</li>
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<li><strong>Build 17 (v0.1.1-build17)</strong>: FIR DSP48 pipelining + matched filter BRAM migration.</li>
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<li>Remote Vivado build infrastructure on Ubuntu 24.04 with Vivado 2025.2, targeting XC7A200T-2FBG484I.</li>
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</ul>
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</article>
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</section>
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</main>
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<footer class="footer">
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<div class="container"><p>Update this page at each major commit or bring-up gate.</p></div>
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