AERIS-10 Docs

Engineering Journal

Implementation Timeline and Improvements

Consolidated record of key firmware, timing, debug and infrastructure changes.

Recent milestone timeline

Gap 4: USB Read Path wired with toggle CDC (e5d1b3c)

FT601 read FSM cmd_* outputs connected through toggle CDC to clk_100m command decode registers in radar_system_top.v. Host can now set radar mode, trigger chirps, set CFAR threshold, and control data streaming via USB. 3 new testbench groups (55 total checks). 18/18 FPGA regression.

Build 20 tagged v0.1.3-build20 — new production baseline (c6103b3)

WNS improved 7x to +0.426 ns (from +0.062 ns in Build 18). Includes 400 MHz MMCM jitter cleaner, CIC comb DSP48E1 CREG pipeline, and XDC clock-name fix. All timing constraints met. 6,092 LUTs (4.5%), 9,024 FFs (3.4%), 16 BRAM (4.4%), 140 DSP48E1 (18.9%), 0.730 W.

Build 19 timing failure root-caused and fixed

Build 19 had WNS -0.011 ns due to conflicting XDC create_generated_clock preventing false-path application on CDC paths. Fixed by removing the conflicting constraint and using Vivado auto-generated clk_mmcm_out0.

Gap 3: Safety Architecture closed (f3bbf77)

Added IWDG watchdog configuration, Emergency_Stop PA rail cutoff, temperature max guard, periodic IDQ re-read, and emergency state ordering. 5 new MCU tests, 20/20 MCU regression pass.

Gap 5: BRAM async reset fixed (c87dce0)

Chirp memory loader BRAM async reset converted to synchronous reset pattern per Xilinx UG901 guidelines. Prevents BRAM inference failures on production target.

Build 18 tagged v0.1.2-build18 — prior production baseline

WNS +0.062 ns, WHS +0.059 ns. 6,088 LUTs, 8,946 FFs, 16 BRAM, 140 DSP48E1, 0.631 W. All timing met.

Firmware bug sweep closed with regression coverage

All 17 audited MCU firmware bugs were fixed, regression-tested, and pushed, including LO init ordering, SPI chip-select handling, PA calibration logic, TIM3 PWM bring-up, and stale diagnostic mismatches. 20/20 MCU tests pass.

FPGA timing/resource cleanup phase completed

Chirp BRAM migration, Doppler DSP48 pipelining, CIC pipeline staging, matched-filter regression repair, and full FPGA regression brought the active baseline to 18/18 passing tests.

Codebase quality and verification upgrades

  • FPGA regression: 18/18 passing suites covering matched filter, Doppler, CIC, CDC, USB (with read path), FFT, NCO, FIR, range decimator, mode controller, and system-top integration.
  • MCU regression: 20/20 passing tests (15 bug-fix + 5 Gap-3 safety tests).
  • Architectural gaps 3, 4, 5, 7 closed with full test coverage. Gaps 1, 2, 6 deferred to post-bring-up or pre-tuning.
  • USB host-to-FPGA command path fully wired: read FSM, toggle CDC, command decode for mode/trigger/CFAR/stream control.
  • Safety architecture: IWDG watchdog, emergency stop PA cutoff, temperature guard, IDQ re-read, state ordering.

Build history and timing improvements

  • Build 20 (v0.1.3-build20): Current production baseline. WNS +0.426 ns, WHS +0.058 ns. 400 MHz MMCM + CIC CREG pipeline. 0.730 W.
  • Build 19: Failed (WNS -0.011 ns). Root cause: conflicting XDC generated clock prevented false-path application.
  • Build 18 (v0.1.2-build18): Prior baseline. WNS +0.062 ns, WHS +0.059 ns. 0.631 W.
  • Build 17 (v0.1.1-build17): FIR DSP48 pipelining + matched filter BRAM migration.
  • Remote Vivado build infrastructure on Ubuntu 24.04 with Vivado 2025.2, targeting XC7A200T-2FBG484I.