Jason
558f49cd4a
Testbenches for: edge_detector (17), nco_400m (20), cic_decimator (14), fir_lowpass (13), freq_matched_filter (14), ddc_400m full-chain (7), chirp_controller (39), chirp_contract regression (20). Includes CSV output data for waveform verification. Add .gitignore to exclude VCD/VVP build artifacts.
11 lines
91 B
Plaintext
11 lines
91 B
Plaintext
# Verilog simulation artifacts
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*.vvp
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*.vcd
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# macOS
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.DS_Store
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# Python
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__pycache__/
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*.pyc
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