Jason
c871281f1e
Guard all $display/$error/$time calls with ifdef SIMULATION in: - chirp_memory_loader_param.v (initial + always block debug prints) - cic_decimator_4x_enhanced.v (5 saturation/overflow displays + monitor block) - ddc_400m.v (FIR/baseband debug monitor block) - fft_1024_inverse.v (IFFT config debug block) - matched_filter_multi_segment.v (16 state machine displays + monitor) - nco_400m_enhanced.v (initial block debug print) - radar_receiver_final.v (frame/chirp counter displays) Replace SystemVerilog constructs with Verilog-2001: - usb_data_interface.v (typedef enum -> localparam + reg) - usb_packet_analyzer.v (typedef enum -> localparam, output reg -> wire)
99 lines
2.7 KiB
Verilog
99 lines
2.7 KiB
Verilog
`timescale 1ns / 1ps
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module fft_1024_inverse_enhanced (
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input wire clk,
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input wire reset_n,
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input wire [15:0] data_i,
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input wire [15:0] data_q,
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input wire data_valid,
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output wire [15:0] ifft_i,
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output wire [15:0] ifft_q,
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output wire ifft_valid
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);
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// ========== MATCH YOUR FFT IP CONFIGURATION ==========
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wire [15:0] s_axis_config_tdata; // 16-bit
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wire s_axis_config_tvalid;
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wire s_axis_config_tready;
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wire [31:0] s_axis_data_tdata; // 32-bit for your IP {Q[15:0],I[15:0]}
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wire s_axis_data_tvalid;
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wire s_axis_data_tready;
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wire s_axis_data_tlast;
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wire [31:0] m_axis_data_tdata; // 32-bit
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wire m_axis_data_tvalid;
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wire m_axis_data_tready;
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wire m_axis_data_tlast;
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// Configuration: bit 0 = 0 for inverse FFT
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assign s_axis_config_tdata = 16'h0000;
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assign s_axis_config_tvalid = 1'b1;
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assign s_axis_data_tdata = {data_q, data_i};
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assign s_axis_data_tvalid = data_valid;
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// Frame counter
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reg [9:0] sample_count;
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reg frame_active;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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sample_count <= 0;
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frame_active <= 0;
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end else begin
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if (data_valid && !frame_active) begin
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frame_active <= 1'b1;
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sample_count <= 0;
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end
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if (frame_active && data_valid) begin
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if (sample_count == 1023) begin
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sample_count <= 0;
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frame_active <= 0;
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end else begin
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sample_count <= sample_count + 1;
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end
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end
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end
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end
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assign s_axis_data_tlast = (sample_count == 1023) && data_valid;
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// Output
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assign ifft_i = m_axis_data_tdata[15:0]; // I = lower 16 bits
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assign ifft_q = m_axis_data_tdata[31:16]; // Q = upper 16 bits
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assign ifft_valid = m_axis_data_tvalid;
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assign m_axis_data_tready = 1'b1;
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// Debug
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`ifdef SIMULATION
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reg [31:0] debug_counter;
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always @(posedge clk) begin
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debug_counter <= debug_counter + 1;
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if (debug_counter < 1000) begin
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if (s_axis_config_tvalid && s_axis_config_tready) begin
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$display("[IFFT_CORRECTED @%d] CONFIG ACCEPTED!", debug_counter);
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end
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end
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end
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`endif
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// IFFT IP instance
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FFT_enhanced ifft_inverse_inst ( // Same IP core, different configuration
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.aclk(clk),
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.aresetn(reset_n),
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.s_axis_config_tdata(s_axis_config_tdata),
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.s_axis_config_tvalid(s_axis_config_tvalid),
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.s_axis_config_tready(s_axis_config_tready),
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.s_axis_data_tdata(s_axis_data_tdata),
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.s_axis_data_tvalid(s_axis_data_tvalid),
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.s_axis_data_tready(s_axis_data_tready),
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.s_axis_data_tlast(s_axis_data_tlast),
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.m_axis_data_tdata(m_axis_data_tdata),
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.m_axis_data_tvalid(m_axis_data_tvalid),
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.m_axis_data_tlast(m_axis_data_tlast)
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);
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endmodule |