Jason 49eb6169b6 Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB ...

- Expand ft601_be from [1:0] to [3:0] across RTL, top-level, testbenches,
  and XDC (uncomment be[2:3] pin assignments B21/A21)
- Fix NCO XSim testbench: correct reset check (0x7FFF not 0), add pipeline
  warmup and sample skip for DSP48E1 quadrature test
- All local regression tests pass (39/39 USB, 10/10 integration, all co-sim)

2026-03-16 23:17:38 +02:00

..

constraints

Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB

2026-03-16 23:17:38 +02:00

tb

Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB

2026-03-16 23:17:38 +02:00

ad9484_interface_400m.v

Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I

2026-03-16 22:24:22 +02:00

cdc_modules.v

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

chirp_lut_init.v

Add files via upload

2026-03-09 00:17:39 +00:00

chirp_memory_loader_param.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

cic_decimator_4x_enhanced.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

cntrt.xdc

Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I

2026-03-16 22:24:22 +02:00

dac_interface_single.v

Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I

2026-03-16 22:24:22 +02:00

ddc_400m.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

ddc_input_interface.v

Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale

2026-03-16 18:14:06 +02:00

doppler_processor.v

Fix RTL Bug #3: S_IDLE->S_ACCUMULATE now writes first sample immediately

2026-03-16 19:08:16 +02:00

edge_detector.v

Add files via upload

2026-03-09 00:17:39 +00:00

fft_1024_forward.v

Add files via upload

2026-03-09 00:17:39 +00:00

fft_1024_inverse.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

fft_engine.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

fft_twiddle_32.mem

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

fft_twiddle_1024.mem

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

fir_lowpass.v

Fix P0/P1 RTL bugs found during pre-hardware audit

2026-03-16 22:24:06 +02:00

frequency_matched_filter.v

Add files via upload

2026-03-09 00:17:39 +00:00

latency_buffer_2159.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

level_shifter_interface.v

Add files via upload

2026-03-10 01:31:50 +00:00

long_chirp_seg0_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg0_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg1_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg1_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg2_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg2_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg3_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg3_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

lvds_to_cmos_400m.v

Add files via upload

2026-03-09 00:17:39 +00:00

matched_filter_multi_segment.v

Fix overlap-save: fill full 1024-sample buffer per segment, zero-pad last partial segment

2026-03-16 19:15:23 +02:00

matched_filter_processing_chain.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

nco_400m_enhanced.v

Fix P0/P1 RTL bugs found during pre-hardware audit

2026-03-16 22:24:06 +02:00

plfm_chirp_controller.v

Fix 6 RTL bugs in FPGA signal processing chain

2026-03-15 06:14:04 +02:00

radar_mode_controller.v

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

radar_receiver_final.v

Fix P0/P1 RTL bugs found during pre-hardware audit

2026-03-16 22:24:06 +02:00

radar_system_tb.v

Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB

2026-03-16 23:17:38 +02:00

radar_system_top.v

Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB

2026-03-16 23:17:38 +02:00

radar_transmitter.v

Add files via upload

2026-03-09 00:17:39 +00:00

range_bin_decimator.v

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

short_chirp_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

short_chirp_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

usb_data_interface.v

Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB

2026-03-16 23:17:38 +02:00

usb_packet_analyzer.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

xfft_32.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00