Jason 39f78d4349 Fix RTL Bug #3: S_IDLE->S_ACCUMULATE now writes first sample immediately ...

Previously the S_IDLE->S_ACCUMULATE transition consumed one data_valid
cycle without writing to BRAM, losing the first sample. The testbench
worked around this by sending sample[0] twice.

Fix: drive mem_we + data capture in S_IDLE on the transition cycle and
advance write_range_bin to 1. Testbench workaround removed.

Verified: 3/3 Doppler co-sim BIT-PERFECT, integration test 10/10 PASS.

2026-03-16 19:08:16 +02:00

..

cosim

Add .mem file validator: verify FFT twiddle + chirp .mem files against radar parameters (55/56 PASS)

2026-03-16 19:02:45 +02:00

ad9484_interface_400m_stub.v

Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS)

2026-03-16 18:51:08 +02:00

cic_dc_output.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

cic_impulse_output.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

cic_sine_passband.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

ddc_120mhz_output.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

fir_dc_output.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

fir_impulse_output.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

fir_sine_passband.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

gen_mf_golden_ref.py

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_out_i_case1.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_out_i_case2.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_out_i_case3.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_out_i_case4.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_out_q_case1.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_out_q_case2.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_out_q_case3.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_out_q_case4.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_ref_i_case1.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_ref_i_case2.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_ref_i_case3.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_ref_i_case4.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_ref_q_case1.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_ref_q_case2.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_ref_q_case3.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_ref_q_case4.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_sig_i_case1.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_sig_i_case2.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_sig_i_case3.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_sig_i_case4.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_sig_q_case1.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_sig_q_case2.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_sig_q_case3.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_sig_q_case4.hex

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_golden_summary.txt

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

mf_pipeline_output.csv

Add 8 Verilog testbenches with full coverage (144/144 pass)

2026-03-15 06:14:11 +02:00

nco_1mhz_output.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

nco_120mhz_output.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

nco_freq_switch.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

nco_quadrature.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

tb_chirp_contract.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

2026-03-15 06:14:11 +02:00

tb_chirp_controller.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

2026-03-15 06:14:11 +02:00

tb_cic_decimator.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

2026-03-15 06:14:11 +02:00

tb_ddc_400m.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

2026-03-15 06:14:11 +02:00

tb_ddc_cosim.v

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

tb_ddc_input_interface.v

Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale

2026-03-16 18:14:06 +02:00

tb_doppler_cosim.v

Fix RTL Bug #3: S_IDLE->S_ACCUMULATE now writes first sample immediately

2026-03-16 19:08:16 +02:00

tb_edge_detector.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

2026-03-15 06:14:11 +02:00

tb_fft_engine.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

tb_fir_lowpass.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

2026-03-15 06:14:11 +02:00

tb_freq_matched_filter.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

2026-03-15 06:14:11 +02:00

tb_matched_filter_processing_chain.v

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

tb_mf_chain_synth.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

tb_mf_cosim.v

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

tb_multiseg_cosim.v

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

tb_nco_400m.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

tb_radar_mode_controller.v

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

tb_radar_receiver_final.v

Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS)

2026-03-16 18:51:08 +02:00

tb_range_bin_decimator.v

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

tb_xfft_32.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00