Jason 39f78d4349 Fix RTL Bug #3: S_IDLE->S_ACCUMULATE now writes first sample immediately ...

Previously the S_IDLE->S_ACCUMULATE transition consumed one data_valid
cycle without writing to BRAM, losing the first sample. The testbench
worked around this by sending sample[0] twice.

Fix: drive mem_we + data capture in S_IDLE on the transition cycle and
advance write_range_bin to 1. Testbench workaround removed.

Verified: 3/3 Doppler co-sim BIT-PERFECT, integration test 10/10 PASS.

2026-03-16 19:08:16 +02:00

..

9_1_Microcontroller

Merge pull request #7 from walidb212/fix/gy85-i2c-status

2026-03-15 01:57:28 +00:00

9_2_FPGA

Fix RTL Bug #3: S_IDLE->S_ACCUMULATE now writes first sample immediately

2026-03-16 19:08:16 +02:00

9_3_GUI

fix(gui): validate radar settings before usb send

2026-03-13 19:28:35 +01:00