Jason
e93bc33c6c
Fix 1: Combinational magnitude + non-sticky detection flag (tb: 23/23) Fix 2: Rename all cfar_* signals to detect_*/threshold_* (honest naming) Fix 3: New rx_gain_control.v between DDC and FFT, opcode 0x16 (tb: 33/33) Fix 4: Clamp host_chirps_per_elev to DOPPLER_FFT_SIZE, error flag (E2E: 54/54) Fix 5: Decimator watchdog timeout, 256-cycle limit (tb: 63/63) Fix 6: Remove bypass_mode dead code from ddc_400m.v (DDC tb: 21/21) Fix 7: Range-mode register 0x20 with status readback (USB tb: 77/77)
723 lines
23 KiB
Verilog
723 lines
23 KiB
Verilog
`timescale 1ns / 1ps
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module ddc_400m_enhanced (
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input wire clk_400m, // 400MHz clock from ADC DCO
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input wire clk_100m, // 100MHz system clock
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input wire reset_n,
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input wire mixers_enable,
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input wire [7:0] adc_data, // ADC data at 400MHz
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input wire adc_data_valid_i, // Valid at 400MHz
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input wire adc_data_valid_q,
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output wire signed [17:0] baseband_i,
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output wire signed [17:0] baseband_q,
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output wire baseband_valid_i,
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output wire baseband_valid_q,
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output wire [1:0] ddc_status,
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// Enhanced interfaces
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output wire [7:0] ddc_diagnostics,
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output wire mixer_saturation,
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output wire filter_overflow,
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input wire [1:0] test_mode,
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input wire [15:0] test_phase_inc,
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input wire force_saturation,
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input wire reset_monitors,
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output wire [31:0] debug_sample_count,
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output wire [17:0] debug_internal_i,
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output wire [17:0] debug_internal_q
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);
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// Parameters for numerical precision
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parameter ADC_WIDTH = 8;
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parameter NCO_WIDTH = 16;
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parameter MIXER_WIDTH = 18;
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parameter OUTPUT_WIDTH = 18;
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// IF frequency parameters
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parameter IF_FREQ = 120000000;
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parameter FS = 400000000;
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parameter PHASE_WIDTH = 32;
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// Internal signals
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wire signed [15:0] sin_out, cos_out;
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wire nco_ready;
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wire cic_valid;
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wire fir_valid;
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wire [17:0] cic_i_out, cic_q_out;
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wire signed [17:0] fir_i_out, fir_q_out;
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// Diagnostic registers
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reg [2:0] saturation_count;
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reg overflow_detected;
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reg [7:0] error_counter;
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// ============================================================================
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// 400 MHz Reset Synchronizer
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//
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// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
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// Using it directly as an async reset in the 400 MHz domain causes the reset
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// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
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// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
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// domain, requiring 18.243ns of routing (WNS = -18.081ns).
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//
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// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
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// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
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// path from reset_n to all 400 MHz registers). Reset deassertion is
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// synchronized to clk_400m rising edge, preventing metastability.
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//
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// All 400 MHz submodules (NCO, CIC, mixers, LFSR) use reset_n_400m.
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// All 100 MHz submodules (FIR, output stage) continue using reset_n directly
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// (already synchronized to 100 MHz at radar_system_top level).
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// ============================================================================
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(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m;
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(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
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// Active-high reset for DSP48E1 RST ports (avoids LUT1 inverter fan-out)
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(* max_fanout = 50 *) reg reset_400m;
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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reset_sync_400m <= 2'b00;
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reset_400m <= 1'b1;
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end else begin
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reset_sync_400m <= {reset_sync_400m[0], 1'b1};
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reset_400m <= ~reset_sync_400m[1];
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end
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end
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// CDC synchronization for control signals (2-stage synchronizers)
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(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
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(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
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wire mixers_enable_sync;
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wire force_saturation_sync;
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// Debug monitoring signals
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reg [31:0] sample_counter;
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wire signed [17:0] debug_mixed_i_trunc;
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wire signed [17:0] debug_mixed_q_trunc;
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// Real-time status monitoring
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reg [7:0] signal_power_i, signal_power_q;
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// Internal mixing signals
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// DSP48E1 with AREG=1, BREG=1, MREG=1, PREG=1 handles all internal pipelining
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// Latency: 3 cycles (1 for AREG/BREG, 1 for MREG, 1 for PREG)
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wire signed [MIXER_WIDTH-1:0] adc_signed_w;
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reg signed [MIXER_WIDTH + NCO_WIDTH -1:0] mixed_i, mixed_q;
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reg mixed_valid;
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reg mixer_overflow_i, mixer_overflow_q;
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// Pipeline valid tracking: 3-stage shift register to match DSP48E1 AREG+MREG+PREG latency
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reg [2:0] dsp_valid_pipe;
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// Output stage registers
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reg signed [17:0] baseband_i_reg, baseband_q_reg;
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reg baseband_valid_reg;
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// ============================================================================
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// Phase Dithering Signals
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// ============================================================================
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wire [7:0] phase_dither_bits;
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reg [31:0] phase_inc_dithered;
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// ============================================================================
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// Debug Signal Assignments
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// ============================================================================
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assign debug_internal_i = mixed_i[25:8];
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assign debug_internal_q = mixed_q[25:8];
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assign debug_sample_count = sample_counter;
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assign debug_mixed_i_trunc = mixed_i[25:8];
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assign debug_mixed_q_trunc = mixed_q[25:8];
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// ============================================================================
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// Clock Domain Crossing for Control Signals (2-stage synchronizers)
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// ============================================================================
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assign mixers_enable_sync = mixers_enable_sync_chain[1];
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assign force_saturation_sync = force_saturation_sync_chain[1];
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always @(posedge clk_400m or negedge reset_n_400m) begin
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if (!reset_n_400m) begin
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mixers_enable_sync_chain <= 2'b00;
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force_saturation_sync_chain <= 2'b00;
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end else begin
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mixers_enable_sync_chain <= {mixers_enable_sync_chain[0], mixers_enable};
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force_saturation_sync_chain <= {force_saturation_sync_chain[0], force_saturation};
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end
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end
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// ============================================================================
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// Sample Counter and Debug Monitoring
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n_400m) begin
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if (!reset_n_400m || reset_monitors) begin
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sample_counter <= 0;
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error_counter <= 0;
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end else if (adc_data_valid_i && adc_data_valid_q ) begin
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sample_counter <= sample_counter + 1;
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end
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end
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// ============================================================================
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// Enhanced Phase Dithering Instance
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// ============================================================================
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lfsr_dither_enhanced #(
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.DITHER_WIDTH(8)
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) phase_dither_gen (
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.clk(clk_400m),
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.reset_n(reset_n_400m),
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.enable(nco_ready),
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.dither_out(phase_dither_bits)
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);
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// ============================================================================
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// Phase Increment Calculation with Dithering
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// ============================================================================
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// Calculate phase increment for 120MHz IF at 400MHz sampling
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localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
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// Apply dithering to reduce spurious tones (registered for 400 MHz timing)
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always @(posedge clk_400m or negedge reset_n_400m) begin
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if (!reset_n_400m)
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phase_inc_dithered <= PHASE_INC_120MHZ;
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else
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phase_inc_dithered <= PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
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end
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// ============================================================================
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// Enhanced NCO with Diagnostics
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// ============================================================================
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nco_400m_enhanced nco_core (
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.clk_400m(clk_400m),
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.reset_n(reset_n_400m),
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.frequency_tuning_word(phase_inc_dithered),
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.phase_valid(mixers_enable),
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.phase_offset(16'h0000),
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.sin_out(sin_out),
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.cos_out(cos_out),
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.dds_ready(nco_ready)
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);
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// ============================================================================
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// Enhanced Mixing Stage — DSP48E1 direct instantiation for 400 MHz timing
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//
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// Architecture:
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// ADC data → sign-extend to 18b → DSP48E1 A-port (AREG=1 pipelines it)
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// NCO cos/sin → sign-extend to 18b → DSP48E1 B-port (BREG=1 pipelines it)
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// Multiply result captured by MREG=1, then output registered by PREG=1
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// force_saturation override applied AFTER DSP48E1 output (not on input path)
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//
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// Latency: 3 clock cycles (AREG/BREG + MREG + PREG)
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// PREG=1 absorbs DSP48E1 CLK→P delay internally, preventing fabric timing violations
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// In simulation (Icarus), uses behavioral equivalent since DSP48E1 is Xilinx-only
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// ============================================================================
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// Combinational ADC sign conversion (no register — DSP48E1 AREG handles it)
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assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
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{1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
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// Valid pipeline: 3-stage shift register matching DSP48E1 AREG+MREG+PREG latency
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always @(posedge clk_400m or negedge reset_n_400m) begin
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if (!reset_n_400m) begin
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dsp_valid_pipe <= 3'b000;
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end else begin
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dsp_valid_pipe <= {dsp_valid_pipe[1:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
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end
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end
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`ifdef SIMULATION
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// ---- Behavioral model for Icarus Verilog simulation ----
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// Mimics DSP48E1 with AREG=1, BREG=1, MREG=1, PREG=1 (3-cycle latency)
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reg signed [MIXER_WIDTH-1:0] adc_signed_reg; // Models AREG
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reg signed [15:0] cos_pipe_reg, sin_pipe_reg; // Models BREG
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reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal; // Models MREG
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reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg; // Models PREG
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// Stage 1: AREG/BREG equivalent
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always @(posedge clk_400m or negedge reset_n_400m) begin
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if (!reset_n_400m) begin
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adc_signed_reg <= 0;
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cos_pipe_reg <= 0;
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sin_pipe_reg <= 0;
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end else begin
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adc_signed_reg <= adc_signed_w;
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cos_pipe_reg <= cos_out;
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sin_pipe_reg <= sin_out;
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end
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end
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// Stage 2: MREG equivalent
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always @(posedge clk_400m or negedge reset_n_400m) begin
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if (!reset_n_400m) begin
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mult_i_internal <= 0;
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mult_q_internal <= 0;
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end else begin
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mult_i_internal <= $signed(adc_signed_reg) * $signed(cos_pipe_reg);
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mult_q_internal <= $signed(adc_signed_reg) * $signed(sin_pipe_reg);
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end
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end
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// Stage 3: PREG equivalent
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always @(posedge clk_400m or negedge reset_n_400m) begin
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if (!reset_n_400m) begin
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mult_i_reg <= 0;
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mult_q_reg <= 0;
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end else begin
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mult_i_reg <= mult_i_internal;
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mult_q_reg <= mult_q_internal;
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end
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end
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`else
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// ---- Direct DSP48E1 instantiation for Vivado synthesis ----
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// This guarantees AREG/BREG/MREG are used, achieving timing closure at 400 MHz
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wire [47:0] dsp_p_i, dsp_p_q;
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// DSP48E1 for I-channel mixer (adc_signed * cos_out)
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DSP48E1 #(
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// Feature control attributes
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.A_INPUT("DIRECT"),
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.B_INPUT("DIRECT"),
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.USE_DPORT("FALSE"),
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.USE_MULT("MULTIPLY"),
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.USE_SIMD("ONE48"),
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// Pipeline register attributes — all enabled for max timing
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.AREG(1),
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.BREG(1),
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.MREG(1),
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.PREG(1), // P register enabled — absorbs CLK→P delay for timing closure
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.ADREG(0),
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.ACASCREG(1),
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.BCASCREG(1),
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.ALUMODEREG(0),
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.CARRYINREG(0),
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.CARRYINSELREG(0),
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.CREG(0),
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.DREG(0),
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.INMODEREG(0),
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.OPMODEREG(0),
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// Pattern detector (unused)
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.AUTORESET_PATDET("NO_RESET"),
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.MASK(48'h3fffffffffff),
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.PATTERN(48'h000000000000),
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.SEL_MASK("MASK"),
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.SEL_PATTERN("PATTERN"),
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.USE_PATTERN_DETECT("NO_PATDET")
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) dsp_mixer_i (
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// Clock and reset
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.CLK(clk_400m),
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.RSTA(reset_400m),
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.RSTB(reset_400m),
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.RSTM(reset_400m),
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.RSTP(reset_400m),
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.RSTALLCARRYIN(1'b0),
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.RSTALUMODE(1'b0),
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.RSTCTRL(1'b0),
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.RSTC(1'b0),
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.RSTD(1'b0),
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.RSTINMODE(1'b0),
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// Clock enables
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.CEA1(1'b0), // AREG=1 uses CEA2
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.CEA2(1'b1),
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.CEB1(1'b0), // BREG=1 uses CEB2
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.CEB2(1'b1),
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.CEM(1'b1),
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.CEP(1'b1), // P register clock enable (PREG=1)
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.CEAD(1'b0),
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.CEALUMODE(1'b0),
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.CECARRYIN(1'b0),
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.CECTRL(1'b0),
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.CEC(1'b0),
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.CED(1'b0),
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.CEINMODE(1'b0),
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// Data ports
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.A({{12{adc_signed_w[MIXER_WIDTH-1]}}, adc_signed_w}), // Sign-extend 18b to 30b
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.B({{2{cos_out[15]}}, cos_out}), // Sign-extend 16b to 18b
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.C(48'b0),
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.D(25'b0),
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.CARRYIN(1'b0),
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// Control ports
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.OPMODE(7'b0000101), // P = M (multiply only, no accumulate)
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.ALUMODE(4'b0000), // Z + X + Y + CIN
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.INMODE(5'b00000), // A2 * B2 (direct)
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.CARRYINSEL(3'b000),
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// Output ports
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.P(dsp_p_i),
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.PATTERNDETECT(),
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.PATTERNBDETECT(),
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.OVERFLOW(),
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.UNDERFLOW(),
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.CARRYOUT(),
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// Cascade ports (unused)
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.ACIN(30'b0),
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.BCIN(18'b0),
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.CARRYCASCIN(1'b0),
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.MULTSIGNIN(1'b0),
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.PCIN(48'b0),
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.ACOUT(),
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.BCOUT(),
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.CARRYCASCOUT(),
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.MULTSIGNOUT(),
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.PCOUT()
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);
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// DSP48E1 for Q-channel mixer (adc_signed * sin_out)
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DSP48E1 #(
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.A_INPUT("DIRECT"),
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.B_INPUT("DIRECT"),
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.USE_DPORT("FALSE"),
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.USE_MULT("MULTIPLY"),
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.USE_SIMD("ONE48"),
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.AREG(1),
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.BREG(1),
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.MREG(1),
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.PREG(1),
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.ADREG(0),
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.ACASCREG(1),
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.BCASCREG(1),
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.ALUMODEREG(0),
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.CARRYINREG(0),
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.CARRYINSELREG(0),
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.CREG(0),
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.DREG(0),
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.INMODEREG(0),
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.OPMODEREG(0),
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.AUTORESET_PATDET("NO_RESET"),
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.MASK(48'h3fffffffffff),
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.PATTERN(48'h000000000000),
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.SEL_MASK("MASK"),
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.SEL_PATTERN("PATTERN"),
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.USE_PATTERN_DETECT("NO_PATDET")
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) dsp_mixer_q (
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.CLK(clk_400m),
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.RSTA(reset_400m),
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.RSTB(reset_400m),
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.RSTM(reset_400m),
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.RSTP(reset_400m),
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.RSTALLCARRYIN(1'b0),
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.RSTALUMODE(1'b0),
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.RSTCTRL(1'b0),
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.RSTC(1'b0),
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.RSTD(1'b0),
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.RSTINMODE(1'b0),
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.CEA1(1'b0),
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.CEA2(1'b1),
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.CEB1(1'b0),
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.CEB2(1'b1),
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.CEM(1'b1),
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.CEP(1'b1), // P register clock enable (PREG=1)
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.CEAD(1'b0),
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.CEALUMODE(1'b0),
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.CECARRYIN(1'b0),
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.CECTRL(1'b0),
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.CEC(1'b0),
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.CED(1'b0),
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.CEINMODE(1'b0),
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.A({{12{adc_signed_w[MIXER_WIDTH-1]}}, adc_signed_w}),
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.B({{2{sin_out[15]}}, sin_out}),
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.C(48'b0),
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.D(25'b0),
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.CARRYIN(1'b0),
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.OPMODE(7'b0000101),
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.ALUMODE(4'b0000),
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.INMODE(5'b00000),
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.CARRYINSEL(3'b000),
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.P(dsp_p_q),
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.PATTERNDETECT(),
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.PATTERNBDETECT(),
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.OVERFLOW(),
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.UNDERFLOW(),
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.CARRYOUT(),
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.ACIN(30'b0),
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.BCIN(18'b0),
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.CARRYCASCIN(1'b0),
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.MULTSIGNIN(1'b0),
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.PCIN(48'b0),
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.ACOUT(),
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.BCOUT(),
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.CARRYCASCOUT(),
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.MULTSIGNOUT(),
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.PCOUT()
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);
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// Extract the multiply result from DSP48E1 P output
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// adc_signed is 18 bits, NCO is 16 bits → product is 34 bits (bits [33:0] of P)
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wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg = dsp_p_i[MIXER_WIDTH+NCO_WIDTH-1:0];
|
|
wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_q_reg = dsp_p_q[MIXER_WIDTH+NCO_WIDTH-1:0];
|
|
|
|
`endif
|
|
|
|
// ============================================================================
|
|
// Post-DSP48E1 output stage: force_saturation override + overflow detection
|
|
// force_saturation mux is intentionally AFTER the DSP48E1 output to avoid
|
|
// polluting the critical input path with extra logic
|
|
// ============================================================================
|
|
always @(posedge clk_400m or negedge reset_n_400m) begin
|
|
if (!reset_n_400m) begin
|
|
mixed_i <= 0;
|
|
mixed_q <= 0;
|
|
mixed_valid <= 0;
|
|
mixer_overflow_i <= 0;
|
|
mixer_overflow_q <= 0;
|
|
saturation_count <= 0;
|
|
overflow_detected <= 0;
|
|
end else if (dsp_valid_pipe[2]) begin
|
|
// Force saturation for testing (applied after DSP output, not on input path)
|
|
if (force_saturation_sync) begin
|
|
mixed_i <= 34'h1FFFFFFFF;
|
|
mixed_q <= 34'h200000000;
|
|
mixer_overflow_i <= 1'b1;
|
|
mixer_overflow_q <= 1'b1;
|
|
end else begin
|
|
// Normal path: take DSP48E1 multiply result
|
|
mixed_i <= mult_i_reg;
|
|
mixed_q <= mult_q_reg;
|
|
|
|
// Overflow detection on current cycle's multiply result
|
|
mixer_overflow_i <= (mult_i_reg > (2**(MIXER_WIDTH+NCO_WIDTH-2)-1)) ||
|
|
(mult_i_reg < -(2**(MIXER_WIDTH+NCO_WIDTH-2)));
|
|
mixer_overflow_q <= (mult_q_reg > (2**(MIXER_WIDTH+NCO_WIDTH-2)-1)) ||
|
|
(mult_q_reg < -(2**(MIXER_WIDTH+NCO_WIDTH-2)));
|
|
end
|
|
|
|
mixed_valid <= 1;
|
|
|
|
if (mixer_overflow_i || mixer_overflow_q) begin
|
|
saturation_count <= saturation_count + 1;
|
|
overflow_detected <= 1'b1;
|
|
end else begin
|
|
overflow_detected <= 1'b0;
|
|
end
|
|
|
|
end else begin
|
|
mixed_valid <= 0;
|
|
mixer_overflow_i <= 0;
|
|
mixer_overflow_q <= 0;
|
|
overflow_detected <= 1'b0;
|
|
end
|
|
end
|
|
|
|
// ============================================================================
|
|
// Enhanced CIC Decimators
|
|
// ============================================================================
|
|
wire cic_valid_i, cic_valid_q;
|
|
|
|
cic_decimator_4x_enhanced cic_i_inst (
|
|
.clk(clk_400m),
|
|
.reset_n(reset_n_400m),
|
|
.data_in(mixed_i[33:16]),
|
|
.data_valid(mixed_valid),
|
|
.data_out(cic_i_out),
|
|
.data_out_valid(cic_valid_i)
|
|
);
|
|
|
|
cic_decimator_4x_enhanced cic_q_inst (
|
|
.clk(clk_400m),
|
|
.reset_n(reset_n_400m),
|
|
.data_in(mixed_q[33:16]),
|
|
.data_valid(mixed_valid),
|
|
.data_out(cic_q_out),
|
|
.data_out_valid(cic_valid_q)
|
|
);
|
|
|
|
assign cic_valid = cic_valid_i & cic_valid_q;
|
|
|
|
// ============================================================================
|
|
// Enhanced FIR Filters with FIXED valid signal handling
|
|
// NOTE: Wire declarations moved BEFORE CDC instances to fix forward-reference
|
|
// error in Icarus Verilog (was originally after CDC instantiation)
|
|
// ============================================================================
|
|
wire fir_in_valid_i, fir_in_valid_q;
|
|
wire fir_valid_i, fir_valid_q;
|
|
wire fir_i_ready, fir_q_ready;
|
|
wire [17:0] fir_d_in_i, fir_d_in_q;
|
|
|
|
cdc_adc_to_processing #(
|
|
.WIDTH(18),
|
|
.STAGES(3)
|
|
)CDC_FIR_i(
|
|
.src_clk(clk_400m),
|
|
.dst_clk(clk_100m),
|
|
.src_reset_n(reset_n_400m),
|
|
.dst_reset_n(reset_n),
|
|
.src_data(cic_i_out),
|
|
.src_valid(cic_valid_i),
|
|
.dst_data(fir_d_in_i),
|
|
.dst_valid(fir_in_valid_i)
|
|
);
|
|
|
|
cdc_adc_to_processing #(
|
|
.WIDTH(18),
|
|
.STAGES(3)
|
|
)CDC_FIR_q(
|
|
.src_clk(clk_400m),
|
|
.dst_clk(clk_100m),
|
|
.src_reset_n(reset_n_400m),
|
|
.dst_reset_n(reset_n),
|
|
.src_data(cic_q_out),
|
|
.src_valid(cic_valid_q),
|
|
.dst_data(fir_d_in_q),
|
|
.dst_valid(fir_in_valid_q)
|
|
);
|
|
|
|
// ============================================================================
|
|
// FIR Filter Instances
|
|
// ============================================================================
|
|
|
|
// FIR I channel
|
|
fir_lowpass_parallel_enhanced fir_i_inst (
|
|
.clk(clk_100m),
|
|
.reset_n(reset_n),
|
|
.data_in(fir_d_in_i), // Use synchronized data
|
|
.data_valid(fir_in_valid_i), // Use synchronized valid
|
|
.data_out(fir_i_out),
|
|
.data_out_valid(fir_valid_i),
|
|
.fir_ready(fir_i_ready),
|
|
.filter_overflow()
|
|
);
|
|
|
|
// FIR Q channel
|
|
fir_lowpass_parallel_enhanced fir_q_inst (
|
|
.clk(clk_100m),
|
|
.reset_n(reset_n),
|
|
.data_in(fir_d_in_q), // Use synchronized data
|
|
.data_valid(fir_in_valid_q), // Use synchronized valid
|
|
.data_out(fir_q_out),
|
|
.data_out_valid(fir_valid_q),
|
|
.fir_ready(fir_q_ready),
|
|
.filter_overflow()
|
|
);
|
|
|
|
assign fir_valid = fir_valid_i & fir_valid_q;
|
|
|
|
// ============================================================================
|
|
// Enhanced Output Stage
|
|
// ============================================================================
|
|
always @(posedge clk_100m or negedge reset_n) begin
|
|
if (!reset_n) begin
|
|
baseband_i_reg <= 0;
|
|
baseband_q_reg <= 0;
|
|
baseband_valid_reg <= 0;
|
|
end else if (fir_valid) begin
|
|
baseband_i_reg <= fir_i_out;
|
|
baseband_q_reg <= fir_q_out;
|
|
baseband_valid_reg <= 1;
|
|
end else begin
|
|
baseband_valid_reg <= 0;
|
|
end
|
|
end
|
|
|
|
|
|
// ============================================================================
|
|
// Output Assignments
|
|
// ============================================================================
|
|
assign baseband_i = baseband_i_reg;
|
|
assign baseband_q = baseband_q_reg;
|
|
assign baseband_valid_i = baseband_valid_reg;
|
|
assign baseband_valid_q = baseband_valid_reg;
|
|
assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
|
|
assign mixer_saturation = overflow_detected;
|
|
assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
|
|
|
|
// ============================================================================
|
|
// Enhanced Debug and Monitoring
|
|
// ============================================================================
|
|
reg [31:0] debug_cic_count, debug_fir_count, debug_bb_count;
|
|
|
|
`ifdef SIMULATION
|
|
always @(posedge clk_100m) begin
|
|
|
|
if (fir_valid_i && debug_fir_count < 20) begin
|
|
debug_fir_count <= debug_fir_count + 1;
|
|
$display("FIR_OUTPUT: fir_i=%6d, fir_q=%6d", fir_i_out, fir_q_out);
|
|
end
|
|
|
|
if (adc_data_valid_i && adc_data_valid_q && debug_bb_count < 20) begin
|
|
debug_bb_count <= debug_bb_count + 1;
|
|
$display("BASEBAND_OUT: i=%6d, q=%6d, count=%0d",
|
|
baseband_i, baseband_q, debug_bb_count);
|
|
end
|
|
end
|
|
`endif
|
|
|
|
// In ddc_400m.v, add these debug signals:
|
|
|
|
// Debug monitoring (simulation only)
|
|
`ifdef SIMULATION
|
|
reg [31:0] debug_adc_count = 0;
|
|
reg [31:0] debug_baseband_count = 0;
|
|
|
|
always @(posedge clk_400m) begin
|
|
if (adc_data_valid_i && adc_data_valid_q && debug_adc_count < 10) begin
|
|
debug_adc_count <= debug_adc_count + 1;
|
|
$display("DDC_ADC: data=%0d, count=%0d, time=%t",
|
|
adc_data, debug_adc_count, $time);
|
|
end
|
|
end
|
|
|
|
always @(posedge clk_100m) begin
|
|
if (baseband_valid_i && baseband_valid_q && debug_baseband_count < 10) begin
|
|
debug_baseband_count <= debug_baseband_count + 1;
|
|
$display("DDC_BASEBAND: i=%0d, q=%0d, count=%0d, time=%t",
|
|
baseband_i, baseband_q, debug_baseband_count, $time);
|
|
end
|
|
end
|
|
`endif
|
|
|
|
|
|
endmodule
|
|
|
|
// ============================================================================
|
|
// Enhanced Phase Dithering Module
|
|
// ============================================================================
|
|
`timescale 1ns / 1ps
|
|
|
|
module lfsr_dither_enhanced #(
|
|
parameter DITHER_WIDTH = 8 // Increased for better dithering
|
|
)(
|
|
input wire clk,
|
|
input wire reset_n,
|
|
input wire enable,
|
|
output wire [DITHER_WIDTH-1:0] dither_out
|
|
);
|
|
|
|
reg [DITHER_WIDTH-1:0] lfsr_reg;
|
|
reg [15:0] cycle_counter;
|
|
reg lock_detected;
|
|
|
|
// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
|
|
wire feedback;
|
|
|
|
generate
|
|
if (DITHER_WIDTH == 4) begin
|
|
assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
|
|
end else if (DITHER_WIDTH == 8) begin
|
|
assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
|
|
end else begin
|
|
assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
|
|
end
|
|
endgenerate
|
|
|
|
always @(posedge clk or negedge reset_n) begin
|
|
if (!reset_n) begin
|
|
lfsr_reg <= {DITHER_WIDTH{1'b1}}; // Non-zero initial state
|
|
cycle_counter <= 0;
|
|
lock_detected <= 0;
|
|
end else if (enable) begin
|
|
lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
|
|
cycle_counter <= cycle_counter + 1;
|
|
|
|
// Detect LFSR lock after sufficient cycles
|
|
if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
|
|
lock_detected <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
|
|
assign dither_out = lfsr_reg;
|
|
|
|
endmodule
|