Jason 30f56f3089 fix(constraints): use LVDS (not LVDS_33) for 50T Bank 14 ADC inputs ...

LVDS_33 is not a valid I/O standard on 7-series FPGAs. The correct
standard for LVDS inputs in HR banks with VCCO != 2.5V is LVDS, which
works with any VCCO for input-only buffers (IBUFDS). LVDS_25 requires
VCCO=2.5V exactly.

Note: the 50T FTG256 build still fails at placement due to pin overflow
(113 ports vs 69 available pins) — this is a pre-existing package
limitation unrelated to this fix.

2026-04-07 05:31:48 +03:00

..

9_1_Microcontroller

Gap 3 Safety Architecture: IWDG watchdog, Emergency_Stop PA rail cutoff, temp max, periodic IDQ re-read, emergency state ordering + 5 tests (20/20 pass)

2026-03-19 21:58:39 +02:00

9_2_FPGA

fix(constraints): use LVDS (not LVDS_33) for 50T Bank 14 ADC inputs

2026-04-07 05:31:48 +03:00

9_3_GUI

fix(rtl,gui,cosim,formal): adapt surrounding files for dual 16-pt FFT (follow-up to PR #33)

2026-04-06 23:15:50 +03:00

tools

Add UART diagnostic capture tool for board-day bring-up

2026-03-19 16:32:54 +02:00