Files
PLFM_RADAR/9_Firmware/9_2_FPGA
Jason 254c0e6f03 Improve timing margins with targeted datapath register tuning
Reduce routing pressure on CIC/NCO critical paths and move Doppler BRAM read-address registers to sync-reset datapath logic so Build 13 closes with stronger setup/hold slack while preserving functional behavior.
2026-03-17 23:51:04 +02:00
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