Jason 254c0e6f03 Improve timing margins with targeted datapath register tuning ...

Reduce routing pressure on CIC/NCO critical paths and move Doppler BRAM read-address registers to sync-reset datapath logic so Build 13 closes with stronger setup/hold slack while preserving functional behavior.

2026-03-17 23:51:04 +02:00

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9_1_Microcontroller

Merge pull request #7 from walidb212/fix/gy85-i2c-status

2026-03-15 01:57:28 +00:00

9_2_FPGA

Improve timing margins with targeted datapath register tuning

2026-03-17 23:51:04 +02:00

9_3_GUI

Added missing classes and functions

2026-03-16 22:25:10 +00:00