Jason
1f315a62c8
Build scripts (17-21): STATS.WNS/TNS/WHS/THS/TPWS from get_property can return empty strings in Vivado 2025.2 after write_bitstream auto-launch. Wrap in catch with N/A fallback. Guard all expr delta calculations and signoff comparisons with [string is double -strict] checks. XDC (xc7a50t_ftg256): Fix PLIO-9 by moving clk_120m_dac from C13 (N-type) to D13 (P-type MRCC) — clock inputs require P-type MRCC pin. Fix BIVC-1 by disabling DIFF_TERM on Bank 14 LVDS pairs to resolve VCCO conflict with single-ended adc_pwdn (LVCMOS33) on T5 — requires external termination.
338 lines
17 KiB
Tcl
338 lines
17 KiB
Tcl
# ============================================================================
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# RADAR SYSTEM FPGA CONSTRAINTS
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# ============================================================================
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# Device: XC7A50T-2FTG256I (FTG256 package)
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# Board: AERIS-10 Phased Array Radar — Main Board
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# Source: Pin assignments extracted from Eagle schematic (RADAR_Main_Board.sch)
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# FPGA = U42
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#
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# NOTE: The README and prior version of this file incorrectly referenced
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# XC7A100TCSG324-1. The physical board uses XC7A50T in a 256-ball BGA
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# (FTG256). All PACKAGE_PIN values below are FTG256 ball locations.
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#
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# I/O Bank Voltage Summary:
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# Bank 0: VCCO = 3.3V (JTAG, flash CS)
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# Bank 14: VCCO = 3.3V (ADC LVDS data, SPI flash, adc_pwdn)
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# Bank 15: VCCO = 3.3V (DAC, clocks, STM32 SPI 3.3V side, DIG bus, mixer)
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# Bank 34: VCCO = 1.8V (ADAR1000 beamformer control, SPI 1.8V side)
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# Bank 35: VCCO = 3.3V (unused — no signal connections)
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#
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# DRC Fix History:
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# - PLIO-9: Moved clk_120m_dac from C13 (N-type) to D13 (P-type MRCC).
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# Clock inputs must use the P-type pin of a Multi-Region Clock-Capable pair.
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# - BIVC-1: Disabled DIFF_TERM on Bank 14 LVDS pairs (adc_dco, adc_d) to
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# resolve VCCO conflict with single-ended adc_pwdn (LVCMOS33) on T5.
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# External 100-ohm differential termination required on board.
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# ============================================================================
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# ============================================================================
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# CLOCK CONSTRAINTS
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# ============================================================================
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# 100MHz System Clock (AD9523 OUT6 → FPGA_SYS_CLOCK → Bank 15 MRCC pin E12)
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set_property PACKAGE_PIN E12 [get_ports {clk_100m}]
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set_property IOSTANDARD LVCMOS33 [get_ports {clk_100m}]
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create_clock -name clk_100m -period 10.0 [get_ports {clk_100m}]
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set_input_jitter [get_clocks clk_100m] 0.1
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# 120MHz DAC Clock (AD9523 OUT11 → FPGA_DAC_CLOCK → Bank 15 MRCC pin D13)
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# NOTE: The physical DAC (U3, AD9708) receives its clock directly from the
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# AD9523 via a separate net (DAC_CLOCK), NOT from the FPGA. The FPGA
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# uses this clock input for internal DAC data timing only. The RTL port
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# `dac_clk` is an output that assigns clk_120m directly — it has no
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# separate physical pin on this board and should be removed from the
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# RTL or left unconnected.
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# FIX: Moved from C13 (IO_L12N = N-type) to D13 (IO_L12P = P-type MRCC).
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# Clock inputs must use the P-type pin of an MRCC pair (PLIO-9 DRC).
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set_property PACKAGE_PIN D13 [get_ports {clk_120m_dac}]
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set_property IOSTANDARD LVCMOS33 [get_ports {clk_120m_dac}]
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create_clock -name clk_120m_dac -period 8.333 [get_ports {clk_120m_dac}]
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set_input_jitter [get_clocks clk_120m_dac] 0.1
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# ADC DCO Clock (400MHz LVDS — AD9523 OUT5 → AD9484 → FPGA, Bank 14 MRCC)
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set_property PACKAGE_PIN N14 [get_ports {adc_dco_p}]
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set_property PACKAGE_PIN P14 [get_ports {adc_dco_n}]
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set_property IOSTANDARD LVDS_33 [get_ports {adc_dco_p}]
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set_property IOSTANDARD LVDS_33 [get_ports {adc_dco_n}]
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# NOTE: DIFF_TERM disabled to avoid BIVC-1 DRC conflict with single-ended
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# adc_pwdn (LVCMOS33) on T5 in the same bank. The board should have external
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# 100-ohm differential termination on the ADC LVDS pairs. If signal integrity
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# issues arise, the board may need adc_pwdn relocated to a non-Bank-14 pin.
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# set_property DIFF_TERM TRUE [get_ports {adc_dco_p}]
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create_clock -name adc_dco_p -period 2.5 [get_ports {adc_dco_p}]
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set_input_jitter [get_clocks adc_dco_p] 0.05
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# --------------------------------------------------------------------------
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# FT601 Clock — COMMENTED OUT: FT601 (U6) is placed in schematic but has
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# zero net connections. No physical clock pin exists on this board.
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# --------------------------------------------------------------------------
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# create_clock -name ft601_clk_in -period 10.0 [get_ports {ft601_clk_in}]
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# set_input_jitter [get_clocks ft601_clk_in] 0.1
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# ============================================================================
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# RESET (Active-Low)
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# ============================================================================
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# DIG_4 (STM32 PD12 → FPGA Bank 15 pin E15)
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# STM32 firmware uses HAL_GPIO_WritePin to assert/deassert FPGA reset.
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set_property PACKAGE_PIN E15 [get_ports {reset_n}]
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set_property IOSTANDARD LVCMOS33 [get_ports {reset_n}]
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set_property PULLUP true [get_ports {reset_n}]
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# ============================================================================
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# TRANSMITTER INTERFACE (DAC — Bank 15, VCCO=3.3V)
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# ============================================================================
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# DAC Data Bus (8-bit) — AD9708 data inputs via schematic nets DAC_0..DAC_7
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set_property PACKAGE_PIN A14 [get_ports {dac_data[0]}]
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set_property PACKAGE_PIN A13 [get_ports {dac_data[1]}]
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set_property PACKAGE_PIN A12 [get_ports {dac_data[2]}]
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set_property PACKAGE_PIN B11 [get_ports {dac_data[3]}]
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set_property PACKAGE_PIN B10 [get_ports {dac_data[4]}]
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set_property PACKAGE_PIN A10 [get_ports {dac_data[5]}]
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set_property PACKAGE_PIN A9 [get_ports {dac_data[6]}]
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set_property PACKAGE_PIN A8 [get_ports {dac_data[7]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {dac_data[*]}]
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set_property SLEW FAST [get_ports {dac_data[*]}]
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set_property DRIVE 8 [get_ports {dac_data[*]}]
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# DAC Clock Output — NOT DIRECTLY WIRED TO DAC IN SCHEMATIC
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# The DAC chip (U3) receives its clock from AD9523 via a separate net
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# (DAC_CLOCK), not from the FPGA. The RTL `dac_clk` output has no
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# physical pin. Comment out or remove from RTL.
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# set_property PACKAGE_PIN ??? [get_ports {dac_clk}]
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# set_property IOSTANDARD LVCMOS33 [get_ports {dac_clk}]
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# set_property SLEW FAST [get_ports {dac_clk}]
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# DAC Sleep Control — DAC_SLEEP net
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set_property PACKAGE_PIN A15 [get_ports {dac_sleep}]
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set_property IOSTANDARD LVCMOS33 [get_ports {dac_sleep}]
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# RF Switch Control — M3S_VCTRL net
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set_property PACKAGE_PIN G15 [get_ports {fpga_rf_switch}]
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set_property IOSTANDARD LVCMOS33 [get_ports {fpga_rf_switch}]
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# Mixer Enables — MIX_RX_EN, MIX_TX_EN nets
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set_property PACKAGE_PIN D11 [get_ports {rx_mixer_en}]
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set_property PACKAGE_PIN C11 [get_ports {tx_mixer_en}]
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set_property IOSTANDARD LVCMOS33 [get_ports {rx_mixer_en}]
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set_property IOSTANDARD LVCMOS33 [get_ports {tx_mixer_en}]
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# ============================================================================
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# ADAR1000 BEAMFORMER CONTROL (Bank 34, VCCO=1.8V)
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# ============================================================================
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# ADAR1000 TX Load Pins (via level shifters, active-high pulse)
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set_property PACKAGE_PIN P3 [get_ports {adar_tx_load_1}]
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set_property PACKAGE_PIN T4 [get_ports {adar_tx_load_2}]
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set_property PACKAGE_PIN R3 [get_ports {adar_tx_load_3}]
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set_property PACKAGE_PIN R2 [get_ports {adar_tx_load_4}]
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# ADAR1000 RX Load Pins
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set_property PACKAGE_PIN M5 [get_ports {adar_rx_load_1}]
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set_property PACKAGE_PIN T2 [get_ports {adar_rx_load_2}]
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set_property PACKAGE_PIN R1 [get_ports {adar_rx_load_3}]
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set_property PACKAGE_PIN N4 [get_ports {adar_rx_load_4}]
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# Bank 34 VCCO = 1.8V → must use LVCMOS18 (not LVCMOS33)
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set_property IOSTANDARD LVCMOS18 [get_ports {adar_*_load_*}]
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# ADAR1000 TR (Transmit/Receive) Pins
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set_property PACKAGE_PIN N2 [get_ports {adar_tr_1}]
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set_property PACKAGE_PIN N1 [get_ports {adar_tr_2}]
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set_property PACKAGE_PIN P1 [get_ports {adar_tr_3}]
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set_property PACKAGE_PIN P4 [get_ports {adar_tr_4}]
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set_property IOSTANDARD LVCMOS18 [get_ports {adar_tr_*}]
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# ============================================================================
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# LEVEL SHIFTER SPI INTERFACE (STM32 ↔ ADAR1000)
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# ============================================================================
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# 3.3V Side (from STM32, Bank 15, VCCO=3.3V)
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set_property PACKAGE_PIN J16 [get_ports {stm32_sclk_3v3}]
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set_property PACKAGE_PIN H13 [get_ports {stm32_mosi_3v3}]
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set_property PACKAGE_PIN G14 [get_ports {stm32_miso_3v3}]
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set_property PACKAGE_PIN F14 [get_ports {stm32_cs_adar1_3v3}]
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set_property PACKAGE_PIN H16 [get_ports {stm32_cs_adar2_3v3}]
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set_property PACKAGE_PIN G16 [get_ports {stm32_cs_adar3_3v3}]
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set_property PACKAGE_PIN J15 [get_ports {stm32_cs_adar4_3v3}]
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set_property IOSTANDARD LVCMOS33 [get_ports {stm32_*_3v3}]
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# 1.8V Side (to ADAR1000, Bank 34, VCCO=1.8V)
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set_property PACKAGE_PIN P5 [get_ports {stm32_sclk_1v8}]
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set_property PACKAGE_PIN M1 [get_ports {stm32_mosi_1v8}]
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set_property PACKAGE_PIN N3 [get_ports {stm32_miso_1v8}]
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set_property PACKAGE_PIN L5 [get_ports {stm32_cs_adar1_1v8}]
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set_property PACKAGE_PIN L4 [get_ports {stm32_cs_adar2_1v8}]
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set_property PACKAGE_PIN M4 [get_ports {stm32_cs_adar3_1v8}]
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set_property PACKAGE_PIN M2 [get_ports {stm32_cs_adar4_1v8}]
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set_property IOSTANDARD LVCMOS18 [get_ports {stm32_*_1v8}]
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# ============================================================================
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# STM32 CONTROL INTERFACE (DIG bus, Bank 15, VCCO=3.3V)
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# ============================================================================
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# DIG_0..DIG_4 are STM32 outputs (PD8-PD12) → FPGA inputs
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# DIG_5..DIG_7 are STM32 inputs (PD13-PD15) ← FPGA outputs (unused in RTL)
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set_property PACKAGE_PIN F13 [get_ports {stm32_new_chirp}] ;# DIG_0 (PD8)
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set_property PACKAGE_PIN E16 [get_ports {stm32_new_elevation}] ;# DIG_1 (PD9)
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set_property PACKAGE_PIN D16 [get_ports {stm32_new_azimuth}] ;# DIG_2 (PD10)
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set_property PACKAGE_PIN F15 [get_ports {stm32_mixers_enable}] ;# DIG_3 (PD11)
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set_property IOSTANDARD LVCMOS33 [get_ports {stm32_new_*}]
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set_property IOSTANDARD LVCMOS33 [get_ports {stm32_mixers_enable}]
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# reset_n is DIG_4 (PD12) — constrained above in the RESET section
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# DIG_5 = H11, DIG_6 = G12, DIG_7 = H12 — available for FPGA→STM32 status
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# Currently unused in RTL. Could be connected to status outputs if needed.
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# ============================================================================
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# ADC INTERFACE (LVDS — Bank 14, VCCO=3.3V)
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# ============================================================================
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# ADC Data (8-bit LVDS pairs from AD9484)
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set_property PACKAGE_PIN P15 [get_ports {adc_d_p[0]}]
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set_property PACKAGE_PIN P16 [get_ports {adc_d_n[0]}]
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set_property PACKAGE_PIN R15 [get_ports {adc_d_p[1]}]
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set_property PACKAGE_PIN R16 [get_ports {adc_d_n[1]}]
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set_property PACKAGE_PIN T14 [get_ports {adc_d_p[2]}]
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set_property PACKAGE_PIN T15 [get_ports {adc_d_n[2]}]
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set_property PACKAGE_PIN R13 [get_ports {adc_d_p[3]}]
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set_property PACKAGE_PIN T13 [get_ports {adc_d_n[3]}]
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set_property PACKAGE_PIN R10 [get_ports {adc_d_p[4]}]
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set_property PACKAGE_PIN R11 [get_ports {adc_d_n[4]}]
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set_property PACKAGE_PIN T9 [get_ports {adc_d_p[5]}]
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set_property PACKAGE_PIN T10 [get_ports {adc_d_n[5]}]
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set_property PACKAGE_PIN T7 [get_ports {adc_d_p[6]}]
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set_property PACKAGE_PIN T8 [get_ports {adc_d_n[6]}]
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set_property PACKAGE_PIN R6 [get_ports {adc_d_p[7]}]
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set_property PACKAGE_PIN R7 [get_ports {adc_d_n[7]}]
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# ADC DCO Clock (LVDS) — already constrained above in CLOCK section
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# ADC Power Down — ADC_PWRD net (single-ended, Bank 14)
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set_property PACKAGE_PIN T5 [get_ports {adc_pwdn}]
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set_property IOSTANDARD LVCMOS33 [get_ports {adc_pwdn}]
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# LVDS I/O Standard — Bank 14 VCCO = 3.3V → use LVDS_33 (not LVDS_25)
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set_property IOSTANDARD LVDS_33 [get_ports {adc_d_p[*]}]
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set_property IOSTANDARD LVDS_33 [get_ports {adc_d_n[*]}]
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# Differential termination — disabled to avoid BIVC-1 DRC conflict with
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# single-ended adc_pwdn (LVCMOS33) on T5 in the same bank. Requires external
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# 100-ohm differential termination on the board for proper LVDS signal integrity.
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# set_property DIFF_TERM TRUE [get_ports {adc_d_p[*]}]
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# Input delay for ADC data relative to DCO (adjust based on PCB trace length)
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set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 [get_ports {adc_d_p[*]}]
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set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_d_p[*]}]
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# ============================================================================
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# FT601 USB 3.0 INTERFACE — ACTIVE: NO PHYSICAL CONNECTIONS
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# ============================================================================
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# The FT601 chip (U6, FT601Q-B-T) is placed in the Eagle schematic but has
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# ZERO net connections — no signals are routed between it and the FPGA.
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# Bank 35 (which would logically host FT601 signals) has no signal pins
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# connected, only VCCO_35 power.
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#
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# ALL FT601 constraints are commented out. The RTL module usb_data_interface.v
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# instantiates the FT601 interface, but it cannot function without physical
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# pin assignments. To use USB, the schematic must be updated to wire the
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# FT601 to FPGA Bank 35 pins, and then these constraints can be populated.
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#
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# Ports affected (from radar_system_top.v):
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# ft601_data[31:0], ft601_be[1:0], ft601_txe_n, ft601_rxf_n, ft601_txe,
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# ft601_rxf, ft601_wr_n, ft601_rd_n, ft601_oe_n, ft601_siwu_n,
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# ft601_srb[1:0], ft601_swb[1:0], ft601_clk_out, ft601_clk_in
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#
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# TODO: Wire FT601 in schematic, then assign pins here.
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# ============================================================================
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# ============================================================================
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# STATUS / DEBUG OUTPUTS — NO PHYSICAL CONNECTIONS
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# ============================================================================
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# The following RTL output ports have no corresponding FPGA pins in the
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# schematic. The only FPGA→STM32 outputs available are DIG_5 (H11),
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# DIG_6 (G12), and DIG_7 (H12) — only 3 pins for potentially 60+ signals.
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#
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# These constraints are commented out. If status readback is needed, either:
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# (a) Multiplex selected status bits onto DIG_5/6/7, or
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# (b) Send status data over the SPI interface, or
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# (c) Route through USB once FT601 is wired.
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#
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# Ports affected:
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# current_elevation[5:0], current_azimuth[5:0], current_chirp[5:0],
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# new_chirp_frame, dbg_doppler_data[31:0], dbg_doppler_valid,
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# dbg_doppler_bin[4:0], dbg_range_bin[5:0], system_status[3:0]
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# ============================================================================
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# ============================================================================
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# TIMING EXCEPTIONS
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# ============================================================================
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# False paths for asynchronous STM32 control signals (active-edge toggle interface)
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set_false_path -from [get_ports {stm32_new_*}]
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set_false_path -from [get_ports {stm32_mixers_enable}]
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# --------------------------------------------------------------------------
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# Async reset recovery/removal false paths
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#
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# The async reset (reset_n) is held asserted for multiple clock cycles during
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# power-on and system reset. The recovery/removal timing checks on CLR pins
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# are over-constrained for this use case:
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# - reset_sync_reg[1] fans out to 1000+ registers across the FPGA
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# - Route delay alone exceeds the clock period (18+ ns for 10ns period)
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# - Reset deassertion order is not functionally critical — all registers
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# come out of reset within a few cycles of each other
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# --------------------------------------------------------------------------
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set_false_path -from [get_cells reset_sync_reg[*]] -to [get_pins -filter {REF_PIN_NAME == CLR} -of_objects [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ REGISTER.*.*}]]
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# --------------------------------------------------------------------------
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# Clock Domain Crossing false paths
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# --------------------------------------------------------------------------
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# clk_100m ↔ adc_dco_p (400 MHz): DDC has internal CDC synchronizers
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set_false_path -from [get_clocks clk_100m] -to [get_clocks adc_dco_p]
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set_false_path -from [get_clocks adc_dco_p] -to [get_clocks clk_100m]
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# clk_100m ↔ clk_120m_dac: CDC via synchronizers in radar_system_top
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set_false_path -from [get_clocks clk_100m] -to [get_clocks clk_120m_dac]
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set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_100m]
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# FT601 CDC paths removed — no ft601_clk_in clock defined (chip unwired)
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# ============================================================================
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# PHYSICAL CONSTRAINTS
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# ============================================================================
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# Pull up unused pins to prevent floating inputs
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set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
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# ============================================================================
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# ADDITIONAL NOTES
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# ============================================================================
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#
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# 1. ADC Sampling Clock: FPGA_ADC_CLOCK_P/N (N11/N12) is the 400 MHz LVDS
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# clock from AD9523 OUT5 that drives the AD9484. It connects to FPGA MRCC
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# pins but is not used as an FPGA clock input — the ADC returns data with
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# its own DCO (adc_dco_p/n on N14/P14).
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#
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# 2. Clock Test: FPGA_CLOCK_TEST (H14) is a 20 MHz LVCMOS output from the
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# FPGA, configured by AD9523 OUT7. Not currently used in RTL.
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#
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# 3. SPI Flash: FPGA_FLASH_CS (E8), FPGA_FLASH_CLK (J13),
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# FPGA_FLASH_D0 (J14), D1 (K15), D2 (K16), D3 (L12), unnamed (L13).
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# These are typically handled by Vivado bitstream configuration and do
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# not need explicit XDC constraints for user logic.
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#
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# 4. JTAG: FPGA_TCK (L7), FPGA_TDI (N7), FPGA_TDO (N8), FPGA_TMS (M7).
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# Dedicated pins — no XDC constraints needed.
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#
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# 5. dac_clk port: The RTL top module declares `dac_clk` as an output, but
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# the physical board wires the DAC clock (AD9708 CLOCK pin) directly from
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# the AD9523, not from the FPGA. This port should be removed from the RTL
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# or left unconnected. It currently just assigns clk_120m_dac passthrough.
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#
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# ============================================================================
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# END OF CONSTRAINTS
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# ============================================================================
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