2 Commits

Author	SHA1	Message	Date
Jason	1f315a62c8	fix(scripts,constraints): handle empty STATS properties in build summaries, fix 50T XDC DRC errors ... Build scripts (17-21): STATS.WNS/TNS/WHS/THS/TPWS from get_property can return empty strings in Vivado 2025.2 after write_bitstream auto-launch. Wrap in catch with N/A fallback. Guard all expr delta calculations and signoff comparisons with [string is double -strict] checks. XDC (xc7a50t_ftg256): Fix PLIO-9 by moving clk_120m_dac from C13 (N-type) to D13 (P-type MRCC) — clock inputs require P-type MRCC pin. Fix BIVC-1 by disabling DIFF_TERM on Bank 14 LVDS pairs to resolve VCCO conflict with single-ended adc_pwdn (LVCMOS33) on T5 — requires external termination.	2026-04-07 05:07:14 +03:00
Jason	1acedf494c	Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I ... Production FPGA: Artix-7 XC7A200T-2FBG484I (33,650 slices, 740 DSP48E1, 365 BRAM, -2 speed grade). Pin-mapped across 6 banks with proper VCCO assignment (3.3V/2.5V/1.8V). RTL timing primitives added for clean timing closure: - ad9484_interface_400m.v: BUFIO for IDDR capture at 400MHz DDR, BUFG for fabric logic, reset synchronizer (P1-7) - dac_interface_single.v: ODDR for dac_clk forwarding + dac_data[7:0] output registration, eliminates clock-forwarding insertion delay - usb_data_interface.v: ODDR for ft601_clk_out forwarding, FSM runs on ft601_clk_in domain with CDC synchronizers Constraints: - New production XDC (xc7a200t_fbg484.xdc): 182 pins, generated clocks for ODDR outputs, BUFIO/DDR input delays, fixed false_path strategy (from reset source, not to CLR pins), IOB packing on cells not ports - Preserved upstream XDC as xc7a50t_ftg256.xdc for reference - Updated cntrt.xdc with DRC fixes (I/O standards, missing constraints)	2026-03-16 22:24:22 +02:00