Jason
063fa081fe
FPGA timing (400MHz domain WNS: +0.339ns, was +0.002ns): - DONT_TOUCH on BUFG to prevent AggressiveExplore cascade replication - NCO→mixer pipeline registers break critical 1.5ns route - Clock uncertainty reduced 200ps→100ps (adequate guardband) - Updated golden/cosim references for +1 cycle pipeline latency STM32 bug fixes: - Guard uint32_t underflow in processStartFlag (length<4) - Replace unbounded strcat in getSystemStatusForGUI with snprintf - Early-return error masking in checkSystemHealth - Add HAL_Delay in emergency blink loop GUI bug fixes: - Remove 0x03 from _HARDWARE_ONLY_OPCODES (was in both sets) - Wire real error count in V7 diagnostics panel - Fix _stop_demo showing 'Live' label during replay mode FPGA comment fixes + CI: add test_v7.py to pytest command Vivado build 50t passed: 0 failing endpoints, WHS=+0.056ns
117 lines
3.4 KiB
YAML
117 lines
3.4 KiB
YAML
name: AERIS-10 CI
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on:
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pull_request:
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branches: [main, develop]
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push:
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branches: [main, develop]
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jobs:
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# ===========================================================================
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# Python: lint (ruff), syntax check (py_compile), unit tests (pytest)
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# CI structure proposed by hcm444 — uses uv for dependency management
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# ===========================================================================
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python-tests:
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name: Python Lint + Tests
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v4
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- uses: actions/setup-python@v5
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with:
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python-version: "3.12"
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- uses: astral-sh/setup-uv@v5
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- name: Install dependencies
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run: uv sync --group dev
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- name: Ruff lint (whole repo)
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run: uv run ruff check .
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- name: Syntax check (py_compile)
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run: |
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uv run python - <<'PY'
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import py_compile
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from pathlib import Path
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skip = {".git", "__pycache__", ".venv", "venv", "docs"}
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for p in Path(".").rglob("*.py"):
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if skip & set(p.parts):
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continue
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py_compile.compile(str(p), doraise=True)
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PY
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- name: Unit tests
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run: >
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uv run pytest
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9_Firmware/9_3_GUI/test_radar_dashboard.py
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9_Firmware/9_3_GUI/test_v7.py
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-v --tb=short
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# ===========================================================================
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# MCU Firmware Unit Tests (20 tests)
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# Bug regression (15) + Gap-3 safety tests (5)
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# ===========================================================================
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mcu-tests:
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name: MCU Firmware Tests
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v4
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- name: Install build tools
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run: sudo apt-get update && sudo apt-get install -y build-essential
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- name: Build and run MCU tests
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run: make test
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working-directory: 9_Firmware/9_1_Microcontroller/tests
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# ===========================================================================
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# FPGA RTL Regression (25 testbenches + lint)
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# ===========================================================================
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fpga-regression:
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name: FPGA Regression
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v4
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- name: Install Icarus Verilog
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run: sudo apt-get update && sudo apt-get install -y iverilog
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- name: Run full FPGA regression
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run: bash run_regression.sh
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working-directory: 9_Firmware/9_2_FPGA
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# ===========================================================================
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# Cross-Layer Contract Tests (Python ↔ Verilog ↔ C)
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# Validates opcode maps, bit widths, packet layouts, and round-trip
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# correctness across FPGA RTL, Python GUI, and STM32 firmware.
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# ===========================================================================
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cross-layer-tests:
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name: Cross-Layer Contract Tests
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v4
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- uses: actions/setup-python@v5
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with:
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python-version: "3.12"
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- uses: astral-sh/setup-uv@v5
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- name: Install dependencies
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run: uv sync --group dev
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- name: Install Icarus Verilog
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run: sudo apt-get update && sudo apt-get install -y iverilog
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- name: Run cross-layer contract tests
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run: >
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uv run pytest
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9_Firmware/tests/cross_layer/test_cross_layer_contract.py
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-v --tb=short
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