Jason
02925ac34e
- Correct carrier from 10.525/10 GHz to 10.5 GHz (verified ADF4382 config) - Correct range-per-bin from 4.8/5.6/781.25 m to 24.0 m (matched-filter) - Correct velocity resolution from 1.484 to 2.67 m/s/bin (PRI-based) - Correct processing rate from 4 MSPS to 100 MSPS (post-DDC) - Correct max range from 307/5000/50000 m to 1536 m (64 bins x 24 m) - Add WaveformConfig.pri_s field (167 us PRI for velocity calculation) - Fix short chirp chirp_complete deadlock (Bug A) - Remove dead short_chirp ports, rename long_chirp to ref_chirp (Bug B) - Fix stale latency comment 2159 -> 3187 cycles (Bug C) - Create radar_params.vh as single source of truth for FPGA parameters - Lower RadarSettings.cpp map_size validation bound from 1000 to 100 - Add PLFM hardware constants to golden_reference.py - Update all GUI versions, tests, and cross-layer contracts All 244 tests passing (167 Python + 21 MCU + 29 cross-layer + 27 FPGA)
28 lines
963 B
Python
28 lines
963 B
Python
import numpy as np
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# Define parameters
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# NOTE: This is a standalone LUT generation utility. The production chirp LUT
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# is generated by 9_Firmware/9_2_FPGA/tb/cosim/gen_chirp_mem.py with
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# CHIRP_BW=20e6 (target: 30e6 Phase 1) and DAC_CLK=120e6.
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fs = 120e6 # Sampling frequency (DAC clock from AD9523 OUT10)
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Ts = 1 / fs # Sampling time
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Tb = 1e-6 # Burst time
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Tau = 30e-6 # Pulse repetition time
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fmax = 15e6 # Maximum frequency on ramp
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fmin = 1e6 # Minimum frequency on ramp
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# Compute number of samples per ramp
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n = int(Tb / Ts)
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N = np.arange(0, n, 1)
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# Compute instantaneous phase
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theta_n = 2 * np.pi * ((N**2 * Ts**2 * (fmax - fmin) / (2 * Tb)) + fmin * N * Ts)
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# Generate waveform and scale it to 8-bit unsigned values (0 to 255)
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y = 1 + np.sin(theta_n) # Normalize from 0 to 2
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y_scaled = np.round(y * 127.5).astype(int) # Scale to 8-bit range (0-255)
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# Print values in Verilog-friendly format
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for _i in range(n):
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pass
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