Jason
2106e24952
- Expand ruff config from E/F to 17 rule sets (B, RUF, SIM, PIE, T20, ARG, ERA, A, BLE, RET, ISC, TCH, UP, C4, PERF) - Fix 907 lint errors across all Python files (GUI, FPGA cosim, schematics scripts, simulations, utilities, tools) - Replace all blind except-Exception with specific exception types - Remove commented-out dead code (ERA001) from cosim/simulation files - Modernize typing: deprecated typing.List/Dict/Tuple to builtins - Fix unused args/loop vars, ambiguous unicode, perf anti-patterns - Delete legacy GUI files V1-V4 - Add V7 test suite, requirements files - All CI jobs pass: ruff (0 errors), py_compile, pytest (92/92), MCU tests (20/20), FPGA regression (25/25)
25 lines
725 B
Python
25 lines
725 B
Python
import numpy as np
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# Define parameters
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fs = 120e6 # Sampling frequency
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Ts = 1 / fs # Sampling time
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Tb = 1e-6 # Burst time
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Tau = 30e-6 # Pulse repetition time
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fmax = 15e6 # Maximum frequency on ramp
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fmin = 1e6 # Minimum frequency on ramp
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# Compute number of samples per ramp
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n = int(Tb / Ts)
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N = np.arange(0, n, 1)
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# Compute instantaneous phase
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theta_n = 2 * np.pi * ((N**2 * Ts**2 * (fmax - fmin) / (2 * Tb)) + fmin * N * Ts)
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# Generate waveform and scale it to 8-bit unsigned values (0 to 255)
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y = 1 + np.sin(theta_n) # Normalize from 0 to 2
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y_scaled = np.round(y * 127.5).astype(int) # Scale to 8-bit range (0-255)
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# Print values in Verilog-friendly format
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for _i in range(n):
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pass
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