NawfalMotii79
168b9b2ae0
Updated the HTML structure and content for the AERIS-10 documentation site, including new sections for engineering documentation and navigation links.
88 lines
3.6 KiB
HTML
88 lines
3.6 KiB
HTML
<!doctype html>
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<html lang="en">
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<head>
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<meta charset="utf-8">
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<meta name="viewport" content="width=device-width, initial-scale=1">
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<title>AERIS-10 Engineering Docs</title>
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<link rel="stylesheet" href="assets/style.css">
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</head>
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<body>
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<header class="topbar">
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<div class="container nav">
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<a class="brand" href="index.html">AERIS-10 Docs</a>
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<nav>
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<a href="architecture.html">Architecture</a>
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<a href="implementation-log.html">Implementation Log</a>
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<a href="bring-up.html">Bring-Up</a>
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<a href="reports.html">Reports</a>
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<a href="release-notes.html">Release Notes</a>
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</nav>
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</div>
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</header>
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<main class="container page">
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<section class="hero">
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<p class="eyebrow">Open-Source Phased Array Radar</p>
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<h1>Engineering Documentation Site</h1>
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<p>This site tracks architecture, validated implementation baselines, constraint cleanup progress, and pre-hardware bring-up readiness for AERIS-10.</p>
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<div class="cta-row">
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<a class="button" href="implementation-log.html">View Change Timeline</a>
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<a class="button ghost" href="bring-up.html">Open Readiness Package</a>
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</div>
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</section>
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<section class="stats-grid">
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<article class="card stat">
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<h2>Tracked Timing Baseline</h2>
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<p class="metric">WNS +0.058 ns</p>
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<p class="muted">WHS +0.068, WPWS +0.684 after validated Build 16 XDC port</p>
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</article>
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<article class="card stat">
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<h2>Regression Status</h2>
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<p class="metric">MCU 15 / 15, FPGA 18 / 18</p>
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<p class="muted">Host firmware regression plus FPGA unit and integration suites passing</p>
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</article>
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<article class="card stat">
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<h2>Methodology State</h2>
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<p class="metric">XDCB-5 = 0</p>
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<p class="muted">Single documented TIMING-18 residue on `ft601_txe` async observation</p>
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</article>
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<article class="card stat">
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<h2>Current Phase</h2>
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<p class="metric">Pre-Hardware Readiness</p>
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<p class="muted">Board-arrival smoke test, artifact inventory, and open-risk tracking prepared</p>
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</article>
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</section>
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<section class="grid-2">
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<article class="card">
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<h2>What changed recently</h2>
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<ul>
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<li>Ported the validated Build 16 production-target XDC cleanup into the tracked repository.</li>
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<li>Preserved positive post-route timing while clearing XDCB-5 and reducing methodology residue to a single documented item.</li>
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<li>Validated the tracked branch with MCU host regression and FPGA regression/integration suites.</li>
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<li>Refreshed the bring-up documentation into a pre-arrival readiness package for the FPGA module and carrier board.</li>
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<li>Kept upstream ADAR1000 bulk imports out of the baseline pending selective, justified reuse only.</li>
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</ul>
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</article>
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<article class="card">
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<h2>Documentation Map</h2>
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<ul>
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<li><a href="architecture.html">System and FPGA Architecture</a></li>
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<li><a href="implementation-log.html">Detailed Engineering Change Log</a></li>
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<li><a href="bring-up.html">Pre-Arrival Bring-Up Plan, Artifact Checklist, and Open Risks</a></li>
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<li><a href="reports.html">Published reports, simulations, and artifact context</a></li>
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<li><a href="release-notes.html">Release Notes by Key Commit</a></li>
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</ul>
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</article>
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</section>
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</main>
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<footer class="footer">
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<div class="container">
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<p>AERIS-10 documentation published via GitHub Pages from <code>/docs</code>.</p>
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</div>
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</footer>
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</body>
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</html>
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