Jason
34 lines
966 B
Markdown
34 lines
966 B
Markdown
<!doctype markdown>
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# TE0713/TE0701 heartbeat bring-up artifact
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- Date: 2026-03-21
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- Target: Trenz `TE0713-03-82C46-A` on `TE0701-06`
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- Top module: `radar_system_top_te0713_dev`
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- Constraint file: `9_Firmware/9_2_FPGA/constraints/te0713_te0701_minimal.xdc`
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- Bitstream: `docs/artifacts/te0713-te0701-heartbeat-2026-03-21.bit`
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Build result:
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- Vivado: `2025.2`
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- Implementation: `write_bitstream Complete!`
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- DRC: `0 Errors`
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- WNS: `+17.863 ns`
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- WHS: `+0.265 ns`
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Purpose:
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- Lowest-risk first-power image for `TE0713 + TE0701`
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- Verifies FPGA configuration, primary clock path, and heartbeat/status outputs before FT601 or radar-path bring-up
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Board-day usage:
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- Program this image first
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- Confirm JTAG enumeration and successful configuration
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- Verify heartbeat/status activity before moving to FT601 or higher-risk integrations
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Build origin:
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- Built remotely on `livepeerservice.ddns.net`
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- Vivado path: `/mnt/bcache/Xilinx/Vivado/2025.2/Vivado/bin/vivado`
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