Jason
e9705e40b7
Complete cross-layer upgrade from 1024-pt/64-bin to 2048-pt/512-bin FFT: FPGA RTL (14+ modules): - radar_params.vh: FFT_SIZE=2048, RANGE_BINS=512, 9-bit range, 6-bit stream - fft_engine.v: 2048-pt FFT with XPM BRAM - chirp_memory_loader_param.v: 2 segments x 2048 (was 4 x 1024) - matched_filter_multi_segment.v: BRAM inference for overlap_cache, explicit ov_waddr - mti_canceller.v: BRAM inference for prev_i/q arrays (was fabric FFs) - doppler_processor.v: 16384-deep memory, 14-bit addressing - cfar_ca.v: 512 rows, indentation fix - radar_receiver_final.v: rising-edge detector for frame_complete, 11-bit sample_addr - range_bin_decimator.v: 512 output bins - usb_data_interface_ft2232h.v: bulk per-frame with Manhattan magnitude - radar_mode_controller.v: XOR edge detector for toggle signals - rx_gain_control.v: updated for new bin count Python GUI + Protocol (8 files): - radar_protocol.py: 512-bin bulk frame parser, LSB-first bitmap - GUI_V65_Tk.py, v7/*.py: updated for 512 bins, 6m range resolution Golden data + tests: - All .hex/.csv/.npy golden references regenerated for 2048/512 - fft_twiddle_2048.mem added - Deleted stale seg2/seg3 chirp mem files - 9 new bulk frame cross-layer tests, deleted 6 stale per-sample tests - Deleted stale tb_cross_layer_ft2232h.v and dead contract_parser functions - Updated validate_mem_files.py for 2048/2-segment config MCU: RadarSettings.cpp max_distance/map_size 1536->3072 All 4 CI jobs pass: 285 tests, 0 failures, 0 skips
80 lines
2.6 KiB
Plaintext
80 lines
2.6 KiB
Plaintext
# Verilog simulation artifacts
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*.vvp
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*.vcd
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# Debug / scratch RTL (not part of the design)
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9_Firmware/9_2_FPGA/debug_*.v
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9_Firmware/9_2_FPGA/tb/tb_fft_debug*.v
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9_Firmware/9_2_FPGA/tb/tb_fft_mini*.v
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9_Firmware/9_2_FPGA/tb/tb_bram_debug.v
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# Local simulation artifacts and CSV outputs
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9_Firmware/9_2_FPGA/cic_*.csv
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9_Firmware/9_2_FPGA/fir_*.csv
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9_Firmware/9_2_FPGA/nco_*.csv
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9_Firmware/9_2_FPGA/ddc_*.csv
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9_Firmware/9_2_FPGA/mf_pipeline_output.csv
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9_Firmware/9_2_FPGA/mf_chain_autocorr.csv
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9_Firmware/9_2_FPGA/rbd_mode00_ramp.csv
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9_Firmware/9_2_FPGA/rbd_mode01_peak.csv
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9_Firmware/9_2_FPGA/rbd_mode10_avg.csv
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9_Firmware/9_2_FPGA/rbd_mode10_ramp.csv
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9_Firmware/9_2_FPGA/rmc_autoscan.csv
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9_Firmware/9_2_FPGA/tb/mf_chain_autocorr.csv
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9_Firmware/9_2_FPGA/tb/rbd_mode00_ramp.csv
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9_Firmware/9_2_FPGA/tb/rbd_mode01_peak.csv
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9_Firmware/9_2_FPGA/tb/rbd_mode10_avg.csv
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9_Firmware/9_2_FPGA/tb/rbd_mode10_ramp.csv
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9_Firmware/9_2_FPGA/tb/rmc_autoscan.csv
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9_Firmware/9_2_FPGA/tb_usb_data_interface.csv
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# Co-sim intermediate CSVs (regenerated by scripts)
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9_Firmware/9_2_FPGA/tb/cosim/rtl_doppler_*.csv
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9_Firmware/9_2_FPGA/tb/cosim/compare_doppler_*.csv
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9_Firmware/9_2_FPGA/tb/cosim/rtl_multiseg_*.csv
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9_Firmware/9_2_FPGA/tb/cosim/rx_final_doppler_out.csv
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9_Firmware/9_2_FPGA/tb/cosim/rtl_mf_*.csv
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9_Firmware/9_2_FPGA/tb/cosim/compare_mf_*.csv
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# Golden reference outputs (regenerated by testbenches)
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9_Firmware/9_2_FPGA/tb/golden/
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# macOS
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.DS_Store
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# Python
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__pycache__/
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*.pyc
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# Local organization/archival folders (not part of repo source)
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10_docs/
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# Local simulation workspaces and generated outputs
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5_Simulations/generated/
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5_Simulations/aeris10_antenna_sim.py
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5_Simulations/aeris10_radar_sim.py
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# Local FPGA report dumps and scratch constraints
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9_Firmware/9_2_FPGA/reports/
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9_Firmware/9_2_FPGA/synth_only.xdc
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# Local timing closure report snapshots
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build*_reports/
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# UART capture logs (generated by tools/uart_capture.py)
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logs/
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# Local schematic files
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# Schematic and board files (untracked)
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4_Schematics and Boards Layout/4_6_Schematics/FMC_TestBoard/*
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4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.kicad_sch
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4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.kicad_pcb
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4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.bak
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4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.tmp
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4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.net
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4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.dcm
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4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.svg
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4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.pdf
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4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.sch-bak
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4_Schematics and Boards Layout/4_6_Schematics/Main_Board/backup/
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